Source file src/cmd/internal/obj/loong64/asm.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  	"cmd/internal/objabi"
    10  	"fmt"
    11  	"log"
    12  	"math/bits"
    13  	"slices"
    14  )
    15  
    16  // ctxt0 holds state while assembling a single function.
    17  // Each function gets a fresh ctxt0.
    18  // This allows for multiple functions to be safely concurrently assembled.
    19  type ctxt0 struct {
    20  	ctxt       *obj.Link
    21  	newprog    obj.ProgAlloc
    22  	cursym     *obj.LSym
    23  	autosize   int32
    24  	instoffset int64
    25  	pc         int64
    26  }
    27  
    28  // Instruction layout.
    29  
    30  const (
    31  	FuncAlign = 4
    32  	loopAlign = 16
    33  )
    34  
    35  type Optab struct {
    36  	as    obj.As
    37  	from1 uint8
    38  	reg   uint8
    39  	from3 uint8
    40  	to1   uint8
    41  	to2   uint8
    42  	type_ int8
    43  	size  int8
    44  	param int16
    45  	flag  uint8
    46  }
    47  
    48  const (
    49  	NOTUSETMP = 1 << iota // p expands to multiple instructions, but does NOT use REGTMP
    50  
    51  	// branchLoopHead marks loop entry.
    52  	// Used to insert padding for under-aligned loops.
    53  	branchLoopHead
    54  )
    55  
    56  var optab = []Optab{
    57  	{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0},
    58  
    59  	{AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
    60  	{AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
    61  	{AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
    62  	{AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
    63  	{AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
    64  
    65  	{ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    66  	{ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    67  	{AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    68  	{AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    69  	{AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    70  	{ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    71  	{ASUBV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    72  	{AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    73  	{AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    74  	{AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    75  	{ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    76  	{ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    77  	{AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    78  	{ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    79  	{ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    80  	{ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    81  	{ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    82  	{AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    83  	{AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    84  	{AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    85  	{AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    86  	{AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
    87  	{AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
    88  	{ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
    89  
    90  	{AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
    91  	{AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
    92  	{AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
    93  	{AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
    94  	{AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
    95  	{AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
    96  	{AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
    97  	{AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
    98  
    99  	{AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   100  	{AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   101  	{AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   102  	{AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   103  
   104  	{AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   105  	{AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   106  	{AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   107  	{AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   108  	{AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
   109  	{AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
   110  	{AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
   111  	{AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
   112  
   113  	{AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   114  	{AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   115  	{AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   116  	{AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   117  	{AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
   118  	{AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
   119  	{AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
   120  	{AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
   121  
   122  	{AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   123  	{AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   124  	{AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   125  	{AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   126  	{AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
   127  	{AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
   128  	{AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
   129  	{AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
   130  
   131  	{AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   132  	{AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   133  	{AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   134  	{AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   135  	{AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
   136  	{AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
   137  	{AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
   138  	{AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
   139  
   140  	{ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
   141  	{AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   142  	{AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   143  	{AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   144  	{AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   145  	{AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0},
   146  	{AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0},
   147  	{AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
   148  	{AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
   149  
   150  	{AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
   151  	{AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
   152  
   153  	{AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   154  	{AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   155  	{AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   156  	{AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   157  	{AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   158  	{AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   159  	{AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   160  	{AMOVV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   161  	{AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   162  	{AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   163  	{AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   164  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   165  	{AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
   166  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
   167  	{ASC, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   168  	{ASCV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   169  
   170  	{AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   171  	{AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   172  	{AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   173  	{AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   174  	{AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   175  	{AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   176  	{AMOVWU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   177  	{AMOVV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   178  	{AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   179  	{AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   180  	{AVMOVQ, C_SOREG, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
   181  	{AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
   182  	{AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
   183  	{AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
   184  	{ALL, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   185  	{ALLV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   186  
   187  	{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   188  	{AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   189  	{AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   190  	{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   191  	{AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   192  	{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   193  	{AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   194  	{AMOVV, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   195  	{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   196  	{AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   197  	{ASC, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   198  	{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   199  	{AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   200  	{AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   201  	{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   202  	{AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   203  	{AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   204  	{AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   205  	{AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   206  	{AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   207  	{AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   208  
   209  	{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   210  	{AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   211  	{AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   212  	{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   213  	{AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   214  	{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   215  	{AMOVWU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   216  	{AMOVV, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   217  	{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   218  	{AMOVBU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   219  	{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   220  	{AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   221  	{AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   222  	{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   223  	{AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   224  	{AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   225  	{AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   226  	{AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   227  	{AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   228  	{AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   229  
   230  	{AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
   231  	{AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
   232  	{AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
   233  	{AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
   234  
   235  	{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
   236  	{AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
   237  	{AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
   238  	{AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
   239  
   240  	{AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
   241  	{AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
   242  	{AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
   243  	{AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
   244  	{AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP},
   245  	{AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP},
   246  	{AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP},
   247  	{AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
   248  
   249  	{AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   250  	{AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   251  	{AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   252  	{AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   253  
   254  	{AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   255  	{AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   256  	{AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   257  	{AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   258  
   259  	{AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   260  	{AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   261  	{AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   262  	{AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   263  
   264  	{AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   265  	{AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   266  	{AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   267  	{AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   268  	{AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   269  	{AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   270  
   271  	{AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   272  	{AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   273  	{AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   274  	{AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   275  	{AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   276  	{AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   277  
   278  	{AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   279  	{AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   280  	{AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   281  	{AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   282  	{AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   283  	{AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   284  	{AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   285  	{AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   286  	{AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   287  	{AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   288  	{AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   289  	{AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   290  	{AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   291  	{AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   292  	{AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   293  	{AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   294  
   295  	{ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   296  	{ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   297  
   298  	{ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   299  	{ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   300  
   301  	{ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0},
   302  	{ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
   303  	{ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
   304  
   305  	{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
   306  	{ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
   307  
   308  	{ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   309  	{ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   310  	{ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   311  	{ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   312  	{ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   313  
   314  	{AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // b
   315  	{AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // bl
   316  
   317  	{AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0}, // jirl r0, rj, 0
   318  	{AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0}, // jirl r1, rj, 0
   319  
   320  	{AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
   321  	{AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
   322  	{AMOVF, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
   323  	{AMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
   324  
   325  	{AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
   326  	{AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
   327  	{AMOVF, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
   328  	{AMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
   329  	{AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
   330  	{AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
   331  
   332  	{AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
   333  	{AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
   334  	{AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
   335  	{AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
   336  
   337  	{AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
   338  	{AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
   339  	{AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
   340  	{AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
   341  	{AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   342  	{AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   343  
   344  	{AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
   345  	{AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
   346  	{AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   347  	{AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   348  	{AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   349  	{AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   350  	{AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
   351  	{AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0},
   352  	{AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
   353  	{AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
   354  
   355  	{AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0},
   356  
   357  	{AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   358  	{AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   359  	{AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   360  	{AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   361  	{AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   362  
   363  	{AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   364  	{AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   365  	{AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   366  	{AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   367  	{AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   368  
   369  	{AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0},
   370  	{AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0},
   371  
   372  	{AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0},
   373  
   374  	{ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
   375  	{ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
   376  
   377  	{ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
   378  	{AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
   379  	{ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
   380  
   381  	/* store with extended register offset */
   382  	{AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   383  	{AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   384  	{AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   385  	{AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   386  	{AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   387  	{AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   388  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   389  
   390  	/* load with extended register offset */
   391  	{AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   392  	{AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   393  	{AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   394  	{AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   395  	{AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   396  	{AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
   397  	{AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
   398  	{AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0},
   399  	{AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0},
   400  
   401  	{AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
   402  	{AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
   403  	{AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
   404  	{AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
   405  
   406  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0},
   407  	{AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0},
   408  
   409  	{AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
   410  	{AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
   411  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0},
   412  
   413  	{AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
   414  
   415  	{obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   416  	{obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
   417  	{obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
   418  	{obj.AFUNCDATA, C_U12CON, C_NONE, C_NONE, C_ADDR, C_NONE, 0, 0, 0, 0},
   419  	{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   420  	{obj.ANOP, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0}, // nop variants, see #40689
   421  	{obj.ANOP, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},  // nop variants, see #40689
   422  	{obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   423  	{obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   424  	{obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // same as AJMP
   425  	{obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // same as AJMP
   426  
   427  	{obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0, 0},
   428  }
   429  
   430  var atomicInst = map[obj.As]uint32{
   431  	AAMSWAPB:   0x070B8 << 15, // amswap.b
   432  	AAMSWAPH:   0x070B9 << 15, // amswap.h
   433  	AAMSWAPW:   0x070C0 << 15, // amswap.w
   434  	AAMSWAPV:   0x070C1 << 15, // amswap.d
   435  	AAMCASB:    0x070B0 << 15, // amcas.b
   436  	AAMCASH:    0x070B1 << 15, // amcas.h
   437  	AAMCASW:    0x070B2 << 15, // amcas.w
   438  	AAMCASV:    0x070B3 << 15, // amcas.d
   439  	AAMADDW:    0x070C2 << 15, // amadd.w
   440  	AAMADDV:    0x070C3 << 15, // amadd.d
   441  	AAMANDW:    0x070C4 << 15, // amand.w
   442  	AAMANDV:    0x070C5 << 15, // amand.d
   443  	AAMORW:     0x070C6 << 15, // amor.w
   444  	AAMORV:     0x070C7 << 15, // amor.d
   445  	AAMXORW:    0x070C8 << 15, // amxor.w
   446  	AAMXORV:    0x070C9 << 15, // amxor.d
   447  	AAMMAXW:    0x070CA << 15, // ammax.w
   448  	AAMMAXV:    0x070CB << 15, // ammax.d
   449  	AAMMINW:    0x070CC << 15, // ammin.w
   450  	AAMMINV:    0x070CD << 15, // ammin.d
   451  	AAMMAXWU:   0x070CE << 15, // ammax.wu
   452  	AAMMAXVU:   0x070CF << 15, // ammax.du
   453  	AAMMINWU:   0x070D0 << 15, // ammin.wu
   454  	AAMMINVU:   0x070D1 << 15, // ammin.du
   455  	AAMSWAPDBB: 0x070BC << 15, // amswap_db.b
   456  	AAMSWAPDBH: 0x070BD << 15, // amswap_db.h
   457  	AAMSWAPDBW: 0x070D2 << 15, // amswap_db.w
   458  	AAMSWAPDBV: 0x070D3 << 15, // amswap_db.d
   459  	AAMCASDBB:  0x070B4 << 15, // amcas_db.b
   460  	AAMCASDBH:  0x070B5 << 15, // amcas_db.h
   461  	AAMCASDBW:  0x070B6 << 15, // amcas_db.w
   462  	AAMCASDBV:  0x070B7 << 15, // amcas_db.d
   463  	AAMADDDBW:  0x070D4 << 15, // amadd_db.w
   464  	AAMADDDBV:  0x070D5 << 15, // amadd_db.d
   465  	AAMANDDBW:  0x070D6 << 15, // amand_db.w
   466  	AAMANDDBV:  0x070D7 << 15, // amand_db.d
   467  	AAMORDBW:   0x070D8 << 15, // amor_db.w
   468  	AAMORDBV:   0x070D9 << 15, // amor_db.d
   469  	AAMXORDBW:  0x070DA << 15, // amxor_db.w
   470  	AAMXORDBV:  0x070DB << 15, // amxor_db.d
   471  	AAMMAXDBW:  0x070DC << 15, // ammax_db.w
   472  	AAMMAXDBV:  0x070DD << 15, // ammax_db.d
   473  	AAMMINDBW:  0x070DE << 15, // ammin_db.w
   474  	AAMMINDBV:  0x070DF << 15, // ammin_db.d
   475  	AAMMAXDBWU: 0x070E0 << 15, // ammax_db.wu
   476  	AAMMAXDBVU: 0x070E1 << 15, // ammax_db.du
   477  	AAMMINDBWU: 0x070E2 << 15, // ammin_db.wu
   478  	AAMMINDBVU: 0x070E3 << 15, // ammin_db.du
   479  }
   480  
   481  func IsAtomicInst(as obj.As) bool {
   482  	_, ok := atomicInst[as]
   483  
   484  	return ok
   485  }
   486  
   487  // pcAlignPadLength returns the number of bytes required to align pc to alignedValue,
   488  // reporting an error if alignedValue is not a power of two or is out of range.
   489  func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
   490  	if !((alignedValue&(alignedValue-1) == 0) && 8 <= alignedValue && alignedValue <= 2048) {
   491  		ctxt.Diag("alignment value of an instruction must be a power of two and in the range [8, 2048], got %d\n", alignedValue)
   492  	}
   493  	return int(-pc & (alignedValue - 1))
   494  }
   495  
   496  var oprange [ALAST & obj.AMask][]Optab
   497  
   498  var xcmp [C_NCLASS][C_NCLASS]bool
   499  
   500  func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
   501  	if ctxt.Retpoline {
   502  		ctxt.Diag("-spectre=ret not supported on loong64")
   503  		ctxt.Retpoline = false // don't keep printing
   504  	}
   505  
   506  	p := cursym.Func().Text
   507  	if p == nil || p.Link == nil { // handle external functions and ELF section symbols
   508  		return
   509  	}
   510  
   511  	c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset + ctxt.Arch.FixedFrameSize)}
   512  
   513  	if oprange[AOR&obj.AMask] == nil {
   514  		c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
   515  	}
   516  
   517  	pc := int64(0)
   518  	p.Pc = pc
   519  
   520  	var m int
   521  	var o *Optab
   522  	for p = p.Link; p != nil; p = p.Link {
   523  		p.Pc = pc
   524  		o = c.oplook(p)
   525  		m = int(o.size)
   526  		if m == 0 {
   527  			switch p.As {
   528  			case obj.APCALIGN:
   529  				alignedValue := p.From.Offset
   530  				m = pcAlignPadLength(ctxt, pc, alignedValue)
   531  				// Update the current text symbol alignment value.
   532  				if int32(alignedValue) > cursym.Func().Align {
   533  					cursym.Func().Align = int32(alignedValue)
   534  				}
   535  				break
   536  			case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
   537  				continue
   538  			default:
   539  				c.ctxt.Diag("zero-width instruction\n%v", p)
   540  			}
   541  		}
   542  
   543  		pc += int64(m)
   544  	}
   545  
   546  	c.cursym.Size = pc
   547  
   548  	// mark loop entry instructions for padding
   549  	// loop entrances are defined as targets of backward branches
   550  	for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
   551  		if q := p.To.Target(); q != nil && q.Pc < p.Pc {
   552  			q.Mark |= branchLoopHead
   553  		}
   554  	}
   555  
   556  	// Run these passes until convergence.
   557  	for {
   558  		rescan := false
   559  		pc = 0
   560  		prev := c.cursym.Func().Text
   561  		for p = prev.Link; p != nil; prev, p = p, p.Link {
   562  			p.Pc = pc
   563  			o = c.oplook(p)
   564  
   565  			// Prepend a PCALIGN $loopAlign to each of the loop heads
   566  			// that need padding, if not already done so (because this
   567  			// pass may execute more than once).
   568  			//
   569  			// This needs to come before any pass that look at pc,
   570  			// because pc will be adjusted if padding happens.
   571  			if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 &&
   572  				!(prev.As == obj.APCALIGN && prev.From.Offset >= loopAlign) {
   573  				q := c.newprog()
   574  				prev.Link = q
   575  				q.Link = p
   576  				q.Pc = pc
   577  				q.As = obj.APCALIGN
   578  				q.From.Type = obj.TYPE_CONST
   579  				q.From.Offset = loopAlign
   580  				// Don't associate the synthesized PCALIGN with
   581  				// the original source position, for deterministic
   582  				// mapping between source and corresponding asm.
   583  				// q.Pos = p.Pos
   584  
   585  				// Manually make the PCALIGN come into effect,
   586  				// since this loop iteration is for p.
   587  				pc += int64(pcAlignPadLength(ctxt, pc, loopAlign))
   588  				p.Pc = pc
   589  				rescan = true
   590  			}
   591  
   592  			// very large conditional branches
   593  			//
   594  			// if any procedure is large enough to generate a large SBRA branch, then
   595  			// generate extra passes putting branches around jmps to fix. this is rare.
   596  			if o.type_ == 6 && p.To.Target() != nil {
   597  				otxt := p.To.Target().Pc - pc
   598  
   599  				// On loong64, the immediate value field of the conditional branch instructions
   600  				// BFPT and BFPT is 21 bits, and the others are 16 bits. The jump target address
   601  				// is to logically shift the immediate value in the instruction code to the left
   602  				// by 2 bits and then sign extend.
   603  				bound := int64(1 << (18 - 1))
   604  
   605  				switch p.As {
   606  				case ABFPT, ABFPF:
   607  					bound = int64(1 << (23 - 1))
   608  				}
   609  
   610  				if otxt < -bound || otxt >= bound {
   611  					q := c.newprog()
   612  					q.Link = p.Link
   613  					p.Link = q
   614  					q.As = AJMP
   615  					q.Pos = p.Pos
   616  					q.To.Type = obj.TYPE_BRANCH
   617  					q.To.SetTarget(p.To.Target())
   618  					p.To.SetTarget(q)
   619  					q = c.newprog()
   620  					q.Link = p.Link
   621  					p.Link = q
   622  					q.As = AJMP
   623  					q.Pos = p.Pos
   624  					q.To.Type = obj.TYPE_BRANCH
   625  					q.To.SetTarget(q.Link.Link)
   626  					rescan = true
   627  				}
   628  			}
   629  
   630  			m = int(o.size)
   631  			if m == 0 {
   632  				switch p.As {
   633  				case obj.APCALIGN:
   634  					alignedValue := p.From.Offset
   635  					m = pcAlignPadLength(ctxt, pc, alignedValue)
   636  					break
   637  				case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
   638  					continue
   639  				default:
   640  					c.ctxt.Diag("zero-width instruction\n%v", p)
   641  				}
   642  			}
   643  
   644  			pc += int64(m)
   645  		}
   646  
   647  		c.cursym.Size = pc
   648  
   649  		if !rescan {
   650  			break
   651  		}
   652  	}
   653  
   654  	pc += -pc & (FuncAlign - 1)
   655  	c.cursym.Size = pc
   656  
   657  	// lay out the code, emitting code and data relocations.
   658  
   659  	c.cursym.Grow(c.cursym.Size)
   660  
   661  	bp := c.cursym.P
   662  	var i int32
   663  	var out [5]uint32
   664  	for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
   665  		c.pc = p.Pc
   666  		o = c.oplook(p)
   667  		if int(o.size) > 4*len(out) {
   668  			log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
   669  		}
   670  		if p.As == obj.APCALIGN {
   671  			alignedValue := p.From.Offset
   672  			v := pcAlignPadLength(c.ctxt, p.Pc, alignedValue)
   673  			for i = 0; i < int32(v/4); i++ {
   674  				// emit ANOOP instruction by the padding size
   675  				c.ctxt.Arch.ByteOrder.PutUint32(bp, OP_12IRR(c.opirr(AAND), 0, 0, 0))
   676  				bp = bp[4:]
   677  			}
   678  			continue
   679  		}
   680  		c.asmout(p, o, out[:])
   681  		for i = 0; i < int32(o.size/4); i++ {
   682  			c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
   683  			bp = bp[4:]
   684  		}
   685  	}
   686  
   687  	// Mark nonpreemptible instruction sequences.
   688  	// We use REGTMP as a scratch register during call injection,
   689  	// so instruction sequences that use REGTMP are unsafe to
   690  	// preempt asynchronously.
   691  	obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, c.isRestartable)
   692  }
   693  
   694  // isUnsafePoint returns whether p is an unsafe point.
   695  func (c *ctxt0) isUnsafePoint(p *obj.Prog) bool {
   696  	// If p explicitly uses REGTMP, it's unsafe to preempt, because the
   697  	// preemption sequence clobbers REGTMP.
   698  	return p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP
   699  }
   700  
   701  // isRestartable returns whether p is a multi-instruction sequence that,
   702  // if preempted, can be restarted.
   703  func (c *ctxt0) isRestartable(p *obj.Prog) bool {
   704  	if c.isUnsafePoint(p) {
   705  		return false
   706  	}
   707  	// If p is a multi-instruction sequence with uses REGTMP inserted by
   708  	// the assembler in order to materialize a large constant/offset, we
   709  	// can restart p (at the start of the instruction sequence), recompute
   710  	// the content of REGTMP, upon async preemption. Currently, all cases
   711  	// of assembler-inserted REGTMP fall into this category.
   712  	// If p doesn't use REGTMP, it can be simply preempted, so we don't
   713  	// mark it.
   714  	o := c.oplook(p)
   715  	return o.size > 4 && o.flag&NOTUSETMP == 0
   716  }
   717  
   718  func isint32(v int64) bool {
   719  	return int64(int32(v)) == v
   720  }
   721  
   722  func isuint32(v uint64) bool {
   723  	return uint64(uint32(v)) == v
   724  }
   725  
   726  func (c *ctxt0) aclass(a *obj.Addr) int {
   727  	switch a.Type {
   728  	case obj.TYPE_NONE:
   729  		return C_NONE
   730  
   731  	case obj.TYPE_REG:
   732  		return c.rclass(a.Reg)
   733  
   734  	case obj.TYPE_MEM:
   735  		switch a.Name {
   736  		case obj.NAME_EXTERN,
   737  			obj.NAME_STATIC:
   738  			if a.Sym == nil {
   739  				break
   740  			}
   741  			c.instoffset = a.Offset
   742  			if a.Sym.Type == objabi.STLSBSS {
   743  				if c.ctxt.Flag_shared {
   744  					return C_TLS_IE
   745  				} else {
   746  					return C_TLS_LE
   747  				}
   748  			}
   749  			return C_ADDR
   750  
   751  		case obj.NAME_AUTO:
   752  			if a.Reg == REGSP {
   753  				// unset base register for better printing, since
   754  				// a.Offset is still relative to pseudo-SP.
   755  				a.Reg = obj.REG_NONE
   756  			}
   757  			c.instoffset = int64(c.autosize) + a.Offset
   758  			if c.instoffset >= -BIG && c.instoffset < BIG {
   759  				return C_SAUTO
   760  			}
   761  			return C_LAUTO
   762  
   763  		case obj.NAME_PARAM:
   764  			if a.Reg == REGSP {
   765  				// unset base register for better printing, since
   766  				// a.Offset is still relative to pseudo-FP.
   767  				a.Reg = obj.REG_NONE
   768  			}
   769  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   770  			if c.instoffset >= -BIG && c.instoffset < BIG {
   771  				return C_SAUTO
   772  			}
   773  			return C_LAUTO
   774  
   775  		case obj.NAME_NONE:
   776  			if a.Index != 0 {
   777  				if a.Offset != 0 {
   778  					return C_GOK
   779  				}
   780  				// register offset
   781  				return C_ROFF
   782  			}
   783  
   784  			c.instoffset = a.Offset
   785  			if c.instoffset == 0 {
   786  				return C_ZOREG
   787  			}
   788  			if c.instoffset >= -BIG && c.instoffset < BIG {
   789  				return C_SOREG
   790  			}
   791  			return C_LOREG
   792  
   793  		case obj.NAME_GOTREF:
   794  			return C_GOTADDR
   795  		}
   796  
   797  		return C_GOK
   798  
   799  	case obj.TYPE_TEXTSIZE:
   800  		return C_TEXTSIZE
   801  
   802  	case obj.TYPE_CONST,
   803  		obj.TYPE_ADDR:
   804  		switch a.Name {
   805  		case obj.NAME_NONE:
   806  			c.instoffset = a.Offset
   807  			if a.Reg != 0 {
   808  				if -BIG <= c.instoffset && c.instoffset <= BIG {
   809  					return C_SACON
   810  				}
   811  				if isint32(c.instoffset) {
   812  					return C_LACON
   813  				}
   814  				return C_DACON
   815  			}
   816  
   817  		case obj.NAME_EXTERN,
   818  			obj.NAME_STATIC:
   819  			s := a.Sym
   820  			if s == nil {
   821  				return C_GOK
   822  			}
   823  
   824  			c.instoffset = a.Offset
   825  			if s.Type == objabi.STLSBSS {
   826  				c.ctxt.Diag("taking address of TLS variable is not supported")
   827  			}
   828  			return C_EXTADDR
   829  
   830  		case obj.NAME_AUTO:
   831  			if a.Reg == REGSP {
   832  				// unset base register for better printing, since
   833  				// a.Offset is still relative to pseudo-SP.
   834  				a.Reg = obj.REG_NONE
   835  			}
   836  			c.instoffset = int64(c.autosize) + a.Offset
   837  			if c.instoffset >= -BIG && c.instoffset < BIG {
   838  				return C_SACON
   839  			}
   840  			return C_LACON
   841  
   842  		case obj.NAME_PARAM:
   843  			if a.Reg == REGSP {
   844  				// unset base register for better printing, since
   845  				// a.Offset is still relative to pseudo-FP.
   846  				a.Reg = obj.REG_NONE
   847  			}
   848  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   849  			if c.instoffset >= -BIG && c.instoffset < BIG {
   850  				return C_SACON
   851  			}
   852  			return C_LACON
   853  
   854  		default:
   855  			return C_GOK
   856  		}
   857  
   858  		if c.instoffset != int64(int32(c.instoffset)) {
   859  			return dconClass(c.instoffset)
   860  		}
   861  
   862  		if c.instoffset >= 0 {
   863  			sbits := bits.Len64(uint64(c.instoffset))
   864  			switch {
   865  			case sbits <= 8:
   866  				return C_ZCON + sbits
   867  			case sbits <= 12:
   868  				if c.instoffset <= 0x7ff {
   869  					return C_US12CON
   870  				}
   871  				return C_U12CON
   872  			case sbits <= 13:
   873  				if c.instoffset&0xfff == 0 {
   874  					return C_U13CON20_0
   875  				}
   876  				return C_U13CON
   877  			case sbits <= 15:
   878  				if c.instoffset&0xfff == 0 {
   879  					return C_U15CON20_0
   880  				}
   881  				return C_U15CON
   882  			}
   883  		} else {
   884  			sbits := bits.Len64(uint64(^c.instoffset))
   885  			switch {
   886  			case sbits < 5:
   887  				return C_S5CON
   888  			case sbits < 12:
   889  				return C_S12CON
   890  			case sbits < 13:
   891  				if c.instoffset&0xfff == 0 {
   892  					return C_S13CON20_0
   893  				}
   894  				return C_S13CON
   895  			}
   896  		}
   897  
   898  		if c.instoffset&0xfff == 0 {
   899  			return C_32CON20_0
   900  		}
   901  		return C_32CON
   902  
   903  	case obj.TYPE_BRANCH:
   904  		return C_BRAN
   905  	}
   906  
   907  	return C_GOK
   908  }
   909  
   910  // The constants here define the data characteristics within the bit field range.
   911  //
   912  //	ALL1: The data in the bit field is all 1
   913  //	ALL0: The data in the bit field is all 0
   914  //	ST1: The data in the bit field starts with 1, but not all 1
   915  //	ST0: The data in the bit field starts with 0, but not all 0
   916  const (
   917  	ALL1 = iota
   918  	ALL0
   919  	ST1
   920  	ST0
   921  )
   922  
   923  // mask returns the mask of the specified bit field, which is used to help determine
   924  // the data characteristics of the immediate value at the specified bit.
   925  func mask(suf int8, len int8) (uint64, uint64) {
   926  	if len == 12 {
   927  		if suf == 0 {
   928  			return 0xfff, 0x800
   929  		} else { // suf == 52
   930  			return 0xfff0000000000000, 0x8000000000000000
   931  		}
   932  	} else { // len == 20
   933  		if suf == 12 {
   934  			return 0xfffff000, 0x80000000
   935  		} else { // suf == 32
   936  			return 0xfffff00000000, 0x8000000000000
   937  		}
   938  	}
   939  }
   940  
   941  // bitField return a number represent status of val in bit field
   942  //
   943  //	suf: The starting bit of the bit field
   944  //	len: The length of the bit field
   945  func bitField(val int64, suf int8, len int8) int8 {
   946  	mask1, mask2 := mask(suf, len)
   947  	if uint64(val)&mask1 == mask1 {
   948  		return ALL1
   949  	} else if uint64(val)&mask1 == 0x0 {
   950  		return ALL0
   951  	} else if uint64(val)&mask2 == mask2 {
   952  		return ST1
   953  	} else {
   954  		return ST0
   955  	}
   956  }
   957  
   958  // Loading an immediate value larger than 32 bits requires four instructions
   959  // on loong64 (lu12i.w + ori + lu32i.d + lu52i.d), but in some special cases,
   960  // we can use the sign extension and zero extension features of the instruction
   961  // to fill in the high-order data (all 0 or all 1), which can save one to
   962  // three instructions.
   963  //
   964  //	| 63 ~ 52 | 51 ~ 32 | 31 ~ 12 | 11 ~ 0 |
   965  //	| lu52i.d | lu32i.d | lu12i.w |   ori  |
   966  func dconClass(offset int64) int {
   967  	tzb := bits.TrailingZeros64(uint64(offset))
   968  	hi12 := bitField(offset, 52, 12)
   969  	hi20 := bitField(offset, 32, 20)
   970  	lo20 := bitField(offset, 12, 20)
   971  	lo12 := bitField(offset, 0, 12)
   972  	if tzb >= 52 {
   973  		return C_DCON12_0 // lu52i.d
   974  	}
   975  	if tzb >= 32 {
   976  		if ((hi20 == ALL1 || hi20 == ST1) && hi12 == ALL1) || ((hi20 == ALL0 || hi20 == ST0) && hi12 == ALL0) {
   977  			return C_DCON20S_0 // addi.w + lu32i.d
   978  		}
   979  		return C_DCON32_0 // addi.w + lu32i.d + lu52i.d
   980  	}
   981  	if tzb >= 12 {
   982  		if lo20 == ST1 || lo20 == ALL1 {
   983  			if hi20 == ALL1 {
   984  				return C_DCON12_20S // lu12i.w + lu52i.d
   985  			}
   986  			if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
   987  				return C_DCON20S_20 // lu12i.w + lu32i.d
   988  			}
   989  			return C_DCON32_20 // lu12i.w + lu32i.d + lu52i.d
   990  		}
   991  		if hi20 == ALL0 {
   992  			return C_DCON12_20S // lu12i.w + lu52i.d
   993  		}
   994  		if (hi20 == ST0 && hi12 == ALL0) || ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) {
   995  			return C_DCON20S_20 // lu12i.w + lu32i.d
   996  		}
   997  		return C_DCON32_20 // lu12i.w + lu32i.d + lu52i.d
   998  	}
   999  	if lo12 == ST1 || lo12 == ALL1 {
  1000  		if lo20 == ALL1 {
  1001  			if hi20 == ALL1 {
  1002  				return C_DCON12_12S // addi.d + lu52i.d
  1003  			}
  1004  			if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
  1005  				return C_DCON20S_12S // addi.w + lu32i.d
  1006  			}
  1007  			return C_DCON32_12S // addi.w + lu32i.d + lu52i.d
  1008  		}
  1009  		if lo20 == ST1 {
  1010  			if hi20 == ALL1 {
  1011  
  1012  				return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1013  			}
  1014  			if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
  1015  				return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1016  			}
  1017  			return C_DCON // lu12i.w + ori + lu32i.d + lu52i.d
  1018  		}
  1019  		if lo20 == ALL0 {
  1020  			if hi20 == ALL0 {
  1021  				return C_DCON12_12U // ori + lu52i.d
  1022  			}
  1023  			if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1024  				return C_DCON20S_12U // ori + lu32i.d
  1025  			}
  1026  			return C_DCON32_12U // ori + lu32i.d + lu52i.d
  1027  		}
  1028  		if hi20 == ALL0 {
  1029  			return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1030  		}
  1031  		if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1032  			return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1033  		}
  1034  		return C_DCON // lu12i.w + ori + lu32i.d + lu52i.d
  1035  	}
  1036  	if lo20 == ALL0 {
  1037  		if hi20 == ALL0 {
  1038  			return C_DCON12_12U // ori + lu52i.d
  1039  		}
  1040  		if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1041  			return C_DCON20S_12U // ori + lu32i.d
  1042  		}
  1043  		return C_DCON32_12U // ori + lu32i.d + lu52i.d
  1044  	}
  1045  	if lo20 == ST1 || lo20 == ALL1 {
  1046  		if hi20 == ALL1 {
  1047  			return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1048  		}
  1049  		if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
  1050  			return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1051  		}
  1052  		return C_DCON
  1053  	}
  1054  	if hi20 == ALL0 {
  1055  		return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1056  	}
  1057  	if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1058  		return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1059  	}
  1060  	return C_DCON
  1061  }
  1062  
  1063  // In Loong64，there are 8 CFRs, denoted as fcc0-fcc7.
  1064  // There are 4 FCSRs, denoted as fcsr0-fcsr3.
  1065  func (c *ctxt0) rclass(r int16) int {
  1066  	switch {
  1067  	case REG_R0 <= r && r <= REG_R31:
  1068  		return C_REG
  1069  	case REG_F0 <= r && r <= REG_F31:
  1070  		return C_FREG
  1071  	case REG_FCC0 <= r && r <= REG_FCC7:
  1072  		return C_FCCREG
  1073  	case REG_FCSR0 <= r && r <= REG_FCSR3:
  1074  		return C_FCSRREG
  1075  	case REG_V0 <= r && r <= REG_V31:
  1076  		return C_VREG
  1077  	case REG_X0 <= r && r <= REG_X31:
  1078  		return C_XREG
  1079  	case r >= REG_ARNG && r < REG_ELEM:
  1080  		return C_ARNG
  1081  	case r >= REG_ELEM && r < REG_ELEM_END:
  1082  		return C_ELEM
  1083  	}
  1084  
  1085  	return C_GOK
  1086  }
  1087  
  1088  func oclass(a *obj.Addr) int {
  1089  	return int(a.Class) - 1
  1090  }
  1091  
  1092  func prasm(p *obj.Prog) {
  1093  	fmt.Printf("%v\n", p)
  1094  }
  1095  
  1096  func (c *ctxt0) oplook(p *obj.Prog) *Optab {
  1097  	if oprange[AOR&obj.AMask] == nil {
  1098  		c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
  1099  	}
  1100  
  1101  	a1 := int(p.Optab)
  1102  	if a1 != 0 {
  1103  		return &optab[a1-1]
  1104  	}
  1105  
  1106  	// first source operand
  1107  	a1 = int(p.From.Class)
  1108  	if a1 == 0 {
  1109  		a1 = c.aclass(&p.From) + 1
  1110  		p.From.Class = int8(a1)
  1111  	}
  1112  	a1--
  1113  
  1114  	// first destination operand
  1115  	a4 := int(p.To.Class)
  1116  	if a4 == 0 {
  1117  		a4 = c.aclass(&p.To) + 1
  1118  		p.To.Class = int8(a4)
  1119  	}
  1120  	a4--
  1121  
  1122  	// 2nd source operand
  1123  	a2 := C_NONE
  1124  	if p.Reg != 0 {
  1125  		a2 = c.rclass(p.Reg)
  1126  	}
  1127  
  1128  	// 2nd destination operand
  1129  	a5 := C_NONE
  1130  	if p.RegTo2 != 0 {
  1131  		a5 = C_REG
  1132  	}
  1133  
  1134  	// 3rd source operand
  1135  	a3 := C_NONE
  1136  	if len(p.RestArgs) > 0 {
  1137  		a3 = int(p.RestArgs[0].Class)
  1138  		if a3 == 0 {
  1139  			a3 = c.aclass(&p.RestArgs[0].Addr) + 1
  1140  			p.RestArgs[0].Class = int8(a3)
  1141  		}
  1142  		a3--
  1143  	}
  1144  
  1145  	ops := oprange[p.As&obj.AMask]
  1146  	c1 := &xcmp[a1]
  1147  	c3 := &xcmp[a3]
  1148  	c4 := &xcmp[a4]
  1149  	for i := range ops {
  1150  		op := &ops[i]
  1151  		if (int(op.reg) == a2) && c3[op.from3] && c1[op.from1] && c4[op.to1] && (int(op.to2) == a5) {
  1152  			p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
  1153  			return op
  1154  		}
  1155  	}
  1156  
  1157  	c.ctxt.Diag("illegal combination %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5))
  1158  	prasm(p)
  1159  	// Turn illegal instruction into an UNDEF, avoid crashing in asmout.
  1160  	return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
  1161  }
  1162  
  1163  func cmp(a int, b int) bool {
  1164  	if a == b {
  1165  		return true
  1166  	}
  1167  	switch a {
  1168  	case C_DCON:
  1169  		return cmp(C_32CON, b) || cmp(C_DCON12_20S, b) || cmp(C_DCON32_12S, b) || b == C_DCON12_0
  1170  	case C_32CON:
  1171  		return cmp(C_32CON20_0, b) || cmp(C_U15CON, b) || cmp(C_13CON, b) || cmp(C_12CON, b)
  1172  	case C_32CON20_0:
  1173  		return b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_S13CON20_0 || b == C_ZCON
  1174  	case C_U15CON:
  1175  		return cmp(C_U12CON, b) || b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_U13CON
  1176  	case C_13CON:
  1177  		return cmp(C_U13CON, b) || cmp(C_S13CON, b)
  1178  	case C_U13CON:
  1179  		return cmp(C_12CON, b) || b == C_U13CON20_0
  1180  	case C_S13CON:
  1181  		return cmp(C_12CON, b) || b == C_S13CON20_0
  1182  	case C_12CON:
  1183  		return cmp(C_U12CON, b) || cmp(C_S12CON, b)
  1184  	case C_UU12CON:
  1185  		return cmp(C_U12CON, b)
  1186  	case C_U12CON:
  1187  		return cmp(C_U8CON, b) || b == C_US12CON
  1188  	case C_U8CON:
  1189  		return cmp(C_U7CON, b)
  1190  	case C_U7CON:
  1191  		return cmp(C_U6CON, b)
  1192  	case C_U6CON:
  1193  		return cmp(C_U5CON, b)
  1194  	case C_U5CON:
  1195  		return cmp(C_U4CON, b)
  1196  	case C_U4CON:
  1197  		return cmp(C_U3CON, b)
  1198  	case C_U3CON:
  1199  		return cmp(C_U2CON, b)
  1200  	case C_U2CON:
  1201  		return cmp(C_U1CON, b)
  1202  	case C_U1CON:
  1203  		return cmp(C_ZCON, b)
  1204  	case C_US12CON:
  1205  		return cmp(C_S12CON, b)
  1206  	case C_S12CON:
  1207  		return cmp(C_S5CON, b) || cmp(C_U8CON, b) || b == C_US12CON
  1208  	case C_S5CON:
  1209  		return cmp(C_ZCON, b) || cmp(C_U4CON, b)
  1210  
  1211  	case C_DCON12_20S:
  1212  		if b == C_DCON20S_20 || b == C_DCON12_12S ||
  1213  			b == C_DCON20S_12S || b == C_DCON12_12U ||
  1214  			b == C_DCON20S_12U || b == C_DCON20S_0 {
  1215  			return true
  1216  		}
  1217  
  1218  	case C_DCON32_12S:
  1219  		if b == C_DCON32_20 || b == C_DCON12_32S ||
  1220  			b == C_DCON20S_32 || b == C_DCON32_12U ||
  1221  			b == C_DCON32_0 {
  1222  			return true
  1223  		}
  1224  
  1225  	case C_LACON:
  1226  		return b == C_SACON
  1227  
  1228  	case C_LAUTO:
  1229  		return b == C_SAUTO
  1230  
  1231  	case C_REG:
  1232  		return b == C_ZCON
  1233  
  1234  	case C_LOREG:
  1235  		return b == C_ZOREG || b == C_SOREG
  1236  
  1237  	case C_SOREG:
  1238  		return b == C_ZOREG
  1239  	}
  1240  
  1241  	return false
  1242  }
  1243  
  1244  func ocmp(p1, p2 Optab) int {
  1245  	if p1.as != p2.as {
  1246  		return int(p1.as) - int(p2.as)
  1247  	}
  1248  	if p1.from1 != p2.from1 {
  1249  		return int(p1.from1) - int(p2.from1)
  1250  	}
  1251  	if p1.reg != p2.reg {
  1252  		return int(p1.reg) - int(p2.reg)
  1253  	}
  1254  	if p1.to1 != p2.to1 {
  1255  		return int(p1.to1) - int(p2.to1)
  1256  	}
  1257  	return 0
  1258  }
  1259  
  1260  func opset(a, b0 obj.As) {
  1261  	oprange[a&obj.AMask] = oprange[b0]
  1262  }
  1263  
  1264  func buildop(ctxt *obj.Link) {
  1265  	if ctxt.DiagFunc == nil {
  1266  		ctxt.DiagFunc = func(format string, args ...interface{}) {
  1267  			log.Printf(format, args...)
  1268  		}
  1269  	}
  1270  
  1271  	if oprange[AOR&obj.AMask] != nil {
  1272  		// Already initialized; stop now.
  1273  		// This happens in the cmd/asm tests,
  1274  		// each of which re-initializes the arch.
  1275  		return
  1276  	}
  1277  
  1278  	var n int
  1279  
  1280  	for i := 0; i < C_NCLASS; i++ {
  1281  		for n = 0; n < C_NCLASS; n++ {
  1282  			if cmp(n, i) {
  1283  				xcmp[i][n] = true
  1284  			}
  1285  		}
  1286  	}
  1287  	for n = 0; optab[n].as != obj.AXXX; n++ {
  1288  	}
  1289  	slices.SortFunc(optab[:n], ocmp)
  1290  	for i := 0; i < n; i++ {
  1291  		r := optab[i].as
  1292  		r0 := r & obj.AMask
  1293  		start := i
  1294  		for optab[i].as == r {
  1295  			i++
  1296  		}
  1297  		oprange[r0] = optab[start:i]
  1298  		i--
  1299  
  1300  		switch r {
  1301  		default:
  1302  			ctxt.Diag("unknown op in build: %v", r)
  1303  			ctxt.DiagFlush()
  1304  			log.Fatalf("bad code")
  1305  
  1306  		case AABSF:
  1307  			opset(AMOVFD, r0)
  1308  			opset(AMOVDF, r0)
  1309  			opset(AMOVWF, r0)
  1310  			opset(AMOVFW, r0)
  1311  			opset(AMOVWD, r0)
  1312  			opset(AMOVDW, r0)
  1313  			opset(ANEGF, r0)
  1314  			opset(ANEGD, r0)
  1315  			opset(AABSD, r0)
  1316  			opset(ATRUNCDW, r0)
  1317  			opset(ATRUNCFW, r0)
  1318  			opset(ASQRTF, r0)
  1319  			opset(ASQRTD, r0)
  1320  			opset(AFCLASSF, r0)
  1321  			opset(AFCLASSD, r0)
  1322  			opset(AFLOGBF, r0)
  1323  			opset(AFLOGBD, r0)
  1324  
  1325  		case AMOVVF:
  1326  			opset(AMOVVD, r0)
  1327  			opset(AMOVFV, r0)
  1328  			opset(AMOVDV, r0)
  1329  			opset(ATRUNCDV, r0)
  1330  			opset(ATRUNCFV, r0)
  1331  			opset(AFFINTFW, r0)
  1332  			opset(AFFINTFV, r0)
  1333  			opset(AFFINTDW, r0)
  1334  			opset(AFFINTDV, r0)
  1335  			opset(AFTINTWF, r0)
  1336  			opset(AFTINTWD, r0)
  1337  			opset(AFTINTVF, r0)
  1338  			opset(AFTINTVD, r0)
  1339  			opset(AFTINTRPWF, r0)
  1340  			opset(AFTINTRPWD, r0)
  1341  			opset(AFTINTRPVF, r0)
  1342  			opset(AFTINTRPVD, r0)
  1343  			opset(AFTINTRMWF, r0)
  1344  			opset(AFTINTRMWD, r0)
  1345  			opset(AFTINTRMVF, r0)
  1346  			opset(AFTINTRMVD, r0)
  1347  			opset(AFTINTRZWF, r0)
  1348  			opset(AFTINTRZWD, r0)
  1349  			opset(AFTINTRZVF, r0)
  1350  			opset(AFTINTRZVD, r0)
  1351  			opset(AFTINTRNEWF, r0)
  1352  			opset(AFTINTRNEWD, r0)
  1353  			opset(AFTINTRNEVF, r0)
  1354  			opset(AFTINTRNEVD, r0)
  1355  
  1356  		case AADD:
  1357  			opset(ASGT, r0)
  1358  			opset(ASGTU, r0)
  1359  			opset(AADDU, r0)
  1360  
  1361  		case AADDV:
  1362  			opset(AADDVU, r0)
  1363  
  1364  		case AADDF:
  1365  			opset(ADIVF, r0)
  1366  			opset(ADIVD, r0)
  1367  			opset(AMULF, r0)
  1368  			opset(AMULD, r0)
  1369  			opset(ASUBF, r0)
  1370  			opset(ASUBD, r0)
  1371  			opset(AADDD, r0)
  1372  			opset(AFMINF, r0)
  1373  			opset(AFMIND, r0)
  1374  			opset(AFMAXF, r0)
  1375  			opset(AFMAXD, r0)
  1376  			opset(AFCOPYSGF, r0)
  1377  			opset(AFCOPYSGD, r0)
  1378  			opset(AFSCALEBF, r0)
  1379  			opset(AFSCALEBD, r0)
  1380  			opset(AFMAXAF, r0)
  1381  			opset(AFMAXAD, r0)
  1382  			opset(AFMINAF, r0)
  1383  			opset(AFMINAD, r0)
  1384  
  1385  		case AFMADDF:
  1386  			opset(AFMADDD, r0)
  1387  			opset(AFMSUBF, r0)
  1388  			opset(AFMSUBD, r0)
  1389  			opset(AFNMADDF, r0)
  1390  			opset(AFNMADDD, r0)
  1391  			opset(AFNMSUBF, r0)
  1392  			opset(AFNMSUBD, r0)
  1393  
  1394  		case AAND:
  1395  			opset(AOR, r0)
  1396  			opset(AXOR, r0)
  1397  			opset(AORN, r0)
  1398  			opset(AANDN, r0)
  1399  
  1400  		case ABEQ:
  1401  			opset(ABNE, r0)
  1402  			opset(ABLT, r0)
  1403  			opset(ABGE, r0)
  1404  			opset(ABGEU, r0)
  1405  			opset(ABLTU, r0)
  1406  
  1407  		case ABLEZ:
  1408  			opset(ABGEZ, r0)
  1409  			opset(ABLTZ, r0)
  1410  			opset(ABGTZ, r0)
  1411  
  1412  		case AMOVB:
  1413  			opset(AMOVH, r0)
  1414  
  1415  		case AMOVBU:
  1416  			opset(AMOVHU, r0)
  1417  
  1418  		case AMUL:
  1419  			opset(AMULU, r0)
  1420  			opset(AMULH, r0)
  1421  			opset(AMULHU, r0)
  1422  			opset(AREM, r0)
  1423  			opset(AREMU, r0)
  1424  			opset(ADIV, r0)
  1425  			opset(ADIVU, r0)
  1426  
  1427  		case AMULV:
  1428  			opset(AMULVU, r0)
  1429  			opset(AMULHV, r0)
  1430  			opset(AMULHVU, r0)
  1431  			opset(AREMV, r0)
  1432  			opset(AREMVU, r0)
  1433  			opset(ADIVV, r0)
  1434  			opset(ADIVVU, r0)
  1435  
  1436  		case ASLL:
  1437  			opset(ASRL, r0)
  1438  			opset(ASRA, r0)
  1439  			opset(AROTR, r0)
  1440  
  1441  		case ASLLV:
  1442  			opset(ASRAV, r0)
  1443  			opset(ASRLV, r0)
  1444  			opset(AROTRV, r0)
  1445  
  1446  		case ABSTRPICKW:
  1447  			opset(ABSTRPICKV, r0)
  1448  			opset(ABSTRINSW, r0)
  1449  			opset(ABSTRINSV, r0)
  1450  
  1451  		case ASUB:
  1452  			opset(ASUBU, r0)
  1453  			opset(ANOR, r0)
  1454  
  1455  		case ASUBV:
  1456  			opset(ASUBVU, r0)
  1457  
  1458  		case ASYSCALL:
  1459  			opset(ADBAR, r0)
  1460  			opset(ABREAK, r0)
  1461  
  1462  		case ACMPEQF:
  1463  			opset(ACMPGTF, r0)
  1464  			opset(ACMPGTD, r0)
  1465  			opset(ACMPGEF, r0)
  1466  			opset(ACMPGED, r0)
  1467  			opset(ACMPEQD, r0)
  1468  
  1469  		case ABFPT:
  1470  			opset(ABFPF, r0)
  1471  
  1472  		case AMOVW,
  1473  			AMOVD,
  1474  			AMOVF,
  1475  			AMOVV,
  1476  			ARFE,
  1477  			AJAL,
  1478  			AJMP,
  1479  			AMOVWU,
  1480  			AVMOVQ,
  1481  			AXVMOVQ,
  1482  			ALL,
  1483  			ALLV,
  1484  			ASC,
  1485  			ASCV,
  1486  			ANEGW,
  1487  			ANEGV,
  1488  			AWORD,
  1489  			obj.ANOP,
  1490  			obj.ATEXT,
  1491  			obj.AFUNCDATA,
  1492  			obj.APCALIGN,
  1493  			obj.APCDATA,
  1494  			obj.ADUFFZERO,
  1495  			obj.ADUFFCOPY:
  1496  			break
  1497  
  1498  		case ARDTIMELW:
  1499  			opset(ARDTIMEHW, r0)
  1500  			opset(ARDTIMED, r0)
  1501  
  1502  		case ACLOW:
  1503  			opset(ACLZW, r0)
  1504  			opset(ACTOW, r0)
  1505  			opset(ACTZW, r0)
  1506  			opset(ACLOV, r0)
  1507  			opset(ACLZV, r0)
  1508  			opset(ACTOV, r0)
  1509  			opset(ACTZV, r0)
  1510  			opset(AREVB2H, r0)
  1511  			opset(AREVB4H, r0)
  1512  			opset(AREVB2W, r0)
  1513  			opset(AREVBV, r0)
  1514  			opset(AREVH2W, r0)
  1515  			opset(AREVHV, r0)
  1516  			opset(ABITREV4B, r0)
  1517  			opset(ABITREV8B, r0)
  1518  			opset(ABITREVW, r0)
  1519  			opset(ABITREVV, r0)
  1520  			opset(AEXTWB, r0)
  1521  			opset(AEXTWH, r0)
  1522  			opset(ACPUCFG, r0)
  1523  
  1524  		case ATEQ:
  1525  			opset(ATNE, r0)
  1526  
  1527  		case AMASKEQZ:
  1528  			opset(AMASKNEZ, r0)
  1529  			opset(ACRCWBW, r0)
  1530  			opset(ACRCWHW, r0)
  1531  			opset(ACRCWWW, r0)
  1532  			opset(ACRCWVW, r0)
  1533  			opset(ACRCCWBW, r0)
  1534  			opset(ACRCCWHW, r0)
  1535  			opset(ACRCCWWW, r0)
  1536  			opset(ACRCCWVW, r0)
  1537  
  1538  		case ANOOP:
  1539  			opset(obj.AUNDEF, r0)
  1540  
  1541  		case AAMSWAPW:
  1542  			for i := range atomicInst {
  1543  				if i == AAMSWAPW {
  1544  					continue
  1545  				}
  1546  				opset(i, r0)
  1547  			}
  1548  
  1549  		case AVSEQB:
  1550  			opset(AVSEQH, r0)
  1551  			opset(AVSEQW, r0)
  1552  			opset(AVSEQV, r0)
  1553  			opset(AVILVLB, r0)
  1554  			opset(AVILVLH, r0)
  1555  			opset(AVILVLW, r0)
  1556  			opset(AVILVLV, r0)
  1557  			opset(AVILVHB, r0)
  1558  			opset(AVILVHH, r0)
  1559  			opset(AVILVHW, r0)
  1560  			opset(AVILVHV, r0)
  1561  			opset(AVMULB, r0)
  1562  			opset(AVMULH, r0)
  1563  			opset(AVMULW, r0)
  1564  			opset(AVMULV, r0)
  1565  			opset(AVMUHB, r0)
  1566  			opset(AVMUHH, r0)
  1567  			opset(AVMUHW, r0)
  1568  			opset(AVMUHV, r0)
  1569  			opset(AVMUHBU, r0)
  1570  			opset(AVMUHHU, r0)
  1571  			opset(AVMUHWU, r0)
  1572  			opset(AVMUHVU, r0)
  1573  			opset(AVDIVB, r0)
  1574  			opset(AVDIVH, r0)
  1575  			opset(AVDIVW, r0)
  1576  			opset(AVDIVV, r0)
  1577  			opset(AVMODB, r0)
  1578  			opset(AVMODH, r0)
  1579  			opset(AVMODW, r0)
  1580  			opset(AVMODV, r0)
  1581  			opset(AVDIVBU, r0)
  1582  			opset(AVDIVHU, r0)
  1583  			opset(AVDIVWU, r0)
  1584  			opset(AVDIVVU, r0)
  1585  			opset(AVMODBU, r0)
  1586  			opset(AVMODHU, r0)
  1587  			opset(AVMODWU, r0)
  1588  			opset(AVMODVU, r0)
  1589  			opset(AVMULWEVHB, r0)
  1590  			opset(AVMULWEVWH, r0)
  1591  			opset(AVMULWEVVW, r0)
  1592  			opset(AVMULWEVQV, r0)
  1593  			opset(AVMULWODHB, r0)
  1594  			opset(AVMULWODWH, r0)
  1595  			opset(AVMULWODVW, r0)
  1596  			opset(AVMULWODQV, r0)
  1597  			opset(AVMULWEVHBU, r0)
  1598  			opset(AVMULWEVWHU, r0)
  1599  			opset(AVMULWEVVWU, r0)
  1600  			opset(AVMULWEVQVU, r0)
  1601  			opset(AVMULWODHBU, r0)
  1602  			opset(AVMULWODWHU, r0)
  1603  			opset(AVMULWODVWU, r0)
  1604  			opset(AVMULWODQVU, r0)
  1605  			opset(AVMULWEVHBUB, r0)
  1606  			opset(AVMULWEVWHUH, r0)
  1607  			opset(AVMULWEVVWUW, r0)
  1608  			opset(AVMULWEVQVUV, r0)
  1609  			opset(AVMULWODHBUB, r0)
  1610  			opset(AVMULWODWHUH, r0)
  1611  			opset(AVMULWODVWUW, r0)
  1612  			opset(AVMULWODQVUV, r0)
  1613  			opset(AVADDF, r0)
  1614  			opset(AVADDD, r0)
  1615  			opset(AVSUBF, r0)
  1616  			opset(AVSUBD, r0)
  1617  			opset(AVMULF, r0)
  1618  			opset(AVMULD, r0)
  1619  			opset(AVDIVF, r0)
  1620  			opset(AVDIVD, r0)
  1621  
  1622  		case AXVSEQB:
  1623  			opset(AXVSEQH, r0)
  1624  			opset(AXVSEQW, r0)
  1625  			opset(AXVSEQV, r0)
  1626  			opset(AXVILVLB, r0)
  1627  			opset(AXVILVLH, r0)
  1628  			opset(AXVILVLW, r0)
  1629  			opset(AXVILVLV, r0)
  1630  			opset(AXVILVHB, r0)
  1631  			opset(AXVILVHH, r0)
  1632  			opset(AXVILVHW, r0)
  1633  			opset(AXVILVHV, r0)
  1634  			opset(AXVMULB, r0)
  1635  			opset(AXVMULH, r0)
  1636  			opset(AXVMULW, r0)
  1637  			opset(AXVMULV, r0)
  1638  			opset(AXVMUHB, r0)
  1639  			opset(AXVMUHH, r0)
  1640  			opset(AXVMUHW, r0)
  1641  			opset(AXVMUHV, r0)
  1642  			opset(AXVMUHBU, r0)
  1643  			opset(AXVMUHHU, r0)
  1644  			opset(AXVMUHWU, r0)
  1645  			opset(AXVMUHVU, r0)
  1646  			opset(AXVDIVB, r0)
  1647  			opset(AXVDIVH, r0)
  1648  			opset(AXVDIVW, r0)
  1649  			opset(AXVDIVV, r0)
  1650  			opset(AXVMODB, r0)
  1651  			opset(AXVMODH, r0)
  1652  			opset(AXVMODW, r0)
  1653  			opset(AXVMODV, r0)
  1654  			opset(AXVDIVBU, r0)
  1655  			opset(AXVDIVHU, r0)
  1656  			opset(AXVDIVWU, r0)
  1657  			opset(AXVDIVVU, r0)
  1658  			opset(AXVMODBU, r0)
  1659  			opset(AXVMODHU, r0)
  1660  			opset(AXVMODWU, r0)
  1661  			opset(AXVMODVU, r0)
  1662  			opset(AXVMULWEVHB, r0)
  1663  			opset(AXVMULWEVWH, r0)
  1664  			opset(AXVMULWEVVW, r0)
  1665  			opset(AXVMULWEVQV, r0)
  1666  			opset(AXVMULWODHB, r0)
  1667  			opset(AXVMULWODWH, r0)
  1668  			opset(AXVMULWODVW, r0)
  1669  			opset(AXVMULWODQV, r0)
  1670  			opset(AXVMULWEVHBU, r0)
  1671  			opset(AXVMULWEVWHU, r0)
  1672  			opset(AXVMULWEVVWU, r0)
  1673  			opset(AXVMULWEVQVU, r0)
  1674  			opset(AXVMULWODHBU, r0)
  1675  			opset(AXVMULWODWHU, r0)
  1676  			opset(AXVMULWODVWU, r0)
  1677  			opset(AXVMULWODQVU, r0)
  1678  			opset(AXVMULWEVHBUB, r0)
  1679  			opset(AXVMULWEVWHUH, r0)
  1680  			opset(AXVMULWEVVWUW, r0)
  1681  			opset(AXVMULWEVQVUV, r0)
  1682  			opset(AXVMULWODHBUB, r0)
  1683  			opset(AXVMULWODWHUH, r0)
  1684  			opset(AXVMULWODVWUW, r0)
  1685  			opset(AXVMULWODQVUV, r0)
  1686  			opset(AXVADDF, r0)
  1687  			opset(AXVADDD, r0)
  1688  			opset(AXVSUBF, r0)
  1689  			opset(AXVSUBD, r0)
  1690  			opset(AXVMULF, r0)
  1691  			opset(AXVMULD, r0)
  1692  			opset(AXVDIVF, r0)
  1693  			opset(AXVDIVD, r0)
  1694  
  1695  		case AVANDB:
  1696  			opset(AVORB, r0)
  1697  			opset(AVXORB, r0)
  1698  			opset(AVNORB, r0)
  1699  			opset(AVSHUF4IB, r0)
  1700  			opset(AVSHUF4IH, r0)
  1701  			opset(AVSHUF4IW, r0)
  1702  			opset(AVSHUF4IV, r0)
  1703  
  1704  		case AXVANDB:
  1705  			opset(AXVORB, r0)
  1706  			opset(AXVXORB, r0)
  1707  			opset(AXVNORB, r0)
  1708  			opset(AXVSHUF4IB, r0)
  1709  			opset(AXVSHUF4IH, r0)
  1710  			opset(AXVSHUF4IW, r0)
  1711  			opset(AXVSHUF4IV, r0)
  1712  
  1713  		case AVANDV:
  1714  			opset(AVORV, r0)
  1715  			opset(AVXORV, r0)
  1716  			opset(AVNORV, r0)
  1717  			opset(AVANDNV, r0)
  1718  			opset(AVORNV, r0)
  1719  
  1720  		case AXVANDV:
  1721  			opset(AXVORV, r0)
  1722  			opset(AXVXORV, r0)
  1723  			opset(AXVNORV, r0)
  1724  			opset(AXVANDNV, r0)
  1725  			opset(AXVORNV, r0)
  1726  
  1727  		case AVPCNTB:
  1728  			opset(AVPCNTH, r0)
  1729  			opset(AVPCNTW, r0)
  1730  			opset(AVPCNTV, r0)
  1731  			opset(AVFSQRTF, r0)
  1732  			opset(AVFSQRTD, r0)
  1733  			opset(AVFRECIPF, r0)
  1734  			opset(AVFRECIPD, r0)
  1735  			opset(AVFRSQRTF, r0)
  1736  			opset(AVFRSQRTD, r0)
  1737  			opset(AVNEGB, r0)
  1738  			opset(AVNEGH, r0)
  1739  			opset(AVNEGW, r0)
  1740  			opset(AVNEGV, r0)
  1741  			opset(AVFRINTRNEF, r0)
  1742  			opset(AVFRINTRNED, r0)
  1743  			opset(AVFRINTRZF, r0)
  1744  			opset(AVFRINTRZD, r0)
  1745  			opset(AVFRINTRPF, r0)
  1746  			opset(AVFRINTRPD, r0)
  1747  			opset(AVFRINTRMF, r0)
  1748  			opset(AVFRINTRMD, r0)
  1749  			opset(AVFRINTF, r0)
  1750  			opset(AVFRINTD, r0)
  1751  			opset(AVFCLASSF, r0)
  1752  			opset(AVFCLASSD, r0)
  1753  
  1754  		case AXVPCNTB:
  1755  			opset(AXVPCNTH, r0)
  1756  			opset(AXVPCNTW, r0)
  1757  			opset(AXVPCNTV, r0)
  1758  			opset(AXVFSQRTF, r0)
  1759  			opset(AXVFSQRTD, r0)
  1760  			opset(AXVFRECIPF, r0)
  1761  			opset(AXVFRECIPD, r0)
  1762  			opset(AXVFRSQRTF, r0)
  1763  			opset(AXVFRSQRTD, r0)
  1764  			opset(AXVNEGB, r0)
  1765  			opset(AXVNEGH, r0)
  1766  			opset(AXVNEGW, r0)
  1767  			opset(AXVNEGV, r0)
  1768  			opset(AXVFRINTRNEF, r0)
  1769  			opset(AXVFRINTRNED, r0)
  1770  			opset(AXVFRINTRZF, r0)
  1771  			opset(AXVFRINTRZD, r0)
  1772  			opset(AXVFRINTRPF, r0)
  1773  			opset(AXVFRINTRPD, r0)
  1774  			opset(AXVFRINTRMF, r0)
  1775  			opset(AXVFRINTRMD, r0)
  1776  			opset(AXVFRINTF, r0)
  1777  			opset(AXVFRINTD, r0)
  1778  			opset(AXVFCLASSF, r0)
  1779  			opset(AXVFCLASSD, r0)
  1780  
  1781  		case AVADDB:
  1782  			opset(AVADDH, r0)
  1783  			opset(AVADDW, r0)
  1784  			opset(AVADDV, r0)
  1785  			opset(AVADDQ, r0)
  1786  			opset(AVSUBB, r0)
  1787  			opset(AVSUBH, r0)
  1788  			opset(AVSUBW, r0)
  1789  			opset(AVSUBV, r0)
  1790  			opset(AVSUBQ, r0)
  1791  
  1792  		case AXVADDB:
  1793  			opset(AXVADDH, r0)
  1794  			opset(AXVADDW, r0)
  1795  			opset(AXVADDV, r0)
  1796  			opset(AXVADDQ, r0)
  1797  			opset(AXVSUBB, r0)
  1798  			opset(AXVSUBH, r0)
  1799  			opset(AXVSUBW, r0)
  1800  			opset(AXVSUBV, r0)
  1801  			opset(AXVSUBQ, r0)
  1802  
  1803  		case AVSLLB:
  1804  			opset(AVSRLB, r0)
  1805  			opset(AVSRAB, r0)
  1806  			opset(AVROTRB, r0)
  1807  
  1808  		case AXVSLLB:
  1809  			opset(AXVSRLB, r0)
  1810  			opset(AXVSRAB, r0)
  1811  			opset(AXVROTRB, r0)
  1812  
  1813  		case AVSLLH:
  1814  			opset(AVSRLH, r0)
  1815  			opset(AVSRAH, r0)
  1816  			opset(AVROTRH, r0)
  1817  
  1818  		case AXVSLLH:
  1819  			opset(AXVSRLH, r0)
  1820  			opset(AXVSRAH, r0)
  1821  			opset(AXVROTRH, r0)
  1822  
  1823  		case AVSLLW:
  1824  			opset(AVSRLW, r0)
  1825  			opset(AVSRAW, r0)
  1826  			opset(AVROTRW, r0)
  1827  			opset(AVADDBU, r0)
  1828  			opset(AVADDHU, r0)
  1829  			opset(AVADDWU, r0)
  1830  			opset(AVADDVU, r0)
  1831  			opset(AVSUBBU, r0)
  1832  			opset(AVSUBHU, r0)
  1833  			opset(AVSUBWU, r0)
  1834  			opset(AVSUBVU, r0)
  1835  
  1836  		case AXVSLLW:
  1837  			opset(AXVSRLW, r0)
  1838  			opset(AXVSRAW, r0)
  1839  			opset(AXVROTRW, r0)
  1840  			opset(AXVADDBU, r0)
  1841  			opset(AXVADDHU, r0)
  1842  			opset(AXVADDWU, r0)
  1843  			opset(AXVADDVU, r0)
  1844  			opset(AXVSUBBU, r0)
  1845  			opset(AXVSUBHU, r0)
  1846  			opset(AXVSUBWU, r0)
  1847  			opset(AXVSUBVU, r0)
  1848  
  1849  		case AVSLLV:
  1850  			opset(AVSRLV, r0)
  1851  			opset(AVSRAV, r0)
  1852  			opset(AVROTRV, r0)
  1853  
  1854  		case AXVSLLV:
  1855  			opset(AXVSRLV, r0)
  1856  			opset(AXVSRAV, r0)
  1857  			opset(AXVROTRV, r0)
  1858  
  1859  		case AVSETEQV:
  1860  			opset(AVSETNEV, r0)
  1861  			opset(AVSETANYEQB, r0)
  1862  			opset(AVSETANYEQH, r0)
  1863  			opset(AVSETANYEQW, r0)
  1864  			opset(AVSETANYEQV, r0)
  1865  			opset(AVSETALLNEB, r0)
  1866  			opset(AVSETALLNEH, r0)
  1867  			opset(AVSETALLNEW, r0)
  1868  			opset(AVSETALLNEV, r0)
  1869  
  1870  		case AXVSETEQV:
  1871  			opset(AXVSETNEV, r0)
  1872  			opset(AXVSETANYEQB, r0)
  1873  			opset(AXVSETANYEQH, r0)
  1874  			opset(AXVSETANYEQW, r0)
  1875  			opset(AXVSETANYEQV, r0)
  1876  			opset(AXVSETALLNEB, r0)
  1877  			opset(AXVSETALLNEH, r0)
  1878  			opset(AXVSETALLNEW, r0)
  1879  			opset(AXVSETALLNEV, r0)
  1880  
  1881  		}
  1882  	}
  1883  }
  1884  
  1885  func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
  1886  	return op | (r1&0x1F)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4 & 0x1F)
  1887  }
  1888  
  1889  // r1 -> rk
  1890  // r2 -> rj
  1891  // r3 -> rd
  1892  func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32 {
  1893  	return op | (r1&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1894  }
  1895  
  1896  // r2 -> rj
  1897  // r3 -> rd
  1898  func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
  1899  	return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1900  }
  1901  
  1902  func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
  1903  	return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
  1904  }
  1905  
  1906  func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1907  	return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1908  }
  1909  
  1910  func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1911  	return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1912  }
  1913  
  1914  func OP_8IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1915  	return op | (i&0xFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1916  }
  1917  
  1918  func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1919  	return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1920  }
  1921  
  1922  func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1923  	return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1924  }
  1925  
  1926  func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1927  	return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1928  }
  1929  
  1930  func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1931  	return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1932  }
  1933  
  1934  func OP_IR(op uint32, i uint32, r2 uint32) uint32 {
  1935  	return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0 // ui20, rd5
  1936  }
  1937  
  1938  func OP_15I(op uint32, i uint32) uint32 {
  1939  	return op | (i&0x7FFF)<<0
  1940  }
  1941  
  1942  // i1 -> msb
  1943  // r2 -> rj
  1944  // i3 -> lsb
  1945  // r4 -> rd
  1946  func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32 {
  1947  	return op | (i1 << 16) | (r2&0x1F)<<5 | (i3 << 10) | (r4&0x1F)<<0
  1948  }
  1949  
  1950  // Encoding for the 'b' or 'bl' instruction.
  1951  func OP_B_BL(op uint32, i uint32) uint32 {
  1952  	return op | ((i & 0xFFFF) << 10) | ((i >> 16) & 0x3FF)
  1953  }
  1954  
  1955  func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
  1956  	o1 := uint32(0)
  1957  	o2 := uint32(0)
  1958  	o3 := uint32(0)
  1959  	o4 := uint32(0)
  1960  	o5 := uint32(0)
  1961  
  1962  	add := AADDU
  1963  	add = AADDVU
  1964  
  1965  	switch o.type_ {
  1966  	default:
  1967  		c.ctxt.Diag("unknown type %d %v", o.type_)
  1968  		prasm(p)
  1969  
  1970  	case 0: // pseudo ops
  1971  		break
  1972  
  1973  	case 1: // mov r1,r2 ==> OR r1,r0,r2
  1974  		a := AOR
  1975  		if p.As == AMOVW {
  1976  			a = ASLL
  1977  		}
  1978  		o1 = OP_RRR(c.oprrr(a), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
  1979  
  1980  	case 2: // add/sub r1,[r2],r3
  1981  		r := int(p.Reg)
  1982  		if p.As == ANEGW || p.As == ANEGV {
  1983  			r = REGZERO
  1984  		}
  1985  		if r == 0 {
  1986  			r = int(p.To.Reg)
  1987  		}
  1988  		o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
  1989  
  1990  	case 3: // mov $soreg, r ==> or/add $i,o,r
  1991  		v := c.regoff(&p.From)
  1992  
  1993  		r := int(p.From.Reg)
  1994  		if r == 0 {
  1995  			r = int(o.param)
  1996  		}
  1997  		a := add
  1998  		if o.from1 == C_12CON && v > 0 {
  1999  			a = AOR
  2000  		}
  2001  
  2002  		o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg))
  2003  
  2004  	case 4: // add $scon,[r1],r2
  2005  		v := c.regoff(&p.From)
  2006  		r := int(p.Reg)
  2007  		if r == 0 {
  2008  			r = int(p.To.Reg)
  2009  		}
  2010  		o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2011  
  2012  	case 5: // syscall
  2013  		v := c.regoff(&p.From)
  2014  		o1 = OP_15I(c.opi(p.As), uint32(v))
  2015  
  2016  	case 6: // beq r1,[r2],sbra
  2017  		v := int32(0)
  2018  		if p.To.Target() != nil {
  2019  			v = int32(p.To.Target().Pc-p.Pc) >> 2
  2020  		}
  2021  		as, rd, rj, width := p.As, p.Reg, p.From.Reg, 16
  2022  		switch as {
  2023  		case ABGTZ, ABLEZ:
  2024  			rd, rj = rj, rd
  2025  		case ABFPT, ABFPF:
  2026  			width = 21
  2027  			// FCC0 is the implicit source operand, now that we
  2028  			// don't register-allocate from the FCC bank.
  2029  			if rj == 0 {
  2030  				rj = REG_FCC0
  2031  			}
  2032  		case ABEQ, ABNE:
  2033  			if rd == 0 || rd == REGZERO || rj == REGZERO {
  2034  				// BEQZ/BNEZ can be encoded with 21-bit offsets.
  2035  				width = 21
  2036  				as = -as
  2037  				if rj == 0 || rj == REGZERO {
  2038  					rj = rd
  2039  				}
  2040  			}
  2041  		}
  2042  		switch width {
  2043  		case 21:
  2044  			if (v<<11)>>11 != v {
  2045  				c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
  2046  			}
  2047  			o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
  2048  		case 16:
  2049  			if (v<<16)>>16 != v {
  2050  				c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
  2051  			}
  2052  			o1 = OP_16IRR(c.opirr(as), uint32(v), uint32(rj), uint32(rd))
  2053  		default:
  2054  			c.ctxt.Diag("unexpected branch encoding\n%v", p)
  2055  		}
  2056  
  2057  	case 7: // mov r, soreg
  2058  		r := int(p.To.Reg)
  2059  		if r == 0 {
  2060  			r = int(o.param)
  2061  		}
  2062  		v := c.regoff(&p.To)
  2063  		o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
  2064  
  2065  	case 8: // mov soreg, r
  2066  		r := int(p.From.Reg)
  2067  		if r == 0 {
  2068  			r = int(o.param)
  2069  		}
  2070  		v := c.regoff(&p.From)
  2071  		o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2072  
  2073  	case 9: // sll r1,[r2],r3
  2074  		o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
  2075  
  2076  	case 10: // add $con,[r1],r2 ==> mov $con, t; add t,[r1],r2
  2077  		v := c.regoff(&p.From)
  2078  		a := AOR
  2079  		if v < 0 {
  2080  			a = AADDU
  2081  		}
  2082  		o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
  2083  		r := int(p.Reg)
  2084  		if r == 0 {
  2085  			r = int(p.To.Reg)
  2086  		}
  2087  		o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2088  
  2089  	case 11: // jmp lbra
  2090  		v := int32(0)
  2091  		if p.To.Target() != nil {
  2092  			v = int32(p.To.Target().Pc-p.Pc) >> 2
  2093  		}
  2094  		o1 = OP_B_BL(c.opirr(p.As), uint32(v))
  2095  		if p.To.Sym != nil {
  2096  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  2097  				Type: objabi.R_CALLLOONG64,
  2098  				Off:  int32(c.pc),
  2099  				Siz:  4,
  2100  				Sym:  p.To.Sym,
  2101  				Add:  p.To.Offset,
  2102  			})
  2103  		}
  2104  
  2105  	case 12: // movbs r,r
  2106  		switch p.As {
  2107  		case AMOVB:
  2108  			o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
  2109  		case AMOVH:
  2110  			o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
  2111  		case AMOVBU:
  2112  			o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
  2113  		case AMOVHU:
  2114  			o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
  2115  		case AMOVWU:
  2116  			o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
  2117  		default:
  2118  			c.ctxt.Diag("unexpected encoding\n%v", p)
  2119  		}
  2120  
  2121  	case 13: // vsll $ui3, [vr1], vr2
  2122  		v := c.regoff(&p.From)
  2123  		r := int(p.Reg)
  2124  		if r == 0 {
  2125  			r = int(p.To.Reg)
  2126  		}
  2127  		o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2128  
  2129  	case 14: // vsll $ui4, [vr1], vr2
  2130  		v := c.regoff(&p.From)
  2131  		r := int(p.Reg)
  2132  		if r == 0 {
  2133  			r = int(p.To.Reg)
  2134  		}
  2135  		o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2136  
  2137  	case 15: // teq $c r,r
  2138  		v := c.regoff(&p.From)
  2139  		r := int(p.Reg)
  2140  		if r == 0 {
  2141  			r = REGZERO
  2142  		}
  2143  		/*
  2144  			teq c, r1, r2
  2145  			fallthrough
  2146  			==>
  2147  			bne r1, r2, 2
  2148  			break c
  2149  			fallthrough
  2150  		*/
  2151  		if p.As == ATEQ {
  2152  			o1 = OP_16IRR(c.opirr(ABNE), uint32(2), uint32(r), uint32(p.To.Reg))
  2153  		} else { // ATNE
  2154  			o1 = OP_16IRR(c.opirr(ABEQ), uint32(2), uint32(r), uint32(p.To.Reg))
  2155  		}
  2156  		o2 = OP_15I(c.opi(ABREAK), uint32(v))
  2157  
  2158  	case 16: // sll $c,[r1],r2
  2159  		v := c.regoff(&p.From)
  2160  		r := int(p.Reg)
  2161  		if r == 0 {
  2162  			r = int(p.To.Reg)
  2163  		}
  2164  
  2165  		// instruction ending with V:6-digit immediate, others:5-digit immediate
  2166  		if v >= 32 && vshift(p.As) {
  2167  			o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x3f, uint32(r), uint32(p.To.Reg))
  2168  		} else {
  2169  			o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x1f, uint32(r), uint32(p.To.Reg))
  2170  		}
  2171  
  2172  	case 17: // bstrpickw $msbw, r1, $lsbw, r2
  2173  		rd, rj := p.To.Reg, p.Reg
  2174  		if rj == obj.REG_NONE {
  2175  			rj = rd
  2176  		}
  2177  		msb, lsb := p.From.Offset, p.GetFrom3().Offset
  2178  
  2179  		// check the range of msb and lsb
  2180  		var b uint32
  2181  		if p.As == ABSTRPICKW || p.As == ABSTRINSW {
  2182  			b = 32
  2183  		} else {
  2184  			b = 64
  2185  		}
  2186  		if lsb < 0 || uint32(lsb) >= b || msb < 0 || uint32(msb) >= b || uint32(lsb) > uint32(msb) {
  2187  			c.ctxt.Diag("illegal bit number\n%v", p)
  2188  		}
  2189  
  2190  		o1 = OP_IRIR(c.opirir(p.As), uint32(msb), uint32(rj), uint32(lsb), uint32(rd))
  2191  
  2192  	case 18: // jmp [r1],0(r2)
  2193  		r := int(p.Reg)
  2194  		if r == 0 {
  2195  			r = int(o.param)
  2196  		}
  2197  		o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.To.Reg), uint32(r))
  2198  		if p.As == obj.ACALL {
  2199  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  2200  				Type: objabi.R_CALLIND,
  2201  				Off:  int32(c.pc),
  2202  			})
  2203  		}
  2204  
  2205  	case 19: // mov $lcon,r
  2206  		// NOTE: this case does not use REGTMP. If it ever does,
  2207  		// remove the NOTUSETMP flag in optab.
  2208  		v := c.regoff(&p.From)
  2209  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2210  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2211  
  2212  	case 20: // mov Rsrc, (Rbase)(Roff)
  2213  		o1 = OP_RRR(c.oprrr(p.As), uint32(p.To.Index), uint32(p.To.Reg), uint32(p.From.Reg))
  2214  
  2215  	case 21: // mov (Rbase)(Roff), Rdst
  2216  		o1 = OP_RRR(c.oprrr(-p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(p.To.Reg))
  2217  
  2218  	case 22: // add $si5,[r1],r2
  2219  		v := c.regoff(&p.From)
  2220  		r := int(p.Reg)
  2221  		if r == 0 {
  2222  			r = int(p.To.Reg)
  2223  		}
  2224  
  2225  		o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2226  
  2227  	case 23: // add $ui8,[r1],r2
  2228  		v := c.regoff(&p.From)
  2229  		r := int(p.Reg)
  2230  		if r == 0 {
  2231  			r = int(p.To.Reg)
  2232  		}
  2233  
  2234  		// the operand range available for instructions VSHUF4IV and XVSHUF4IV is [0, 15]
  2235  		if p.As == AVSHUF4IV || p.As == AXVSHUF4IV {
  2236  			operand := uint32(v)
  2237  			c.checkoperand(p, operand, 15)
  2238  		}
  2239  
  2240  		o1 = OP_8IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2241  
  2242  	case 24: // add $lcon,r1,r2
  2243  		v := c.regoff(&p.From)
  2244  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2245  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2246  		r := int(p.Reg)
  2247  		if r == 0 {
  2248  			r = int(p.To.Reg)
  2249  		}
  2250  		o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2251  
  2252  	case 25: // mov $ucon,r
  2253  		v := c.regoff(&p.From)
  2254  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2255  
  2256  	case 26: // add/and $ucon,[r1],r2
  2257  		v := c.regoff(&p.From)
  2258  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2259  		r := int(p.Reg)
  2260  		if r == 0 {
  2261  			r = int(p.To.Reg)
  2262  		}
  2263  		o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2264  
  2265  	case 27: // mov $lsext/auto/oreg,r
  2266  		v := c.regoff(&p.From)
  2267  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2268  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2269  		r := int(p.From.Reg)
  2270  		if r == 0 {
  2271  			r = int(o.param)
  2272  		}
  2273  		o3 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2274  
  2275  	case 28: // mov [sl]ext/auto/oreg,fr
  2276  		v := c.regoff(&p.From)
  2277  		r := int(p.From.Reg)
  2278  		if r == 0 {
  2279  			r = int(o.param)
  2280  		}
  2281  		switch o.size {
  2282  		case 12:
  2283  			o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2284  			o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2285  			o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
  2286  
  2287  		case 4:
  2288  			o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2289  		}
  2290  
  2291  	case 29: // mov fr,[sl]ext/auto/oreg
  2292  		v := c.regoff(&p.To)
  2293  		r := int(p.To.Reg)
  2294  		if r == 0 {
  2295  			r = int(o.param)
  2296  		}
  2297  		switch o.size {
  2298  		case 12:
  2299  			o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2300  			o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2301  			o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
  2302  
  2303  		case 4:
  2304  			o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
  2305  		}
  2306  
  2307  	case 30: // mov gr/fr/fcc/fcsr, fr/fcc/fcsr/gr
  2308  		a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To))
  2309  		o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
  2310  
  2311  	case 31: // vsll $ui5, [vr1], vr2
  2312  		v := c.regoff(&p.From)
  2313  		r := int(p.Reg)
  2314  		if r == 0 {
  2315  			r = int(p.To.Reg)
  2316  		}
  2317  		o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2318  
  2319  	case 32: // vsll $ui6, [vr1], vr2
  2320  		v := c.regoff(&p.From)
  2321  		r := int(p.Reg)
  2322  		if r == 0 {
  2323  			r = int(p.To.Reg)
  2324  		}
  2325  		o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2326  
  2327  	case 34: // mov $con,fr
  2328  		v := c.regoff(&p.From)
  2329  		a := AADDU
  2330  		if v > 0 {
  2331  			a = AOR
  2332  		}
  2333  		a2 := c.specialFpMovInst(p.As, C_REG, oclass(&p.To))
  2334  		o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
  2335  		o2 = OP_RR(a2, uint32(REGTMP), uint32(p.To.Reg))
  2336  
  2337  	case 35: // mov r,lext/auto/oreg
  2338  		v := c.regoff(&p.To)
  2339  		r := int(p.To.Reg)
  2340  		if r == 0 {
  2341  			r = int(o.param)
  2342  		}
  2343  		o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2344  		o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2345  		o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
  2346  
  2347  	case 36: // mov lext/auto/oreg,r
  2348  		v := c.regoff(&p.From)
  2349  		r := int(p.From.Reg)
  2350  		if r == 0 {
  2351  			r = int(o.param)
  2352  		}
  2353  		o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2354  		o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2355  		o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
  2356  
  2357  	case 37: // fmadd r1, r2, [r3], r4
  2358  		r := int(p.To.Reg)
  2359  		if len(p.RestArgs) > 0 {
  2360  			r = int(p.GetFrom3().Reg)
  2361  		}
  2362  		o1 = OP_RRRR(c.oprrrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(r), uint32(p.To.Reg))
  2363  
  2364  	case 38: // word
  2365  		o1 = uint32(c.regoff(&p.From))
  2366  
  2367  	case 39: // vmov Rn, Vd.<T>[index]
  2368  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
  2369  		if v == 0 {
  2370  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2371  		}
  2372  
  2373  		Rj := uint32(p.From.Reg & EXT_REG_MASK)
  2374  		Vd := uint32(p.To.Reg & EXT_REG_MASK)
  2375  		index := uint32(p.To.Index)
  2376  		c.checkindex(p, index, m)
  2377  		o1 = v | (index << 10) | (Rj << 5) | Vd
  2378  
  2379  	case 40: // vmov Vd.<T>[index], Rn
  2380  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
  2381  		if v == 0 {
  2382  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2383  		}
  2384  
  2385  		Vj := uint32(p.From.Reg & EXT_REG_MASK)
  2386  		Rd := uint32(p.To.Reg & EXT_REG_MASK)
  2387  		index := uint32(p.From.Index)
  2388  		c.checkindex(p, index, m)
  2389  		o1 = v | (index << 10) | (Vj << 5) | Rd
  2390  
  2391  	case 41: // vmov Rn, Vd.<T>
  2392  		v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
  2393  		if v == 0 {
  2394  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2395  		}
  2396  
  2397  		Rj := uint32(p.From.Reg & EXT_REG_MASK)
  2398  		Vd := uint32(p.To.Reg & EXT_REG_MASK)
  2399  		o1 = v | (Rj << 5) | Vd
  2400  
  2401  	case 42: // vmov  xj, xd.<T>
  2402  		v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
  2403  		if v == 0 {
  2404  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2405  		}
  2406  
  2407  		Xj := uint32(p.From.Reg & EXT_REG_MASK)
  2408  		Xd := uint32(p.To.Reg & EXT_REG_MASK)
  2409  		o1 = v | (Xj << 5) | Xd
  2410  
  2411  	case 43: // vmov  xj, xd.<T>[index]
  2412  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
  2413  		if v == 0 {
  2414  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2415  		}
  2416  
  2417  		Xj := uint32(p.From.Reg & EXT_REG_MASK)
  2418  		Xd := uint32(p.To.Reg & EXT_REG_MASK)
  2419  		index := uint32(p.To.Index)
  2420  		c.checkindex(p, index, m)
  2421  		o1 = v | (index << 10) | (Xj << 5) | Xd
  2422  
  2423  	case 44: // vmov  xj.<T>[index], xd
  2424  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
  2425  		if v == 0 {
  2426  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2427  		}
  2428  
  2429  		Xj := uint32(p.From.Reg & EXT_REG_MASK)
  2430  		Xd := uint32(p.To.Reg & EXT_REG_MASK)
  2431  		index := uint32(p.From.Index)
  2432  		c.checkindex(p, index, m)
  2433  		o1 = v | (index << 10) | (Xj << 5) | Xd
  2434  
  2435  	case 45: // vmov  vj.<T>[index], vd.<T>
  2436  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
  2437  		if v == 0 {
  2438  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2439  		}
  2440  
  2441  		vj := uint32(p.From.Reg & EXT_REG_MASK)
  2442  		vd := uint32(p.To.Reg & EXT_REG_MASK)
  2443  		index := uint32(p.From.Index)
  2444  		c.checkindex(p, index, m)
  2445  		o1 = v | (index << 10) | (vj << 5) | vd
  2446  
  2447  	case 49:
  2448  		if p.As == ANOOP {
  2449  			// andi r0, r0, 0
  2450  			o1 = OP_12IRR(c.opirr(AAND), 0, 0, 0)
  2451  		} else {
  2452  			// undef
  2453  			o1 = OP_15I(c.opi(ABREAK), 0)
  2454  		}
  2455  
  2456  	// relocation operations
  2457  	case 50: // mov r,addr ==> pcalau12i + sw
  2458  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2459  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2460  			Type: objabi.R_LOONG64_ADDR_HI,
  2461  			Off:  int32(c.pc),
  2462  			Siz:  4,
  2463  			Sym:  p.To.Sym,
  2464  			Add:  p.To.Offset,
  2465  		})
  2466  		o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
  2467  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2468  			Type: objabi.R_LOONG64_ADDR_LO,
  2469  			Off:  int32(c.pc + 4),
  2470  			Siz:  4,
  2471  			Sym:  p.To.Sym,
  2472  			Add:  p.To.Offset,
  2473  		})
  2474  
  2475  	case 51: // mov addr,r ==> pcalau12i + lw
  2476  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2477  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2478  			Type: objabi.R_LOONG64_ADDR_HI,
  2479  			Off:  int32(c.pc),
  2480  			Siz:  4,
  2481  			Sym:  p.From.Sym,
  2482  			Add:  p.From.Offset,
  2483  		})
  2484  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
  2485  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2486  			Type: objabi.R_LOONG64_ADDR_LO,
  2487  			Off:  int32(c.pc + 4),
  2488  			Siz:  4,
  2489  			Sym:  p.From.Sym,
  2490  			Add:  p.From.Offset,
  2491  		})
  2492  
  2493  	case 52: // mov $ext, r
  2494  		// NOTE: this case does not use REGTMP. If it ever does,
  2495  		// remove the NOTUSETMP flag in optab.
  2496  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
  2497  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2498  			Type: objabi.R_LOONG64_ADDR_HI,
  2499  			Off:  int32(c.pc),
  2500  			Siz:  4,
  2501  			Sym:  p.From.Sym,
  2502  			Add:  p.From.Offset,
  2503  		})
  2504  		o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
  2505  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2506  			Type: objabi.R_LOONG64_ADDR_LO,
  2507  			Off:  int32(c.pc + 4),
  2508  			Siz:  4,
  2509  			Sym:  p.From.Sym,
  2510  			Add:  p.From.Offset,
  2511  		})
  2512  
  2513  	case 53: // mov r, tlsvar ==>  lu12i.w + ori + add r2, regtmp + sw o(regtmp)
  2514  		// NOTE: this case does not use REGTMP. If it ever does,
  2515  		// remove the NOTUSETMP flag in optab.
  2516  		o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
  2517  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2518  			Type: objabi.R_LOONG64_TLS_LE_HI,
  2519  			Off:  int32(c.pc),
  2520  			Siz:  4,
  2521  			Sym:  p.To.Sym,
  2522  			Add:  p.To.Offset,
  2523  		})
  2524  		o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2525  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2526  			Type: objabi.R_LOONG64_TLS_LE_LO,
  2527  			Off:  int32(c.pc + 4),
  2528  			Siz:  4,
  2529  			Sym:  p.To.Sym,
  2530  			Add:  p.To.Offset,
  2531  		})
  2532  		o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
  2533  		o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
  2534  
  2535  	case 54: // lu12i.w + ori + add r2, regtmp + lw o(regtmp)
  2536  		// NOTE: this case does not use REGTMP. If it ever does,
  2537  		// remove the NOTUSETMP flag in optab.
  2538  		o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
  2539  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2540  			Type: objabi.R_LOONG64_TLS_LE_HI,
  2541  			Off:  int32(c.pc),
  2542  			Siz:  4,
  2543  			Sym:  p.From.Sym,
  2544  			Add:  p.From.Offset,
  2545  		})
  2546  		o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2547  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2548  			Type: objabi.R_LOONG64_TLS_LE_LO,
  2549  			Off:  int32(c.pc + 4),
  2550  			Siz:  4,
  2551  			Sym:  p.From.Sym,
  2552  			Add:  p.From.Offset,
  2553  		})
  2554  		o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
  2555  		o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
  2556  
  2557  	case 56: // mov r, tlsvar IE model ==> (pcalau12i + ld.d)tlsvar@got + add.d + st.d
  2558  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2559  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2560  			Type: objabi.R_LOONG64_TLS_IE_HI,
  2561  			Off:  int32(c.pc),
  2562  			Siz:  4,
  2563  			Sym:  p.To.Sym,
  2564  		})
  2565  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2566  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2567  			Type: objabi.R_LOONG64_TLS_IE_LO,
  2568  			Off:  int32(c.pc + 4),
  2569  			Siz:  4,
  2570  			Sym:  p.To.Sym,
  2571  		})
  2572  		o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
  2573  		o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
  2574  
  2575  	case 57: // mov tlsvar, r IE model ==> (pcalau12i + ld.d)tlsvar@got + add.d + ld.d
  2576  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2577  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2578  			Type: objabi.R_LOONG64_TLS_IE_HI,
  2579  			Off:  int32(c.pc),
  2580  			Siz:  4,
  2581  			Sym:  p.From.Sym,
  2582  		})
  2583  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2584  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2585  			Type: objabi.R_LOONG64_TLS_IE_LO,
  2586  			Off:  int32(c.pc + 4),
  2587  			Siz:  4,
  2588  			Sym:  p.From.Sym,
  2589  		})
  2590  		o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
  2591  		o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
  2592  
  2593  	case 59: // mov $dcon,r
  2594  		// NOTE: this case does not use REGTMP. If it ever does,
  2595  		// remove the NOTUSETMP flag in optab.
  2596  		v := c.vregoff(&p.From)
  2597  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2598  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2599  		o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2600  		o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2601  
  2602  	case 60: // add $dcon,r1,r2
  2603  		v := c.vregoff(&p.From)
  2604  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2605  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2606  		o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2607  		o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2608  		r := int(p.Reg)
  2609  		if r == 0 {
  2610  			r = int(p.To.Reg)
  2611  		}
  2612  		o5 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2613  
  2614  	case 61: // word C_DCON
  2615  		o1 = uint32(c.vregoff(&p.From))
  2616  		o2 = uint32(c.vregoff(&p.From) >> 32)
  2617  
  2618  	case 62: // rdtimex rd, rj
  2619  		o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
  2620  
  2621  	case 65: // mov sym@GOT, r ==> pcalau12i + ld.d
  2622  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
  2623  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2624  			Type: objabi.R_LOONG64_GOT_HI,
  2625  			Off:  int32(c.pc),
  2626  			Siz:  4,
  2627  			Sym:  p.From.Sym,
  2628  		})
  2629  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
  2630  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2631  			Type: objabi.R_LOONG64_GOT_LO,
  2632  			Off:  int32(c.pc + 4),
  2633  			Siz:  4,
  2634  			Sym:  p.From.Sym,
  2635  		})
  2636  
  2637  	case 66: // am* From, To, RegTo2 ==> am* RegTo2, From, To
  2638  		rk := p.From.Reg
  2639  		rj := p.To.Reg
  2640  		rd := p.RegTo2
  2641  
  2642  		// See section 2.2.7.1 of https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
  2643  		// for the register usage constraints.
  2644  		if rd == rj || rd == rk {
  2645  			c.ctxt.Diag("illegal register combination: %v\n", p)
  2646  		}
  2647  		o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
  2648  
  2649  	case 67: // mov $dcon12_0, r
  2650  		v := c.vregoff(&p.From)
  2651  		o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(p.To.Reg))
  2652  
  2653  	case 68: // mov $dcon12_20S, r
  2654  		v := c.vregoff(&p.From)
  2655  		contype := c.aclass(&p.From)
  2656  		switch contype {
  2657  		default: // C_DCON12_20S
  2658  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2659  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2660  		case C_DCON20S_20:
  2661  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2662  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2663  		case C_DCON12_12S:
  2664  			o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(p.To.Reg))
  2665  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2666  		case C_DCON20S_12S, C_DCON20S_0:
  2667  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
  2668  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2669  		case C_DCON12_12U:
  2670  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
  2671  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2672  		case C_DCON20S_12U:
  2673  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
  2674  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2675  		}
  2676  
  2677  	case 69: // mov $dcon32_12S, r
  2678  		v := c.vregoff(&p.From)
  2679  		contype := c.aclass(&p.From)
  2680  		switch contype {
  2681  		default: // C_DCON32_12S, C_DCON32_0
  2682  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
  2683  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2684  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2685  		case C_DCON32_20:
  2686  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2687  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2688  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2689  		case C_DCON12_32S:
  2690  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2691  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2692  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2693  		case C_DCON20S_32:
  2694  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2695  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2696  			o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2697  		case C_DCON32_12U:
  2698  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
  2699  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2700  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2701  		}
  2702  
  2703  	case 70: // add $dcon12_0,[r1],r2
  2704  		v := c.vregoff(&p.From)
  2705  		r := int(p.Reg)
  2706  		if r == 0 {
  2707  			r = int(p.To.Reg)
  2708  		}
  2709  		o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(REGTMP))
  2710  		o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2711  
  2712  	case 71: // add $dcon12_20S,[r1],r2
  2713  		v := c.vregoff(&p.From)
  2714  		r := int(p.Reg)
  2715  		if r == 0 {
  2716  			r = int(p.To.Reg)
  2717  		}
  2718  		contype := c.aclass(&p.From)
  2719  		switch contype {
  2720  		default: // C_DCON12_20S
  2721  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2722  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2723  		case C_DCON20S_20:
  2724  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2725  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2726  		case C_DCON12_12S:
  2727  			o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(REGTMP))
  2728  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2729  		case C_DCON20S_12S, C_DCON20S_0:
  2730  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
  2731  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2732  		case C_DCON12_12U:
  2733  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
  2734  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2735  		case C_DCON20S_12U:
  2736  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
  2737  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2738  		}
  2739  		o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2740  
  2741  	case 72: // add $dcon32_12S,[r1],r2
  2742  		v := c.vregoff(&p.From)
  2743  		r := int(p.Reg)
  2744  		if r == 0 {
  2745  			r = int(p.To.Reg)
  2746  		}
  2747  		contype := c.aclass(&p.From)
  2748  		switch contype {
  2749  		default: // C_DCON32_12S, C_DCON32_0
  2750  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
  2751  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2752  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2753  		case C_DCON32_20:
  2754  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2755  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2756  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2757  		case C_DCON12_32S:
  2758  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2759  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2760  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2761  		case C_DCON20S_32:
  2762  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2763  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2764  			o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2765  		case C_DCON32_12U:
  2766  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
  2767  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2768  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2769  		}
  2770  		o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2771  	}
  2772  
  2773  	out[0] = o1
  2774  	out[1] = o2
  2775  	out[2] = o3
  2776  	out[3] = o4
  2777  	out[4] = o5
  2778  }
  2779  
  2780  // checkoperand checks if operand >= 0 && operand <= maxoperand
  2781  func (c *ctxt0) checkoperand(p *obj.Prog, operand uint32, mask uint32) {
  2782  	if (operand & ^mask) != 0 {
  2783  		c.ctxt.Diag("operand out of range 0 to %d: %v", mask, p)
  2784  	}
  2785  }
  2786  
  2787  // checkindex checks if index >= 0 && index <= maxindex
  2788  func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32) {
  2789  	if (index & ^mask) != 0 {
  2790  		c.ctxt.Diag("register element index out of range 0 to %d: %v", mask, p)
  2791  	}
  2792  }
  2793  
  2794  func (c *ctxt0) vregoff(a *obj.Addr) int64 {
  2795  	c.instoffset = 0
  2796  	c.aclass(a)
  2797  	return c.instoffset
  2798  }
  2799  
  2800  func (c *ctxt0) regoff(a *obj.Addr) int32 {
  2801  	return int32(c.vregoff(a))
  2802  }
  2803  
  2804  func (c *ctxt0) oprrrr(a obj.As) uint32 {
  2805  	switch a {
  2806  	case AFMADDF:
  2807  		return 0x81 << 20 // fmadd.s
  2808  	case AFMADDD:
  2809  		return 0x82 << 20 // fmadd.d
  2810  	case AFMSUBF:
  2811  		return 0x85 << 20 // fmsub.s
  2812  	case AFMSUBD:
  2813  		return 0x86 << 20 // fmsub.d
  2814  	case AFNMADDF:
  2815  		return 0x89 << 20 // fnmadd.f
  2816  	case AFNMADDD:
  2817  		return 0x8a << 20 // fnmadd.d
  2818  	case AFNMSUBF:
  2819  		return 0x8d << 20 // fnmsub.s
  2820  	case AFNMSUBD:
  2821  		return 0x8e << 20 // fnmsub.d
  2822  	}
  2823  
  2824  	c.ctxt.Diag("bad rrrr opcode %v", a)
  2825  	return 0
  2826  }
  2827  
  2828  func (c *ctxt0) oprrr(a obj.As) uint32 {
  2829  	switch a {
  2830  	case AADD:
  2831  		return 0x20 << 15
  2832  	case AADDU:
  2833  		return 0x20 << 15
  2834  	case ASGT:
  2835  		return 0x24 << 15 // SLT
  2836  	case ASGTU:
  2837  		return 0x25 << 15 // SLTU
  2838  	case AMASKEQZ:
  2839  		return 0x26 << 15
  2840  	case AMASKNEZ:
  2841  		return 0x27 << 15
  2842  	case AAND:
  2843  		return 0x29 << 15
  2844  	case AOR:
  2845  		return 0x2a << 15
  2846  	case AXOR:
  2847  		return 0x2b << 15
  2848  	case AORN:
  2849  		return 0x2c << 15 // orn
  2850  	case AANDN:
  2851  		return 0x2d << 15 // andn
  2852  	case ASUB:
  2853  		return 0x22 << 15
  2854  	case ASUBU, ANEGW:
  2855  		return 0x22 << 15
  2856  	case ANOR:
  2857  		return 0x28 << 15
  2858  	case ASLL:
  2859  		return 0x2e << 15
  2860  	case ASRL:
  2861  		return 0x2f << 15
  2862  	case ASRA:
  2863  		return 0x30 << 15
  2864  	case AROTR:
  2865  		return 0x36 << 15
  2866  	case ASLLV:
  2867  		return 0x31 << 15
  2868  	case ASRLV:
  2869  		return 0x32 << 15
  2870  	case ASRAV:
  2871  		return 0x33 << 15
  2872  	case AROTRV:
  2873  		return 0x37 << 15
  2874  	case AADDV:
  2875  		return 0x21 << 15
  2876  	case AADDVU:
  2877  		return 0x21 << 15
  2878  	case ASUBV:
  2879  		return 0x23 << 15
  2880  	case ASUBVU, ANEGV:
  2881  		return 0x23 << 15
  2882  
  2883  	case AMUL:
  2884  		return 0x38 << 15 // mul.w
  2885  	case AMULU:
  2886  		return 0x38 << 15 // mul.w
  2887  	case AMULH:
  2888  		return 0x39 << 15 // mulh.w
  2889  	case AMULHU:
  2890  		return 0x3a << 15 // mulhu.w
  2891  	case AMULV:
  2892  		return 0x3b << 15 // mul.d
  2893  	case AMULVU:
  2894  		return 0x3b << 15 // mul.d
  2895  	case AMULHV:
  2896  		return 0x3c << 15 // mulh.d
  2897  	case AMULHVU:
  2898  		return 0x3d << 15 // mulhu.d
  2899  	case ADIV:
  2900  		return 0x40 << 15 // div.w
  2901  	case ADIVU:
  2902  		return 0x42 << 15 // div.wu
  2903  	case ADIVV:
  2904  		return 0x44 << 15 // div.d
  2905  	case ADIVVU:
  2906  		return 0x46 << 15 // div.du
  2907  	case AREM:
  2908  		return 0x41 << 15 // mod.w
  2909  	case AREMU:
  2910  		return 0x43 << 15 // mod.wu
  2911  	case AREMV:
  2912  		return 0x45 << 15 // mod.d
  2913  	case AREMVU:
  2914  		return 0x47 << 15 // mod.du
  2915  	case ACRCWBW:
  2916  		return 0x48 << 15 // crc.w.b.w
  2917  	case ACRCWHW:
  2918  		return 0x49 << 15 // crc.w.h.w
  2919  	case ACRCWWW:
  2920  		return 0x4a << 15 // crc.w.w.w
  2921  	case ACRCWVW:
  2922  		return 0x4b << 15 // crc.w.d.w
  2923  	case ACRCCWBW:
  2924  		return 0x4c << 15 // crcc.w.b.w
  2925  	case ACRCCWHW:
  2926  		return 0x4d << 15 // crcc.w.h.w
  2927  	case ACRCCWWW:
  2928  		return 0x4e << 15 // crcc.w.w.w
  2929  	case ACRCCWVW:
  2930  		return 0x4f << 15 // crcc.w.d.w
  2931  	case AJMP:
  2932  		return 0x13 << 26 // jirl r0, rj, 0
  2933  	case AJAL:
  2934  		return (0x13 << 26) | 1 // jirl r1, rj, 0
  2935  
  2936  	case ADIVF:
  2937  		return 0x20d << 15
  2938  	case ADIVD:
  2939  		return 0x20e << 15
  2940  	case AMULF:
  2941  		return 0x209 << 15
  2942  	case AMULD:
  2943  		return 0x20a << 15
  2944  	case ASUBF:
  2945  		return 0x205 << 15
  2946  	case ASUBD:
  2947  		return 0x206 << 15
  2948  	case AADDF:
  2949  		return 0x201 << 15
  2950  	case AADDD:
  2951  		return 0x202 << 15
  2952  	case ACMPEQF:
  2953  		return 0x0c1<<20 | 0x4<<15 // FCMP.CEQ.S
  2954  	case ACMPEQD:
  2955  		return 0x0c2<<20 | 0x4<<15 // FCMP.CEQ.D
  2956  	case ACMPGED:
  2957  		return 0x0c2<<20 | 0x7<<15 // FCMP.SLE.D
  2958  	case ACMPGEF:
  2959  		return 0x0c1<<20 | 0x7<<15 // FCMP.SLE.S
  2960  	case ACMPGTD:
  2961  		return 0x0c2<<20 | 0x3<<15 // FCMP.SLT.D
  2962  	case ACMPGTF:
  2963  		return 0x0c1<<20 | 0x3<<15 // FCMP.SLT.S
  2964  	case AFMINF:
  2965  		return 0x215 << 15 // fmin.s
  2966  	case AFMIND:
  2967  		return 0x216 << 15 // fmin.d
  2968  	case AFMAXF:
  2969  		return 0x211 << 15 // fmax.s
  2970  	case AFMAXD:
  2971  		return 0x212 << 15 // fmax.d
  2972  	case AFMAXAF:
  2973  		return 0x219 << 15 // fmaxa.s
  2974  	case AFMAXAD:
  2975  		return 0x21a << 15 // fmaxa.d
  2976  	case AFMINAF:
  2977  		return 0x21d << 15 // fmina.s
  2978  	case AFMINAD:
  2979  		return 0x21e << 15 // fmina.d
  2980  	case AFSCALEBF:
  2981  		return 0x221 << 15 // fscaleb.s
  2982  	case AFSCALEBD:
  2983  		return 0x222 << 15 // fscaleb.d
  2984  	case AFCOPYSGF:
  2985  		return 0x225 << 15 // fcopysign.s
  2986  	case AFCOPYSGD:
  2987  		return 0x226 << 15 // fcopysign.d
  2988  	case -AMOVB:
  2989  		return 0x07000 << 15 // ldx.b
  2990  	case -AMOVH:
  2991  		return 0x07008 << 15 // ldx.h
  2992  	case -AMOVW:
  2993  		return 0x07010 << 15 // ldx.w
  2994  	case -AMOVV:
  2995  		return 0x07018 << 15 // ldx.d
  2996  	case -AMOVBU:
  2997  		return 0x07040 << 15 // ldx.bu
  2998  	case -AMOVHU:
  2999  		return 0x07048 << 15 // ldx.hu
  3000  	case -AMOVWU:
  3001  		return 0x07050 << 15 // ldx.wu
  3002  	case AMOVB:
  3003  		return 0x07020 << 15 // stx.b
  3004  	case AMOVH:
  3005  		return 0x07028 << 15 // stx.h
  3006  	case AMOVW:
  3007  		return 0x07030 << 15 // stx.w
  3008  	case AMOVV:
  3009  		return 0x07038 << 15 // stx.d
  3010  	case -AMOVF:
  3011  		return 0x07060 << 15 // fldx.s
  3012  	case -AMOVD:
  3013  		return 0x07068 << 15 // fldx.d
  3014  	case AMOVF:
  3015  		return 0x07070 << 15 // fstx.s
  3016  	case AMOVD:
  3017  		return 0x07078 << 15 // fstx.d
  3018  	case -AVMOVQ:
  3019  		return 0x07080 << 15 // vldx
  3020  	case -AXVMOVQ:
  3021  		return 0x07090 << 15 // xvldx
  3022  	case AVMOVQ:
  3023  		return 0x07088 << 15 // vstx
  3024  	case AXVMOVQ:
  3025  		return 0x07098 << 15 // xvstx
  3026  	case AVSEQB:
  3027  		return 0x0e000 << 15 // vseq.b
  3028  	case AXVSEQB:
  3029  		return 0x0e800 << 15 // xvseq.b
  3030  	case AVSEQH:
  3031  		return 0x0e001 << 15 // vseq.h
  3032  	case AXVSEQH:
  3033  		return 0x0e801 << 15 // xvseq.h
  3034  	case AVSEQW:
  3035  		return 0x0e002 << 15 // vseq.w
  3036  	case AXVSEQW:
  3037  		return 0x0e802 << 15 // xvseq.w
  3038  	case AVSEQV:
  3039  		return 0x0e003 << 15 // vseq.d
  3040  	case AXVSEQV:
  3041  		return 0x0e803 << 15 // xvseq.d
  3042  	case AVANDV:
  3043  		return 0x0E24C << 15 // vand.v
  3044  	case AVORV:
  3045  		return 0x0E24D << 15 // vor.v
  3046  	case AVXORV:
  3047  		return 0x0E24E << 15 // vxor.v
  3048  	case AVNORV:
  3049  		return 0x0E24F << 15 // vnor.v
  3050  	case AVANDNV:
  3051  		return 0x0E250 << 15 // vandn.v
  3052  	case AVORNV:
  3053  		return 0x0E251 << 15 // vorn.v
  3054  	case AXVANDV:
  3055  		return 0x0EA4C << 15 // xvand.v
  3056  	case AXVORV:
  3057  		return 0x0EA4D << 15 // xvor.v
  3058  	case AXVXORV:
  3059  		return 0x0EA4E << 15 // xvxor.v
  3060  	case AXVNORV:
  3061  		return 0x0EA4F << 15 // xvnor.v
  3062  	case AXVANDNV:
  3063  		return 0x0EA50 << 15 // xvandn.v
  3064  	case AXVORNV:
  3065  		return 0x0EA51 << 15 // xvorn.v
  3066  	case AVDIVB:
  3067  		return 0xe1c0 << 15 // vdiv.b
  3068  	case AVDIVH:
  3069  		return 0xe1c1 << 15 // vdiv.h
  3070  	case AVDIVW:
  3071  		return 0xe1c2 << 15 // vdiv.w
  3072  	case AVDIVV:
  3073  		return 0xe1c3 << 15 // vdiv.d
  3074  	case AVMODB:
  3075  		return 0xe1c4 << 15 // vmod.b
  3076  	case AVMODH:
  3077  		return 0xe1c5 << 15 // vmod.h
  3078  	case AVMODW:
  3079  		return 0xe1c6 << 15 // vmod.w
  3080  	case AVMODV:
  3081  		return 0xe1c7 << 15 // vmod.d
  3082  	case AVDIVBU:
  3083  		return 0xe1c8 << 15 // vdiv.bu
  3084  	case AVDIVHU:
  3085  		return 0xe1c9 << 15 // vdiv.hu
  3086  	case AVDIVWU:
  3087  		return 0xe1ca << 15 // vdiv.wu
  3088  	case AVDIVVU:
  3089  		return 0xe1cb << 15 // vdiv.du
  3090  	case AVMODBU:
  3091  		return 0xe1cc << 15 // vmod.bu
  3092  	case AVMODHU:
  3093  		return 0xe1cd << 15 // vmod.hu
  3094  	case AVMODWU:
  3095  		return 0xe1ce << 15 // vmod.wu
  3096  	case AVMODVU:
  3097  		return 0xe1cf << 15 // vmod.du
  3098  	case AXVDIVB:
  3099  		return 0xe9c0 << 15 // xvdiv.b
  3100  	case AXVDIVH:
  3101  		return 0xe9c1 << 15 // xvdiv.h
  3102  	case AXVDIVW:
  3103  		return 0xe9c2 << 15 // xvdiv.w
  3104  	case AXVDIVV:
  3105  		return 0xe9c3 << 15 // xvdiv.d
  3106  	case AXVMODB:
  3107  		return 0xe9c4 << 15 // xvmod.b
  3108  	case AXVMODH:
  3109  		return 0xe9c5 << 15 // xvmod.h
  3110  	case AXVMODW:
  3111  		return 0xe9c6 << 15 // xvmod.w
  3112  	case AXVMODV:
  3113  		return 0xe9c7 << 15 // xvmod.d
  3114  	case AXVDIVBU:
  3115  		return 0xe9c8 << 15 // xvdiv.bu
  3116  	case AXVDIVHU:
  3117  		return 0xe9c9 << 15 // xvdiv.hu
  3118  	case AXVDIVWU:
  3119  		return 0xe9ca << 15 // xvdiv.wu
  3120  	case AXVDIVVU:
  3121  		return 0xe9cb << 15 // xvdiv.du
  3122  	case AXVMODBU:
  3123  		return 0xe9cc << 15 // xvmod.bu
  3124  	case AXVMODHU:
  3125  		return 0xe9cd << 15 // xvmod.hu
  3126  	case AXVMODWU:
  3127  		return 0xe9ce << 15 // xvmod.wu
  3128  	case AXVMODVU:
  3129  		return 0xe9cf << 15 // xvmod.du
  3130  	case AVMULWEVHB:
  3131  		return 0xe120 << 15 // vmulwev.h.b
  3132  	case AVMULWEVWH:
  3133  		return 0xe121 << 15 // vmulwev.w.h
  3134  	case AVMULWEVVW:
  3135  		return 0xe122 << 15 // vmulwev.d.w
  3136  	case AVMULWEVQV:
  3137  		return 0xe123 << 15 // vmulwev.q.d
  3138  	case AVMULWODHB:
  3139  		return 0xe124 << 15 // vmulwod.h.b
  3140  	case AVMULWODWH:
  3141  		return 0xe125 << 15 // vmulwod.w.h
  3142  	case AVMULWODVW:
  3143  		return 0xe126 << 15 // vmulwod.d.w
  3144  	case AVMULWODQV:
  3145  		return 0xe127 << 15 // vmulwod.q.d
  3146  	case AVMULWEVHBU:
  3147  		return 0xe130 << 15 // vmulwev.h.bu
  3148  	case AVMULWEVWHU:
  3149  		return 0xe131 << 15 // vmulwev.w.hu
  3150  	case AVMULWEVVWU:
  3151  		return 0xe132 << 15 // vmulwev.d.wu
  3152  	case AVMULWEVQVU:
  3153  		return 0xe133 << 15 // vmulwev.q.du
  3154  	case AVMULWODHBU:
  3155  		return 0xe134 << 15 // vmulwod.h.bu
  3156  	case AVMULWODWHU:
  3157  		return 0xe135 << 15 // vmulwod.w.hu
  3158  	case AVMULWODVWU:
  3159  		return 0xe136 << 15 // vmulwod.d.wu
  3160  	case AVMULWODQVU:
  3161  		return 0xe137 << 15 // vmulwod.q.du
  3162  	case AVMULWEVHBUB:
  3163  		return 0xe140 << 15 // vmulwev.h.bu.b
  3164  	case AVMULWEVWHUH:
  3165  		return 0xe141 << 15 // vmulwev.w.hu.h
  3166  	case AVMULWEVVWUW:
  3167  		return 0xe142 << 15 // vmulwev.d.wu.w
  3168  	case AVMULWEVQVUV:
  3169  		return 0xe143 << 15 // vmulwev.q.du.d
  3170  	case AVMULWODHBUB:
  3171  		return 0xe144 << 15 // vmulwod.h.bu.b
  3172  	case AVMULWODWHUH:
  3173  		return 0xe145 << 15 // vmulwod.w.hu.h
  3174  	case AVMULWODVWUW:
  3175  		return 0xe146 << 15 // vmulwod.d.wu.w
  3176  	case AVMULWODQVUV:
  3177  		return 0xe147 << 15 // vmulwod.q.du.d
  3178  	case AXVMULWEVHB:
  3179  		return 0xe920 << 15 // xvmulwev.h.b
  3180  	case AXVMULWEVWH:
  3181  		return 0xe921 << 15 // xvmulwev.w.h
  3182  	case AXVMULWEVVW:
  3183  		return 0xe922 << 15 // xvmulwev.d.w
  3184  	case AXVMULWEVQV:
  3185  		return 0xe923 << 15 // xvmulwev.q.d
  3186  	case AXVMULWODHB:
  3187  		return 0xe924 << 15 // xvmulwod.h.b
  3188  	case AXVMULWODWH:
  3189  		return 0xe925 << 15 // xvmulwod.w.h
  3190  	case AXVMULWODVW:
  3191  		return 0xe926 << 15 // xvmulwod.d.w
  3192  	case AXVMULWODQV:
  3193  		return 0xe927 << 15 // xvmulwod.q.d
  3194  	case AXVMULWEVHBU:
  3195  		return 0xe930 << 15 // xvmulwev.h.bu
  3196  	case AXVMULWEVWHU:
  3197  		return 0xe931 << 15 // xvmulwev.w.hu
  3198  	case AXVMULWEVVWU:
  3199  		return 0xe932 << 15 // xvmulwev.d.wu
  3200  	case AXVMULWEVQVU:
  3201  		return 0xe933 << 15 // xvmulwev.q.du
  3202  	case AXVMULWODHBU:
  3203  		return 0xe934 << 15 // xvmulwod.h.bu
  3204  	case AXVMULWODWHU:
  3205  		return 0xe935 << 15 // xvmulwod.w.hu
  3206  	case AXVMULWODVWU:
  3207  		return 0xe936 << 15 // xvmulwod.d.wu
  3208  	case AXVMULWODQVU:
  3209  		return 0xe937 << 15 // xvmulwod.q.du
  3210  	case AXVMULWEVHBUB:
  3211  		return 0xe940 << 15 // xvmulwev.h.bu.b
  3212  	case AXVMULWEVWHUH:
  3213  		return 0xe941 << 15 // xvmulwev.w.hu.h
  3214  	case AXVMULWEVVWUW:
  3215  		return 0xe942 << 15 // xvmulwev.d.wu.w
  3216  	case AXVMULWEVQVUV:
  3217  		return 0xe943 << 15 // xvmulwev.q.du.d
  3218  	case AXVMULWODHBUB:
  3219  		return 0xe944 << 15 // xvmulwod.h.bu.b
  3220  	case AXVMULWODWHUH:
  3221  		return 0xe945 << 15 // xvmulwod.w.hu.h
  3222  	case AXVMULWODVWUW:
  3223  		return 0xe946 << 15 // xvmulwod.d.wu.w
  3224  	case AXVMULWODQVUV:
  3225  		return 0xe947 << 15 // xvmulwod.q.du.d
  3226  	case AVSLLB:
  3227  		return 0xe1d0 << 15 // vsll.b
  3228  	case AVSLLH:
  3229  		return 0xe1d1 << 15 // vsll.h
  3230  	case AVSLLW:
  3231  		return 0xe1d2 << 15 // vsll.w
  3232  	case AVSLLV:
  3233  		return 0xe1d3 << 15 // vsll.d
  3234  	case AVSRLB:
  3235  		return 0xe1d4 << 15 // vsrl.b
  3236  	case AVSRLH:
  3237  		return 0xe1d5 << 15 // vsrl.h
  3238  	case AVSRLW:
  3239  		return 0xe1d6 << 15 // vsrl.w
  3240  	case AVSRLV:
  3241  		return 0xe1d7 << 15 // vsrl.d
  3242  	case AVSRAB:
  3243  		return 0xe1d8 << 15 // vsra.b
  3244  	case AVSRAH:
  3245  		return 0xe1d9 << 15 // vsra.h
  3246  	case AVSRAW:
  3247  		return 0xe1da << 15 // vsra.w
  3248  	case AVSRAV:
  3249  		return 0xe1db << 15 // vsra.d
  3250  	case AVROTRB:
  3251  		return 0xe1dc << 15 // vrotr.b
  3252  	case AVROTRH:
  3253  		return 0xe1dd << 15 // vrotr.h
  3254  	case AVROTRW:
  3255  		return 0xe1de << 15 // vrotr.w
  3256  	case AVROTRV:
  3257  		return 0xe1df << 15 // vrotr.d
  3258  	case AXVSLLB:
  3259  		return 0xe9d0 << 15 // xvsll.b
  3260  	case AXVSLLH:
  3261  		return 0xe9d1 << 15 // xvsll.h
  3262  	case AXVSLLW:
  3263  		return 0xe9d2 << 15 // xvsll.w
  3264  	case AXVSLLV:
  3265  		return 0xe9d3 << 15 // xvsll.d
  3266  	case AXVSRLB:
  3267  		return 0xe9d4 << 15 // xvsrl.b
  3268  	case AXVSRLH:
  3269  		return 0xe9d5 << 15 // xvsrl.h
  3270  	case AXVSRLW:
  3271  		return 0xe9d6 << 15 // xvsrl.w
  3272  	case AXVSRLV:
  3273  		return 0xe9d7 << 15 // xvsrl.d
  3274  	case AXVSRAB:
  3275  		return 0xe9d8 << 15 // xvsra.b
  3276  	case AXVSRAH:
  3277  		return 0xe9d9 << 15 // xvsra.h
  3278  	case AXVSRAW:
  3279  		return 0xe9da << 15 // xvsra.w
  3280  	case AXVSRAV:
  3281  		return 0xe9db << 15 // xvsra.d
  3282  	case AXVROTRB:
  3283  		return 0xe9dc << 15 // xvrotr.b
  3284  	case AXVROTRH:
  3285  		return 0xe9dd << 15 // xvrotr.h
  3286  	case AXVROTRW:
  3287  		return 0xe9de << 15 // xvrotr.w
  3288  	case AXVROTRV:
  3289  		return 0xe9df << 15 // xvrotr.d
  3290  	case AVADDB:
  3291  		return 0xe014 << 15 // vadd.b
  3292  	case AVADDH:
  3293  		return 0xe015 << 15 // vadd.h
  3294  	case AVADDW:
  3295  		return 0xe016 << 15 // vadd.w
  3296  	case AVADDV:
  3297  		return 0xe017 << 15 // vadd.d
  3298  	case AVADDQ:
  3299  		return 0xe25a << 15 // vadd.q
  3300  	case AVSUBB:
  3301  		return 0xe018 << 15 // vsub.b
  3302  	case AVSUBH:
  3303  		return 0xe019 << 15 // vsub.h
  3304  	case AVSUBW:
  3305  		return 0xe01a << 15 // vsub.w
  3306  	case AVSUBV:
  3307  		return 0xe01b << 15 // vsub.d
  3308  	case AVSUBQ:
  3309  		return 0xe25b << 15 // vsub.q
  3310  	case AXVADDB:
  3311  		return 0xe814 << 15 // xvadd.b
  3312  	case AXVADDH:
  3313  		return 0xe815 << 15 // xvadd.h
  3314  	case AXVADDW:
  3315  		return 0xe816 << 15 // xvadd.w
  3316  	case AXVADDV:
  3317  		return 0xe817 << 15 // xvadd.d
  3318  	case AXVADDQ:
  3319  		return 0xea5a << 15 // xvadd.q
  3320  	case AXVSUBB:
  3321  		return 0xe818 << 15 // xvsub.b
  3322  	case AXVSUBH:
  3323  		return 0xe819 << 15 // xvsub.h
  3324  	case AXVSUBW:
  3325  		return 0xe81a << 15 // xvsub.w
  3326  	case AXVSUBV:
  3327  		return 0xe81b << 15 // xvsub.d
  3328  	case AXVSUBQ:
  3329  		return 0xea5b << 15 // xvsub.q
  3330  	case AVILVLB:
  3331  		return 0xe234 << 15 // vilvl.b
  3332  	case AVILVLH:
  3333  		return 0xe235 << 15 // vilvl.h
  3334  	case AVILVLW:
  3335  		return 0xe236 << 15 // vilvl.w
  3336  	case AVILVLV:
  3337  		return 0xe237 << 15 // vilvl.d
  3338  	case AVILVHB:
  3339  		return 0xe238 << 15 // vilvh.b
  3340  	case AVILVHH:
  3341  		return 0xe239 << 15 // vilvh.h
  3342  	case AVILVHW:
  3343  		return 0xe23a << 15 // vilvh.w
  3344  	case AVILVHV:
  3345  		return 0xe23b << 15 // vilvh.d
  3346  	case AXVILVLB:
  3347  		return 0xea34 << 15 // xvilvl.b
  3348  	case AXVILVLH:
  3349  		return 0xea35 << 15 // xvilvl.h
  3350  	case AXVILVLW:
  3351  		return 0xea36 << 15 // xvilvl.w
  3352  	case AXVILVLV:
  3353  		return 0xea37 << 15 // xvilvl.d
  3354  	case AXVILVHB:
  3355  		return 0xea38 << 15 // xvilvh.b
  3356  	case AXVILVHH:
  3357  		return 0xea39 << 15 // xvilvh.h
  3358  	case AXVILVHW:
  3359  		return 0xea3a << 15 // xvilvh.w
  3360  	case AXVILVHV:
  3361  		return 0xea3b << 15 // xvilvh.d
  3362  	case AVMULB:
  3363  		return 0xe108 << 15 // vmul.b
  3364  	case AVMULH:
  3365  		return 0xe109 << 15 // vmul.h
  3366  	case AVMULW:
  3367  		return 0xe10a << 15 // vmul.w
  3368  	case AVMULV:
  3369  		return 0xe10b << 15 // vmul.d
  3370  	case AVMUHB:
  3371  		return 0xe10c << 15 // vmuh.b
  3372  	case AVMUHH:
  3373  		return 0xe10d << 15 // vmuh.h
  3374  	case AVMUHW:
  3375  		return 0xe10e << 15 // vmuh.w
  3376  	case AVMUHV:
  3377  		return 0xe10f << 15 // vmuh.d
  3378  	case AVMUHBU:
  3379  		return 0xe110 << 15 // vmuh.bu
  3380  	case AVMUHHU:
  3381  		return 0xe111 << 15 // vmuh.hu
  3382  	case AVMUHWU:
  3383  		return 0xe112 << 15 // vmuh.wu
  3384  	case AVMUHVU:
  3385  		return 0xe113 << 15 // vmuh.du
  3386  	case AXVMULB:
  3387  		return 0xe908 << 15 // xvmul.b
  3388  	case AXVMULH:
  3389  		return 0xe909 << 15 // xvmul.h
  3390  	case AXVMULW:
  3391  		return 0xe90a << 15 // xvmul.w
  3392  	case AXVMULV:
  3393  		return 0xe90b << 15 // xvmul.d
  3394  	case AXVMUHB:
  3395  		return 0xe90c << 15 // xvmuh.b
  3396  	case AXVMUHH:
  3397  		return 0xe90d << 15 // xvmuh.h
  3398  	case AXVMUHW:
  3399  		return 0xe90e << 15 // xvmuh.w
  3400  	case AXVMUHV:
  3401  		return 0xe90f << 15 // xvmuh.d
  3402  	case AXVMUHBU:
  3403  		return 0xe910 << 15 // xvmuh.bu
  3404  	case AXVMUHHU:
  3405  		return 0xe911 << 15 // xvmuh.hu
  3406  	case AXVMUHWU:
  3407  		return 0xe912 << 15 // xvmuh.wu
  3408  	case AXVMUHVU:
  3409  		return 0xe913 << 15 // xvmuh.du
  3410  	case AVADDF:
  3411  		return 0xe261 << 15 // vfadd.s
  3412  	case AVADDD:
  3413  		return 0xe262 << 15 // vfadd.d
  3414  	case AVSUBF:
  3415  		return 0xe265 << 15 // vfsub.s
  3416  	case AVSUBD:
  3417  		return 0xe266 << 15 // vfsub.d
  3418  	case AVMULF:
  3419  		return 0xe271 << 15 // vfmul.s
  3420  	case AVMULD:
  3421  		return 0xe272 << 15 // vfmul.d
  3422  	case AVDIVF:
  3423  		return 0xe275 << 15 // vfdiv.s
  3424  	case AVDIVD:
  3425  		return 0xe276 << 15 // vfdiv.d
  3426  	case AXVADDF:
  3427  		return 0xea61 << 15 // xvfadd.s
  3428  	case AXVADDD:
  3429  		return 0xea62 << 15 // xvfadd.d
  3430  	case AXVSUBF:
  3431  		return 0xea65 << 15 // xvfsub.s
  3432  	case AXVSUBD:
  3433  		return 0xea66 << 15 // xvfsub.d
  3434  	case AXVMULF:
  3435  		return 0xea71 << 15 // xvfmul.s
  3436  	case AXVMULD:
  3437  		return 0xea72 << 15 // xvfmul.d
  3438  	case AXVDIVF:
  3439  		return 0xea75 << 15 // xvfdiv.s
  3440  	case AXVDIVD:
  3441  		return 0xea76 << 15 // xvfdiv.d
  3442  	}
  3443  
  3444  	if a < 0 {
  3445  		c.ctxt.Diag("bad rrr opcode -%v", -a)
  3446  	} else {
  3447  		c.ctxt.Diag("bad rrr opcode %v", a)
  3448  	}
  3449  	return 0
  3450  }
  3451  
  3452  func (c *ctxt0) oprr(a obj.As) uint32 {
  3453  	switch a {
  3454  	case ACLOW:
  3455  		return 0x4 << 10 // clo.w
  3456  	case ACLZW:
  3457  		return 0x5 << 10 // clz.w
  3458  	case ACTOW:
  3459  		return 0x6 << 10 // cto.w
  3460  	case ACTZW:
  3461  		return 0x7 << 10 // ctz.w
  3462  	case ACLOV:
  3463  		return 0x8 << 10 // clo.d
  3464  	case ACLZV:
  3465  		return 0x9 << 10 // clz.d
  3466  	case ACTOV:
  3467  		return 0xa << 10 // cto.d
  3468  	case ACTZV:
  3469  		return 0xb << 10 // ctz.d
  3470  	case AREVB2H:
  3471  		return 0xc << 10 // revb.2h
  3472  	case AREVB4H:
  3473  		return 0xd << 10 // revb.4h
  3474  	case AREVB2W:
  3475  		return 0xe << 10 // revb.2w
  3476  	case AREVBV:
  3477  		return 0xf << 10 // revb.d
  3478  	case AREVH2W:
  3479  		return 0x10 << 10 // revh.2w
  3480  	case AREVHV:
  3481  		return 0x11 << 10 // revh.d
  3482  	case ABITREV4B:
  3483  		return 0x12 << 10 // bitrev.4b
  3484  	case ABITREV8B:
  3485  		return 0x13 << 10 // bitrev.8b
  3486  	case ABITREVW:
  3487  		return 0x14 << 10 // bitrev.w
  3488  	case ABITREVV:
  3489  		return 0x15 << 10 // bitrev.d
  3490  	case AEXTWH:
  3491  		return 0x16 << 10 // ext.w.h
  3492  	case AEXTWB:
  3493  		return 0x17 << 10 // ext.w.h
  3494  	case ACPUCFG:
  3495  		return 0x1b << 10
  3496  	case ARDTIMELW:
  3497  		return 0x18 << 10
  3498  	case ARDTIMEHW:
  3499  		return 0x19 << 10
  3500  	case ARDTIMED:
  3501  		return 0x1a << 10
  3502  	case ATRUNCFV:
  3503  		return 0x46a9 << 10
  3504  	case ATRUNCDV:
  3505  		return 0x46aa << 10
  3506  	case ATRUNCFW:
  3507  		return 0x46a1 << 10
  3508  	case ATRUNCDW:
  3509  		return 0x46a2 << 10
  3510  	case AMOVFV:
  3511  		return 0x46c9 << 10
  3512  	case AMOVDV:
  3513  		return 0x46ca << 10
  3514  	case AMOVVF:
  3515  		return 0x4746 << 10
  3516  	case AMOVVD:
  3517  		return 0x474a << 10
  3518  	case AMOVFW:
  3519  		return 0x46c1 << 10
  3520  	case AMOVDW:
  3521  		return 0x46c2 << 10
  3522  	case AMOVWF:
  3523  		return 0x4744 << 10
  3524  	case AMOVDF:
  3525  		return 0x4646 << 10
  3526  	case AMOVWD:
  3527  		return 0x4748 << 10
  3528  	case AMOVFD:
  3529  		return 0x4649 << 10
  3530  	case AABSF:
  3531  		return 0x4501 << 10
  3532  	case AABSD:
  3533  		return 0x4502 << 10
  3534  	case AMOVF:
  3535  		return 0x4525 << 10
  3536  	case AMOVD:
  3537  		return 0x4526 << 10
  3538  	case ANEGF:
  3539  		return 0x4505 << 10
  3540  	case ANEGD:
  3541  		return 0x4506 << 10
  3542  	case ASQRTF:
  3543  		return 0x4511 << 10
  3544  	case ASQRTD:
  3545  		return 0x4512 << 10
  3546  	case AFLOGBF:
  3547  		return 0x4509 << 10 // flogb.s
  3548  	case AFLOGBD:
  3549  		return 0x450a << 10 // flogb.d
  3550  	case AFCLASSF:
  3551  		return 0x450d << 10 // fclass.s
  3552  	case AFCLASSD:
  3553  		return 0x450e << 10 // fclass.d
  3554  	case AFFINTFW:
  3555  		return 0x4744 << 10 // ffint.s.w
  3556  	case AFFINTFV:
  3557  		return 0x4746 << 10 // ffint.s.l
  3558  	case AFFINTDW:
  3559  		return 0x4748 << 10 // ffint.d.w
  3560  	case AFFINTDV:
  3561  		return 0x474a << 10 // ffint.d.l
  3562  	case AFTINTWF:
  3563  		return 0x46c1 << 10 // ftint.w.s
  3564  	case AFTINTWD:
  3565  		return 0x46c2 << 10 // ftint.w.d
  3566  	case AFTINTVF:
  3567  		return 0x46c9 << 10 // ftint.l.s
  3568  	case AFTINTVD:
  3569  		return 0x46ca << 10 // ftint.l.d
  3570  	case AFTINTRMWF:
  3571  		return 0x4681 << 10 // ftintrm.w.s
  3572  	case AFTINTRMWD:
  3573  		return 0x4682 << 10 // ftintrm.w.d
  3574  	case AFTINTRMVF:
  3575  		return 0x4689 << 10 // ftintrm.l.s
  3576  	case AFTINTRMVD:
  3577  		return 0x468a << 10 // ftintrm.l.d
  3578  	case AFTINTRPWF:
  3579  		return 0x4691 << 10 // ftintrp.w.s
  3580  	case AFTINTRPWD:
  3581  		return 0x4692 << 10 // ftintrp.w.d
  3582  	case AFTINTRPVF:
  3583  		return 0x4699 << 10 // ftintrp.l.s
  3584  	case AFTINTRPVD:
  3585  		return 0x469a << 10 // ftintrp.l.d
  3586  	case AFTINTRZWF:
  3587  		return 0x46a1 << 10 // ftintrz.w.s
  3588  	case AFTINTRZWD:
  3589  		return 0x46a2 << 10 // ftintrz.w.d
  3590  	case AFTINTRZVF:
  3591  		return 0x46a9 << 10 // ftintrz.l.s
  3592  	case AFTINTRZVD:
  3593  		return 0x46aa << 10 // ftintrz.l.d
  3594  	case AFTINTRNEWF:
  3595  		return 0x46b1 << 10 // ftintrne.w.s
  3596  	case AFTINTRNEWD:
  3597  		return 0x46b2 << 10 // ftintrne.w.d
  3598  	case AFTINTRNEVF:
  3599  		return 0x46b9 << 10 // ftintrne.l.s
  3600  	case AFTINTRNEVD:
  3601  		return 0x46ba << 10 // ftintrne.l.d
  3602  	case AVPCNTB:
  3603  		return 0x1ca708 << 10 // vpcnt.b
  3604  	case AVPCNTH:
  3605  		return 0x1ca709 << 10 // vpcnt.h
  3606  	case AVPCNTW:
  3607  		return 0x1ca70a << 10 // vpcnt.w
  3608  	case AVPCNTV:
  3609  		return 0x1ca70b << 10 // vpcnt.v
  3610  	case AXVPCNTB:
  3611  		return 0x1da708 << 10 // xvpcnt.b
  3612  	case AXVPCNTH:
  3613  		return 0x1da709 << 10 // xvpcnt.h
  3614  	case AXVPCNTW:
  3615  		return 0x1da70a << 10 // xvpcnt.w
  3616  	case AXVPCNTV:
  3617  		return 0x1da70b << 10 // xvpcnt.v
  3618  	case AVFSQRTF:
  3619  		return 0x1ca739 << 10 // vfsqrt.s
  3620  	case AVFSQRTD:
  3621  		return 0x1ca73a << 10 // vfsqrt.d
  3622  	case AVFRECIPF:
  3623  		return 0x1ca73d << 10 // vfrecip.s
  3624  	case AVFRECIPD:
  3625  		return 0x1ca73e << 10 // vfrecip.d
  3626  	case AVFRSQRTF:
  3627  		return 0x1ca741 << 10 // vfrsqrt.s
  3628  	case AVFRSQRTD:
  3629  		return 0x1ca742 << 10 // vfrsqrt.d
  3630  	case AXVFSQRTF:
  3631  		return 0x1da739 << 10 // xvfsqrt.s
  3632  	case AXVFSQRTD:
  3633  		return 0x1da73a << 10 // xvfsqrt.d
  3634  	case AXVFRECIPF:
  3635  		return 0x1da73d << 10 // xvfrecip.s
  3636  	case AXVFRECIPD:
  3637  		return 0x1da73e << 10 // xvfrecip.d
  3638  	case AXVFRSQRTF:
  3639  		return 0x1da741 << 10 // xvfrsqrt.s
  3640  	case AXVFRSQRTD:
  3641  		return 0x1da742 << 10 // xvfrsqrt.d
  3642  	case AVNEGB:
  3643  		return 0x1ca70c << 10 // vneg.b
  3644  	case AVNEGH:
  3645  		return 0x1ca70d << 10 // vneg.h
  3646  	case AVNEGW:
  3647  		return 0x1ca70e << 10 // vneg.w
  3648  	case AVNEGV:
  3649  		return 0x1ca70f << 10 // vneg.d
  3650  	case AXVNEGB:
  3651  		return 0x1da70c << 10 // xvneg.b
  3652  	case AXVNEGH:
  3653  		return 0x1da70d << 10 // xvneg.h
  3654  	case AXVNEGW:
  3655  		return 0x1da70e << 10 // xvneg.w
  3656  	case AXVNEGV:
  3657  		return 0x1da70f << 10 // xvneg.d
  3658  	case AVFRINTRNEF:
  3659  		return 0x1ca75d << 10 // vfrintrne.s
  3660  	case AVFRINTRNED:
  3661  		return 0x1ca75e << 10 // vfrintrne.d
  3662  	case AVFRINTRZF:
  3663  		return 0x1ca759 << 10 // vfrintrz.s
  3664  	case AVFRINTRZD:
  3665  		return 0x1ca75a << 10 // vfrintrz.d
  3666  	case AVFRINTRPF:
  3667  		return 0x1ca755 << 10 // vfrintrp.s
  3668  	case AVFRINTRPD:
  3669  		return 0x1ca756 << 10 // vfrintrp.d
  3670  	case AVFRINTRMF:
  3671  		return 0x1ca751 << 10 // vfrintrm.s
  3672  	case AVFRINTRMD:
  3673  		return 0x1ca752 << 10 // vfrintrm.d
  3674  	case AVFRINTF:
  3675  		return 0x1ca74d << 10 // vfrint.s
  3676  	case AVFRINTD:
  3677  		return 0x1ca74e << 10 // vfrint.d
  3678  	case AXVFRINTRNEF:
  3679  		return 0x1da75d << 10 // xvfrintrne.s
  3680  	case AXVFRINTRNED:
  3681  		return 0x1da75e << 10 // xvfrintrne.d
  3682  	case AXVFRINTRZF:
  3683  		return 0x1da759 << 10 // xvfrintrz.s
  3684  	case AXVFRINTRZD:
  3685  		return 0x1da75a << 10 // xvfrintrz.d
  3686  	case AXVFRINTRPF:
  3687  		return 0x1da755 << 10 // xvfrintrp.s
  3688  	case AXVFRINTRPD:
  3689  		return 0x1da756 << 10 // xvfrintrp.d
  3690  	case AXVFRINTRMF:
  3691  		return 0x1da751 << 10 // xvfrintrm.s
  3692  	case AXVFRINTRMD:
  3693  		return 0x1da752 << 10 // xvfrintrm.d
  3694  	case AXVFRINTF:
  3695  		return 0x1da74d << 10 // xvfrint.s
  3696  	case AXVFRINTD:
  3697  		return 0x1da74e << 10 // xvfrint.d
  3698  	case AVFCLASSF:
  3699  		return 0x1ca735 << 10 // vfclass.s
  3700  	case AVFCLASSD:
  3701  		return 0x1ca736 << 10 // vfclass.d
  3702  	case AXVFCLASSF:
  3703  		return 0x1da735 << 10 // xvfclass.s
  3704  	case AXVFCLASSD:
  3705  		return 0x1da736 << 10 // xvfclass.d
  3706  	case AVSETEQV:
  3707  		return 0x1ca726<<10 | 0x0<<3 // vseteqz.v
  3708  	case AVSETNEV:
  3709  		return 0x1ca727<<10 | 0x0<<3 // vsetnez.v
  3710  	case AVSETANYEQB:
  3711  		return 0x1ca728<<10 | 0x0<<3 // vsetanyeqz.b
  3712  	case AVSETANYEQH:
  3713  		return 0x1ca729<<10 | 0x0<<3 // vsetanyeqz.h
  3714  	case AVSETANYEQW:
  3715  		return 0x1ca72a<<10 | 0x0<<3 // vsetanyeqz.w
  3716  	case AVSETANYEQV:
  3717  		return 0x1ca72b<<10 | 0x0<<3 // vsetanyeqz.d
  3718  	case AVSETALLNEB:
  3719  		return 0x1ca72c<<10 | 0x0<<3 // vsetallnez.b
  3720  	case AVSETALLNEH:
  3721  		return 0x1ca72d<<10 | 0x0<<3 // vsetallnez.h
  3722  	case AVSETALLNEW:
  3723  		return 0x1ca72e<<10 | 0x0<<3 // vsetallnez.w
  3724  	case AVSETALLNEV:
  3725  		return 0x1ca72f<<10 | 0x0<<3 // vsetallnez.d
  3726  	case AXVSETEQV:
  3727  		return 0x1da726<<10 | 0x0<<3 // xvseteqz.v
  3728  	case AXVSETNEV:
  3729  		return 0x1da727<<10 | 0x0<<3 // xvsetnez.v
  3730  	case AXVSETANYEQB:
  3731  		return 0x1da728<<10 | 0x0<<3 // xvsetanyeqz.b
  3732  	case AXVSETANYEQH:
  3733  		return 0x1da729<<10 | 0x0<<3 // xvsetanyeqz.h
  3734  	case AXVSETANYEQW:
  3735  		return 0x1da72a<<10 | 0x0<<3 // xvsetanyeqz.w
  3736  	case AXVSETANYEQV:
  3737  		return 0x1da72b<<10 | 0x0<<3 // xvsetanyeqz.d
  3738  	case AXVSETALLNEB:
  3739  		return 0x1da72c<<10 | 0x0<<3 // xvsetallnez.b
  3740  	case AXVSETALLNEH:
  3741  		return 0x1da72d<<10 | 0x0<<3 // xvsetallnez.h
  3742  	case AXVSETALLNEW:
  3743  		return 0x1da72e<<10 | 0x0<<3 // xvsetallnez.w
  3744  	case AXVSETALLNEV:
  3745  		return 0x1da72f<<10 | 0x0<<3 // xvsetallnez.d
  3746  	}
  3747  
  3748  	c.ctxt.Diag("bad rr opcode %v", a)
  3749  	return 0
  3750  }
  3751  
  3752  func (c *ctxt0) opi(a obj.As) uint32 {
  3753  	switch a {
  3754  	case ASYSCALL:
  3755  		return 0x56 << 15
  3756  	case ABREAK:
  3757  		return 0x54 << 15
  3758  	case ADBAR:
  3759  		return 0x70e4 << 15
  3760  	}
  3761  
  3762  	c.ctxt.Diag("bad ic opcode %v", a)
  3763  
  3764  	return 0
  3765  }
  3766  
  3767  func (c *ctxt0) opir(a obj.As) uint32 {
  3768  	switch a {
  3769  	case ALU12IW:
  3770  		return 0x0a << 25
  3771  	case ALU32ID:
  3772  		return 0x0b << 25
  3773  	case APCALAU12I:
  3774  		return 0x0d << 25
  3775  	case APCADDU12I:
  3776  		return 0x0e << 25
  3777  	}
  3778  	return 0
  3779  }
  3780  
  3781  func (c *ctxt0) opirr(a obj.As) uint32 {
  3782  	switch a {
  3783  	case AADD, AADDU:
  3784  		return 0x00a << 22
  3785  	case ASGT:
  3786  		return 0x008 << 22
  3787  	case ASGTU:
  3788  		return 0x009 << 22
  3789  	case AAND:
  3790  		return 0x00d << 22
  3791  	case AOR:
  3792  		return 0x00e << 22
  3793  	case ALU52ID:
  3794  		return 0x00c << 22
  3795  	case AXOR:
  3796  		return 0x00f << 22
  3797  	case ASLL:
  3798  		return 0x00081 << 15
  3799  	case ASRL:
  3800  		return 0x00089 << 15
  3801  	case ASRA:
  3802  		return 0x00091 << 15
  3803  	case AROTR:
  3804  		return 0x00099 << 15
  3805  	case AADDV:
  3806  		return 0x00b << 22
  3807  	case AADDVU:
  3808  		return 0x00b << 22
  3809  
  3810  	case AJMP:
  3811  		return 0x14 << 26
  3812  	case AJAL,
  3813  		obj.ADUFFZERO,
  3814  		obj.ADUFFCOPY:
  3815  		return 0x15 << 26
  3816  
  3817  	case AJIRL:
  3818  		return 0x13 << 26
  3819  	case ABLTU:
  3820  		return 0x1a << 26
  3821  	case ABLT, ABLTZ, ABGTZ:
  3822  		return 0x18 << 26
  3823  	case ABGEU:
  3824  		return 0x1b << 26
  3825  	case ABGE, ABGEZ, ABLEZ:
  3826  		return 0x19 << 26
  3827  	case -ABEQ: // beqz
  3828  		return 0x10 << 26
  3829  	case -ABNE: // bnez
  3830  		return 0x11 << 26
  3831  	case ABEQ:
  3832  		return 0x16 << 26
  3833  	case ABNE:
  3834  		return 0x17 << 26
  3835  	case ABFPT:
  3836  		return 0x12<<26 | 0x1<<8
  3837  	case ABFPF:
  3838  		return 0x12<<26 | 0x0<<8
  3839  
  3840  	case AMOVB,
  3841  		AMOVBU:
  3842  		return 0x0a4 << 22
  3843  	case AMOVH,
  3844  		AMOVHU:
  3845  		return 0x0a5 << 22
  3846  	case AMOVW,
  3847  		AMOVWU:
  3848  		return 0x0a6 << 22
  3849  	case AMOVV:
  3850  		return 0x0a7 << 22
  3851  	case AMOVF:
  3852  		return 0x0ad << 22
  3853  	case AMOVD:
  3854  		return 0x0af << 22
  3855  	case -AMOVB:
  3856  		return 0x0a0 << 22
  3857  	case -AMOVBU:
  3858  		return 0x0a8 << 22
  3859  	case -AMOVH:
  3860  		return 0x0a1 << 22
  3861  	case -AMOVHU:
  3862  		return 0x0a9 << 22
  3863  	case -AMOVW:
  3864  		return 0x0a2 << 22
  3865  	case -AMOVWU:
  3866  		return 0x0aa << 22
  3867  	case -AMOVV:
  3868  		return 0x0a3 << 22
  3869  	case -AMOVF:
  3870  		return 0x0ac << 22
  3871  	case -AMOVD:
  3872  		return 0x0ae << 22
  3873  	case -AVMOVQ:
  3874  		return 0x0b0 << 22 // vld
  3875  	case -AXVMOVQ:
  3876  		return 0x0b2 << 22 // xvld
  3877  	case AVMOVQ:
  3878  		return 0x0b1 << 22 // vst
  3879  	case AXVMOVQ:
  3880  		return 0x0b3 << 22 // xvst
  3881  	case ASLLV:
  3882  		return 0x0041 << 16
  3883  	case ASRLV:
  3884  		return 0x0045 << 16
  3885  	case ASRAV:
  3886  		return 0x0049 << 16
  3887  	case AROTRV:
  3888  		return 0x004d << 16
  3889  	case -ALL:
  3890  		return 0x020 << 24
  3891  	case -ALLV:
  3892  		return 0x022 << 24
  3893  	case ASC:
  3894  		return 0x021 << 24
  3895  	case ASCV:
  3896  		return 0x023 << 24
  3897  	case AVANDB:
  3898  		return 0x1CF4 << 18 // vandi.b
  3899  	case AVORB:
  3900  		return 0x1CF5 << 18 // vori.b
  3901  	case AVXORB:
  3902  		return 0x1CF6 << 18 // xori.b
  3903  	case AVNORB:
  3904  		return 0x1CF7 << 18 // xnori.b
  3905  	case AXVANDB:
  3906  		return 0x1DF4 << 18 // xvandi.b
  3907  	case AXVORB:
  3908  		return 0x1DF5 << 18 // xvori.b
  3909  	case AXVXORB:
  3910  		return 0x1DF6 << 18 // xvxori.b
  3911  	case AXVNORB:
  3912  		return 0x1DF7 << 18 // xvnor.b
  3913  	case AVSEQB:
  3914  		return 0x0E500 << 15 //vseqi.b
  3915  	case AVSEQH:
  3916  		return 0x0E501 << 15 // vseqi.h
  3917  	case AVSEQW:
  3918  		return 0x0E502 << 15 //vseqi.w
  3919  	case AVSEQV:
  3920  		return 0x0E503 << 15 //vseqi.d
  3921  	case AXVSEQB:
  3922  		return 0x0ED00 << 15 //xvseqi.b
  3923  	case AXVSEQH:
  3924  		return 0x0ED01 << 15 // xvseqi.h
  3925  	case AXVSEQW:
  3926  		return 0x0ED02 << 15 // xvseqi.w
  3927  	case AXVSEQV:
  3928  		return 0x0ED03 << 15 // xvseqi.d
  3929  	case AVROTRB:
  3930  		return 0x1ca8<<18 | 0x1<<13 // vrotri.b
  3931  	case AVROTRH:
  3932  		return 0x1ca8<<18 | 0x1<<14 // vrotri.h
  3933  	case AVROTRW:
  3934  		return 0x1ca8<<18 | 0x1<<15 // vrotri.w
  3935  	case AVROTRV:
  3936  		return 0x1ca8<<18 | 0x1<<16 // vrotri.d
  3937  	case AXVROTRB:
  3938  		return 0x1da8<<18 | 0x1<<13 // xvrotri.b
  3939  	case AXVROTRH:
  3940  		return 0x1da8<<18 | 0x1<<14 // xvrotri.h
  3941  	case AXVROTRW:
  3942  		return 0x1da8<<18 | 0x1<<15 // xvrotri.w
  3943  	case AXVROTRV:
  3944  		return 0x1da8<<18 | 0x1<<16 // xvrotri.d
  3945  	case AVSLLB:
  3946  		return 0x1ccb<<18 | 0x1<<13 // vslli.b
  3947  	case AVSLLH:
  3948  		return 0x1ccb<<18 | 0x1<<14 // vslli.h
  3949  	case AVSLLW:
  3950  		return 0x1ccb<<18 | 0x1<<15 // vslli.w
  3951  	case AVSLLV:
  3952  		return 0x1ccb<<18 | 0x1<<16 // vslli.d
  3953  	case AVSRLB:
  3954  		return 0x1ccc<<18 | 0x1<<13 // vsrli.b
  3955  	case AVSRLH:
  3956  		return 0x1ccc<<18 | 0x1<<14 // vsrli.h
  3957  	case AVSRLW:
  3958  		return 0x1ccc<<18 | 0x1<<15 // vsrli.w
  3959  	case AVSRLV:
  3960  		return 0x1ccc<<18 | 0x1<<16 // vsrli.d
  3961  	case AVSRAB:
  3962  		return 0x1ccd<<18 | 0x1<<13 // vsrai.b
  3963  	case AVSRAH:
  3964  		return 0x1ccd<<18 | 0x1<<14 // vsrai.h
  3965  	case AVSRAW:
  3966  		return 0x1ccd<<18 | 0x1<<15 // vsrai.w
  3967  	case AVSRAV:
  3968  		return 0x1ccd<<18 | 0x1<<16 // vsrai.d
  3969  	case AXVSLLB:
  3970  		return 0x1dcb<<18 | 0x1<<13 // xvslli.b
  3971  	case AXVSLLH:
  3972  		return 0x1dcb<<18 | 0x1<<14 // xvslli.h
  3973  	case AXVSLLW:
  3974  		return 0x1dcb<<18 | 0x1<<15 // xvslli.w
  3975  	case AXVSLLV:
  3976  		return 0x1dcb<<18 | 0x1<<16 // xvslli.d
  3977  	case AXVSRLB:
  3978  		return 0x1dcc<<18 | 0x1<<13 // xvsrli.b
  3979  	case AXVSRLH:
  3980  		return 0x1dcc<<18 | 0x1<<14 // xvsrli.h
  3981  	case AXVSRLW:
  3982  		return 0x1dcc<<18 | 0x1<<15 // xvsrli.w
  3983  	case AXVSRLV:
  3984  		return 0x1dcc<<18 | 0x1<<16 // xvsrli.d
  3985  	case AXVSRAB:
  3986  		return 0x1dcd<<18 | 0x1<<13 // xvsrai.b
  3987  	case AXVSRAH:
  3988  		return 0x1dcd<<18 | 0x1<<14 // xvsrai.h
  3989  	case AXVSRAW:
  3990  		return 0x1dcd<<18 | 0x1<<15 // xvsrai.w
  3991  	case AXVSRAV:
  3992  		return 0x1dcd<<18 | 0x1<<16 // xvsrai.d
  3993  	case AVADDBU:
  3994  		return 0xe514 << 15 // vaddi.bu
  3995  	case AVADDHU:
  3996  		return 0xe515 << 15 // vaddi.hu
  3997  	case AVADDWU:
  3998  		return 0xe516 << 15 // vaddi.wu
  3999  	case AVADDVU:
  4000  		return 0xe517 << 15 // vaddi.du
  4001  	case AVSUBBU:
  4002  		return 0xe518 << 15 // vsubi.bu
  4003  	case AVSUBHU:
  4004  		return 0xe519 << 15 // vsubi.hu
  4005  	case AVSUBWU:
  4006  		return 0xe51a << 15 // vsubi.wu
  4007  	case AVSUBVU:
  4008  		return 0xe51b << 15 // vsubi.du
  4009  	case AXVADDBU:
  4010  		return 0xed14 << 15 // xvaddi.bu
  4011  	case AXVADDHU:
  4012  		return 0xed15 << 15 // xvaddi.hu
  4013  	case AXVADDWU:
  4014  		return 0xed16 << 15 // xvaddi.wu
  4015  	case AXVADDVU:
  4016  		return 0xed17 << 15 // xvaddi.du
  4017  	case AXVSUBBU:
  4018  		return 0xed18 << 15 // xvsubi.bu
  4019  	case AXVSUBHU:
  4020  		return 0xed19 << 15 // xvsubi.hu
  4021  	case AXVSUBWU:
  4022  		return 0xed1a << 15 // xvsubi.wu
  4023  	case AXVSUBVU:
  4024  		return 0xed1b << 15 // xvsubi.du
  4025  	case AVSHUF4IB:
  4026  		return 0x1ce4 << 18 // vshuf4i.b
  4027  	case AVSHUF4IH:
  4028  		return 0x1ce5 << 18 // vshuf4i.h
  4029  	case AVSHUF4IW:
  4030  		return 0x1ce6 << 18 // vshuf4i.w
  4031  	case AVSHUF4IV:
  4032  		return 0x1ce7 << 18 // vshuf4i.d
  4033  	case AXVSHUF4IB:
  4034  		return 0x1de4 << 18 // xvshuf4i.b
  4035  	case AXVSHUF4IH:
  4036  		return 0x1de5 << 18 // xvshuf4i.h
  4037  	case AXVSHUF4IW:
  4038  		return 0x1de6 << 18 // xvshuf4i.w
  4039  	case AXVSHUF4IV:
  4040  		return 0x1de7 << 18 // xvshuf4i.d
  4041  	}
  4042  
  4043  	if a < 0 {
  4044  		c.ctxt.Diag("bad irr opcode -%v", -a)
  4045  	} else {
  4046  		c.ctxt.Diag("bad irr opcode %v", a)
  4047  	}
  4048  	return 0
  4049  }
  4050  
  4051  func (c *ctxt0) opirir(a obj.As) uint32 {
  4052  	switch a {
  4053  	case ABSTRINSW:
  4054  		return 0x3<<21 | 0x0<<15 // bstrins.w
  4055  	case ABSTRINSV:
  4056  		return 0x2 << 22 // bstrins.d
  4057  	case ABSTRPICKW:
  4058  		return 0x3<<21 | 0x1<<15 // bstrpick.w
  4059  	case ABSTRPICKV:
  4060  		return 0x3 << 22 // bstrpick.d
  4061  	}
  4062  
  4063  	return 0
  4064  }
  4065  
  4066  func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
  4067  	switch a {
  4068  	case AMOVV:
  4069  		switch fclass {
  4070  		case C_REG:
  4071  			switch tclass {
  4072  			case C_FREG:
  4073  				return 0x452a << 10 // movgr2fr.d
  4074  			case C_FCCREG:
  4075  				return 0x4536 << 10 // movgr2cf
  4076  			case C_FCSRREG:
  4077  				return 0x4530 << 10 // movgr2fcsr
  4078  			}
  4079  		case C_FREG:
  4080  			switch tclass {
  4081  			case C_REG:
  4082  				return 0x452e << 10 // movfr2gr.d
  4083  			case C_FCCREG:
  4084  				return 0x4534 << 10 // movfr2cf
  4085  			}
  4086  		case C_FCCREG:
  4087  			switch tclass {
  4088  			case C_REG:
  4089  				return 0x4537 << 10 // movcf2gr
  4090  			case C_FREG:
  4091  				return 0x4535 << 10 // movcf2fr
  4092  			}
  4093  		case C_FCSRREG:
  4094  			switch tclass {
  4095  			case C_REG:
  4096  				return 0x4532 << 10 // movfcsr2gr
  4097  			}
  4098  		}
  4099  
  4100  	case AMOVW:
  4101  		switch fclass {
  4102  		case C_REG:
  4103  			switch tclass {
  4104  			case C_FREG:
  4105  				return 0x4529 << 10 // movgr2fr.w
  4106  			}
  4107  		case C_FREG:
  4108  			switch tclass {
  4109  			case C_REG:
  4110  				return 0x452d << 10 // movfr2gr.s
  4111  			}
  4112  		}
  4113  	}
  4114  
  4115  	c.ctxt.Diag("bad class combination: %s %s,%s\n", a, fclass, tclass)
  4116  
  4117  	return 0
  4118  }
  4119  
  4120  func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16) (op_code, index_mask uint32) {
  4121  	farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
  4122  	tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
  4123  	fclass := c.rclass(fReg)
  4124  	tclass := c.rclass(tReg)
  4125  
  4126  	switch fclass | (tclass << 16) {
  4127  	case C_REG | (C_ELEM << 16):
  4128  		// vmov Rn, Vd.<T>[index]
  4129  		switch a {
  4130  		case AVMOVQ:
  4131  			switch tarng {
  4132  			case ARNG_B:
  4133  				return (0x01CBAE << 14), 0xf // vinsgr2vr.b
  4134  			case ARNG_H:
  4135  				return (0x03975E << 13), 0x7 // vinsgr2vr.h
  4136  			case ARNG_W:
  4137  				return (0x072EBE << 12), 0x3 // vinsgr2vr.w
  4138  			case ARNG_V:
  4139  				return (0x0E5D7E << 11), 0x1 // vinsgr2vr.d
  4140  			}
  4141  		case AXVMOVQ:
  4142  			switch tarng {
  4143  			case ARNG_W:
  4144  				return (0x03B75E << 13), 0x7 // xvinsgr2vr.w
  4145  			case ARNG_V:
  4146  				return (0x076EBE << 12), 0x3 // xvinsgr2vr.d
  4147  			}
  4148  		}
  4149  
  4150  	case C_ELEM | (C_REG << 16):
  4151  		// vmov Vd.<T>[index], Rn
  4152  		switch a {
  4153  		case AVMOVQ:
  4154  			switch farng {
  4155  			case ARNG_B:
  4156  				return (0x01CBBE << 14), 0xf // vpickve2gr.b
  4157  			case ARNG_H:
  4158  				return (0x03977E << 13), 0x7 // vpickve2gr.h
  4159  			case ARNG_W:
  4160  				return (0x072EFE << 12), 0x3 // vpickve2gr.w
  4161  			case ARNG_V:
  4162  				return (0x0E5DFE << 11), 0x1 // vpickve2gr.d
  4163  			case ARNG_BU:
  4164  				return (0x01CBCE << 14), 0xf // vpickve2gr.bu
  4165  			case ARNG_HU:
  4166  				return (0x03979E << 13), 0x7 // vpickve2gr.hu
  4167  			case ARNG_WU:
  4168  				return (0x072F3E << 12), 0x3 // vpickve2gr.wu
  4169  			case ARNG_VU:
  4170  				return (0x0E5E7E << 11), 0x1 // vpickve2gr.du
  4171  			}
  4172  		case AXVMOVQ:
  4173  			switch farng {
  4174  			case ARNG_W:
  4175  				return (0x03B77E << 13), 0x7 // xvpickve2gr.w
  4176  			case ARNG_V:
  4177  				return (0x076EFE << 12), 0x3 // xvpickve2gr.d
  4178  			case ARNG_WU:
  4179  				return (0x03B79E << 13), 0x7 // xvpickve2gr.wu
  4180  			case ARNG_VU:
  4181  				return (0x076F3E << 12), 0x3 // xvpickve2gr.du
  4182  			}
  4183  		}
  4184  
  4185  	case C_REG | (C_ARNG << 16):
  4186  		// vmov Rn, Vd.<T>
  4187  		switch a {
  4188  		case AVMOVQ:
  4189  			switch tarng {
  4190  			case ARNG_16B:
  4191  				return (0x1CA7C0 << 10), 0x0 // vreplgr2vr.b
  4192  			case ARNG_8H:
  4193  				return (0x1CA7C1 << 10), 0x0 // vreplgr2vr.h
  4194  			case ARNG_4W:
  4195  				return (0x1CA7C2 << 10), 0x0 // vreplgr2vr.w
  4196  			case ARNG_2V:
  4197  				return (0x1CA7C3 << 10), 0x0 // vreplgr2vr.d
  4198  			}
  4199  		case AXVMOVQ:
  4200  			switch tarng {
  4201  			case ARNG_32B:
  4202  				return (0x1DA7C0 << 10), 0x0 // xvreplgr2vr.b
  4203  			case ARNG_16H:
  4204  				return (0x1DA7C1 << 10), 0x0 // xvreplgr2vr.h
  4205  			case ARNG_8W:
  4206  				return (0x1DA7C2 << 10), 0x0 // xvreplgr2vr.w
  4207  			case ARNG_4V:
  4208  				return (0x1DA7C3 << 10), 0x0 // xvreplgr2vr.d
  4209  			}
  4210  		}
  4211  
  4212  	case C_XREG | (C_ARNG << 16):
  4213  		// vmov  xj, xd.<T>
  4214  		switch a {
  4215  		case AVMOVQ:
  4216  			return 0, 0 // unsupported op
  4217  		case AXVMOVQ:
  4218  			switch tarng {
  4219  			case ARNG_32B:
  4220  				return (0x1DC1C0 << 10), 0x0 // xvreplve0.b
  4221  			case ARNG_16H:
  4222  				return (0x1DC1E0 << 10), 0x0 // xvreplve0.h
  4223  			case ARNG_8W:
  4224  				return (0x1DC1F0 << 10), 0x0 // xvreplve0.w
  4225  			case ARNG_4V:
  4226  				return (0x1DC1F8 << 10), 0x0 // xvreplve0.d
  4227  			case ARNG_2Q:
  4228  				return (0x1DC1FC << 10), 0x0 // xvreplve0.q
  4229  			}
  4230  		}
  4231  
  4232  	case C_XREG | (C_ELEM << 16):
  4233  		// vmov  xj, xd.<T>[index]
  4234  		switch a {
  4235  		case AVMOVQ:
  4236  			return 0, 0 // unsupported op
  4237  		case AXVMOVQ:
  4238  			switch tarng {
  4239  			case ARNG_W:
  4240  				return (0x03B7FE << 13), 0x7 // xvinsve0.w
  4241  			case ARNG_V:
  4242  				return (0x076FFE << 12), 0x3 // xvinsve0.d
  4243  			}
  4244  		}
  4245  
  4246  	case C_ELEM | (C_XREG << 16):
  4247  		// vmov  xj.<T>[index], xd
  4248  		switch a {
  4249  		case AVMOVQ:
  4250  			return 0, 0 // unsupported op
  4251  		case AXVMOVQ:
  4252  			switch farng {
  4253  			case ARNG_W:
  4254  				return (0x03B81E << 13), 0x7 // xvpickve.w
  4255  			case ARNG_V:
  4256  				return (0x07703E << 12), 0x3 // xvpickve.d
  4257  			}
  4258  		}
  4259  
  4260  	case C_ELEM | (C_ARNG << 16):
  4261  		// vmov  vj.<T>[index], vd.<T>
  4262  		switch a {
  4263  		case AVMOVQ:
  4264  			switch int32(farng) | (int32(tarng) << 16) {
  4265  			case int32(ARNG_B) | (int32(ARNG_16B) << 16):
  4266  				return (0x01CBDE << 14), 0xf // vreplvei.b
  4267  			case int32(ARNG_H) | (int32(ARNG_8H) << 16):
  4268  				return (0x0397BE << 13), 0x7 // vreplvei.h
  4269  			case int32(ARNG_W) | (int32(ARNG_4W) << 16):
  4270  				return (0x072F7E << 12), 0x3 // vreplvei.w
  4271  			case int32(ARNG_V) | (int32(ARNG_2V) << 16):
  4272  				return (0x0E5EFE << 11), 0x1 // vreplvei.d
  4273  			}
  4274  		case AXVMOVQ:
  4275  			return 0, 0 // unsupported op
  4276  		}
  4277  	}
  4278  
  4279  	return 0, 0
  4280  }
  4281  
  4282  func vshift(a obj.As) bool {
  4283  	switch a {
  4284  	case ASLLV,
  4285  		ASRLV,
  4286  		ASRAV,
  4287  		AROTRV:
  4288  		return true
  4289  	}
  4290  	return false
  4291  }
  4292  

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