Source file src/cmd/internal/obj/arm64/inst_gen.go

     1  // Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. DO NOT EDIT.
     2  
     3  // The following constants are generated from the XML specification.
     4  
     5  package arm64
     6  
     7  // insts are grouped by [goOp].
     8  var insts = [][]instEncoder{
     9  	// ADDPL
    10  	{
    11  		// ADDPL #<imm>, <Xn|SP>, <Xd|SP>
    12  		{
    13  			goOp:      AADDPL,
    14  			fixedBits: 0x4605000,
    15  			args:      cimm__XnSP__XdSP,
    16  		},
    17  	},
    18  	// ADDVL
    19  	{
    20  		// ADDVL #<imm>, <Xn|SP>, <Xd|SP>
    21  		{
    22  			goOp:      AADDVL,
    23  			fixedBits: 0x4205000,
    24  			args:      cimm__XnSP__XdSP,
    25  		},
    26  	},
    27  	// CTERMEQ
    28  	{
    29  		// CTERMEQ <R><m>, <R><n>
    30  		{
    31  			goOp:      ACTERMEQ,
    32  			fixedBits: 0x25e02000,
    33  			args:      Rm__Rn,
    34  		},
    35  	},
    36  	// CTERMEQW
    37  	{
    38  		// CTERMEQW <R><m>, <R><n>
    39  		{
    40  			goOp:      ACTERMEQW,
    41  			fixedBits: 0x25a02000,
    42  			args:      Rm__Rn,
    43  		},
    44  	},
    45  	// CTERMNE
    46  	{
    47  		// CTERMNE <R><m>, <R><n>
    48  		{
    49  			goOp:      ACTERMNE,
    50  			fixedBits: 0x25e02010,
    51  			args:      Rm__Rn,
    52  		},
    53  	},
    54  	// CTERMNEW
    55  	{
    56  		// CTERMNEW <R><m>, <R><n>
    57  		{
    58  			goOp:      ACTERMNEW,
    59  			fixedBits: 0x25a02010,
    60  			args:      Rm__Rn,
    61  		},
    62  	},
    63  	// PAND
    64  	{
    65  		// PAND <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
    66  		{
    67  			goOp:      APAND,
    68  			fixedBits: 0x25004000,
    69  			args:      Pm_B__Pn_B__PgZ__Pd_B,
    70  		},
    71  	},
    72  	// PANDS
    73  	{
    74  		// PANDS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
    75  		{
    76  			goOp:      APANDS,
    77  			fixedBits: 0x25404000,
    78  			args:      Pm_B__Pn_B__PgZ__Pd_B,
    79  		},
    80  	},
    81  	// PBIC
    82  	{
    83  		// PBIC <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
    84  		{
    85  			goOp:      APBIC,
    86  			fixedBits: 0x25004010,
    87  			args:      Pm_B__Pn_B__PgZ__Pd_B,
    88  		},
    89  	},
    90  	// PBICS
    91  	{
    92  		// PBICS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
    93  		{
    94  			goOp:      APBICS,
    95  			fixedBits: 0x25404010,
    96  			args:      Pm_B__Pn_B__PgZ__Pd_B,
    97  		},
    98  	},
    99  	// PBRKA
   100  	{
   101  		// PBRKA <Pn>.B, <Pg>/<ZM>, <Pd>.B
   102  		{
   103  			goOp:      APBRKA,
   104  			fixedBits: 0x25104000,
   105  			args:      Pn_B__PgZM__Pd_B,
   106  		},
   107  	},
   108  	// PBRKAS
   109  	{
   110  		// PBRKAS <Pn>.B, <Pg>/Z, <Pd>.B
   111  		{
   112  			goOp:      APBRKAS,
   113  			fixedBits: 0x25504000,
   114  			args:      Pn_B__PgZ__Pd_B,
   115  		},
   116  	},
   117  	// PBRKB
   118  	{
   119  		// PBRKB <Pn>.B, <Pg>/<ZM>, <Pd>.B
   120  		{
   121  			goOp:      APBRKB,
   122  			fixedBits: 0x25904000,
   123  			args:      Pn_B__PgZM__Pd_B,
   124  		},
   125  	},
   126  	// PBRKBS
   127  	{
   128  		// PBRKBS <Pn>.B, <Pg>/Z, <Pd>.B
   129  		{
   130  			goOp:      APBRKBS,
   131  			fixedBits: 0x25d04000,
   132  			args:      Pn_B__PgZ__Pd_B,
   133  		},
   134  	},
   135  	// PBRKN
   136  	{
   137  		// PBRKN <Pdm>.B, <Pn>.B, <Pg>/Z, <Pdm>.B
   138  		{
   139  			goOp:      APBRKN,
   140  			fixedBits: 0x25184000,
   141  			args:      Pdm_B__Pn_B__PgZ__Pdm_B,
   142  		},
   143  	},
   144  	// PBRKNS
   145  	{
   146  		// PBRKNS <Pdm>.B, <Pn>.B, <Pg>/Z, <Pdm>.B
   147  		{
   148  			goOp:      APBRKNS,
   149  			fixedBits: 0x25584000,
   150  			args:      Pdm_B__Pn_B__PgZ__Pdm_B,
   151  		},
   152  	},
   153  	// PBRKPA
   154  	{
   155  		// PBRKPA <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   156  		{
   157  			goOp:      APBRKPA,
   158  			fixedBits: 0x2500c000,
   159  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   160  		},
   161  	},
   162  	// PBRKPAS
   163  	{
   164  		// PBRKPAS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   165  		{
   166  			goOp:      APBRKPAS,
   167  			fixedBits: 0x2540c000,
   168  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   169  		},
   170  	},
   171  	// PBRKPB
   172  	{
   173  		// PBRKPB <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   174  		{
   175  			goOp:      APBRKPB,
   176  			fixedBits: 0x2500c010,
   177  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   178  		},
   179  	},
   180  	// PBRKPBS
   181  	{
   182  		// PBRKPBS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   183  		{
   184  			goOp:      APBRKPBS,
   185  			fixedBits: 0x2540c010,
   186  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   187  		},
   188  	},
   189  	// PCNTP
   190  	{
   191  		// PCNTP <Pn>.<T>, <Pg>, <Xd>
   192  		{
   193  			goOp:      APCNTP,
   194  			fixedBits: 0x25208000,
   195  			args:      Pn_T__Pg__Xd,
   196  		},
   197  		// PCNTP <vl>, <PNn>.<T>, <Xd>
   198  		{
   199  			goOp:      APCNTP,
   200  			fixedBits: 0x25208200,
   201  			args:      vl__PNn_T__Xd,
   202  		},
   203  	},
   204  	// PDECP
   205  	{
   206  		// PDECP <Pm>.<T>, <Xdn>
   207  		{
   208  			goOp:      APDECP,
   209  			fixedBits: 0x252d8800,
   210  			args:      Pm_T__Xdn,
   211  		},
   212  	},
   213  	// PEOR
   214  	{
   215  		// PEOR <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   216  		{
   217  			goOp:      APEOR,
   218  			fixedBits: 0x25004200,
   219  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   220  		},
   221  	},
   222  	// PEORS
   223  	{
   224  		// PEORS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   225  		{
   226  			goOp:      APEORS,
   227  			fixedBits: 0x25404200,
   228  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   229  		},
   230  	},
   231  	// PFIRSTP
   232  	{
   233  		// PFIRSTP <Pn>.<T>, <Pg>, <Xd>
   234  		{
   235  			goOp:      APFIRSTP,
   236  			fixedBits: 0x25218000,
   237  			args:      Pn_T__Pg__Xd,
   238  		},
   239  	},
   240  	// PINCP
   241  	{
   242  		// PINCP <Pm>.<T>, <Xdn>
   243  		{
   244  			goOp:      APINCP,
   245  			fixedBits: 0x252c8800,
   246  			args:      Pm_T__Xdn,
   247  		},
   248  	},
   249  	// PLASTP
   250  	{
   251  		// PLASTP <Pn>.<T>, <Pg>, <Xd>
   252  		{
   253  			goOp:      APLASTP,
   254  			fixedBits: 0x25228000,
   255  			args:      Pn_T__Pg__Xd,
   256  		},
   257  	},
   258  	// PLDR
   259  	{
   260  		// PLDR [<Xn|SP>{, #<imm>, MUL VL}], <Pt>
   261  		{
   262  			goOp:      APLDR,
   263  			fixedBits: 0x85800000,
   264  			args:      XnSP__cimm__MUL_VL___Pt__1,
   265  		},
   266  	},
   267  	// PNAND
   268  	{
   269  		// PNAND <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   270  		{
   271  			goOp:      APNAND,
   272  			fixedBits: 0x25804210,
   273  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   274  		},
   275  	},
   276  	// PNANDS
   277  	{
   278  		// PNANDS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   279  		{
   280  			goOp:      APNANDS,
   281  			fixedBits: 0x25c04210,
   282  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   283  		},
   284  	},
   285  	// PNOR
   286  	{
   287  		// PNOR <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   288  		{
   289  			goOp:      APNOR,
   290  			fixedBits: 0x25804200,
   291  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   292  		},
   293  	},
   294  	// PNORS
   295  	{
   296  		// PNORS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   297  		{
   298  			goOp:      APNORS,
   299  			fixedBits: 0x25c04200,
   300  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   301  		},
   302  	},
   303  	// PORN
   304  	{
   305  		// PORN <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   306  		{
   307  			goOp:      APORN,
   308  			fixedBits: 0x25804010,
   309  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   310  		},
   311  	},
   312  	// PORNS
   313  	{
   314  		// PORNS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   315  		{
   316  			goOp:      APORNS,
   317  			fixedBits: 0x25c04010,
   318  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   319  		},
   320  	},
   321  	// PORR
   322  	{
   323  		// PORR <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   324  		{
   325  			goOp:      APORR,
   326  			fixedBits: 0x25804000,
   327  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   328  		},
   329  	},
   330  	// PORRS
   331  	{
   332  		// PORRS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B
   333  		{
   334  			goOp:      APORRS,
   335  			fixedBits: 0x25c04000,
   336  			args:      Pm_B__Pn_B__PgZ__Pd_B,
   337  		},
   338  	},
   339  	// PPEXT
   340  	{
   341  		// PPEXT <PNn>[<imm>], <Pd>.<T>
   342  		{
   343  			goOp:      APPEXT,
   344  			fixedBits: 0x25207010,
   345  			args:      PNn_imm___Pd_T,
   346  		},
   347  		// PPEXT <PNn>[<imm>], { <Pd1>.<T>, <Pd2>.<T> }
   348  		{
   349  			goOp:      APPEXT,
   350  			fixedBits: 0x25207410,
   351  			args:      PNn_imm____Pd1_T__Pd2_T_,
   352  		},
   353  	},
   354  	// PPFALSE
   355  	{
   356  		// PPFALSE <Pd>.B
   357  		{
   358  			goOp:      APPFALSE,
   359  			fixedBits: 0x2518e400,
   360  			args:      Pd_B,
   361  		},
   362  	},
   363  	// PPFIRST
   364  	{
   365  		// PPFIRST <Pdn>.B, <Pg>, <Pdn>.B
   366  		{
   367  			goOp:      APPFIRST,
   368  			fixedBits: 0x2558c000,
   369  			args:      Pdn_B__Pg__Pdn_B,
   370  		},
   371  	},
   372  	// PPNEXT
   373  	{
   374  		// PPNEXT <Pdn>.<T>, <Pv>, <Pdn>.<T>
   375  		{
   376  			goOp:      APPNEXT,
   377  			fixedBits: 0x2519c400,
   378  			args:      Pdn_T__Pv__Pdn_T,
   379  		},
   380  	},
   381  	// PPRFB
   382  	{
   383  		// PPRFB [<Xn|SP>, <Xm>], <Pg>, <prfop>
   384  		{
   385  			goOp:      APPRFB,
   386  			fixedBits: 0x8400c000,
   387  			args:      XnSP__Xm___Pg__prfop,
   388  		},
   389  		// PPRFB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
   390  		{
   391  			goOp:      APPRFB,
   392  			fixedBits: 0x85c00000,
   393  			args:      XnSP__cimm__MUL_VL___Pg__prfop,
   394  		},
   395  	},
   396  	// PPRFD
   397  	{
   398  		// PPRFD [<Xn|SP>, <Xm>, LSL #3], <Pg>, <prfop>
   399  		{
   400  			goOp:      APPRFD,
   401  			fixedBits: 0x8580c000,
   402  			args:      XnSP__Xm__LSL_c3___Pg__prfop,
   403  		},
   404  		// PPRFD [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
   405  		{
   406  			goOp:      APPRFD,
   407  			fixedBits: 0x85c06000,
   408  			args:      XnSP__cimm__MUL_VL___Pg__prfop,
   409  		},
   410  	},
   411  	// PPRFH
   412  	{
   413  		// PPRFH [<Xn|SP>, <Xm>, LSL #1], <Pg>, <prfop>
   414  		{
   415  			goOp:      APPRFH,
   416  			fixedBits: 0x8480c000,
   417  			args:      XnSP__Xm__LSL_c1___Pg__prfop,
   418  		},
   419  		// PPRFH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
   420  		{
   421  			goOp:      APPRFH,
   422  			fixedBits: 0x85c02000,
   423  			args:      XnSP__cimm__MUL_VL___Pg__prfop,
   424  		},
   425  	},
   426  	// PPRFW
   427  	{
   428  		// PPRFW [<Xn|SP>, <Xm>, LSL #2], <Pg>, <prfop>
   429  		{
   430  			goOp:      APPRFW,
   431  			fixedBits: 0x8500c000,
   432  			args:      XnSP__Xm__LSL_c2___Pg__prfop,
   433  		},
   434  		// PPRFW [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, <prfop>
   435  		{
   436  			goOp:      APPRFW,
   437  			fixedBits: 0x85c04000,
   438  			args:      XnSP__cimm__MUL_VL___Pg__prfop,
   439  		},
   440  	},
   441  	// PPTEST
   442  	{
   443  		// PPTEST <Pn>.B, <Pg>
   444  		{
   445  			goOp:      APPTEST,
   446  			fixedBits: 0x2550c000,
   447  			args:      Pn_B__Pg,
   448  		},
   449  	},
   450  	// PPTRUE
   451  	{
   452  		// PPTRUE <PNd>.<T>
   453  		{
   454  			goOp:      APPTRUE,
   455  			fixedBits: 0x25207810,
   456  			args:      PNd_T,
   457  		},
   458  	},
   459  	// PPUNPKHI
   460  	{
   461  		// PPUNPKHI <Pn>.B, <Pd>.H
   462  		{
   463  			goOp:      APPUNPKHI,
   464  			fixedBits: 0x5314000,
   465  			args:      Pn_B__Pd_H,
   466  		},
   467  	},
   468  	// PPUNPKLO
   469  	{
   470  		// PPUNPKLO <Pn>.B, <Pd>.H
   471  		{
   472  			goOp:      APPUNPKLO,
   473  			fixedBits: 0x5304000,
   474  			args:      Pn_B__Pd_H,
   475  		},
   476  	},
   477  	// PRDFFR
   478  	{
   479  		// PRDFFR <Pd>.B
   480  		{
   481  			goOp:      APRDFFR,
   482  			fixedBits: 0x2519f000,
   483  			args:      Pd_B,
   484  		},
   485  		// PRDFFR <Pg>/Z, <Pd>.B
   486  		{
   487  			goOp:      APRDFFR,
   488  			fixedBits: 0x2518f000,
   489  			args:      PgZ__Pd_B,
   490  		},
   491  	},
   492  	// PRDFFRS
   493  	{
   494  		// PRDFFRS <Pg>/Z, <Pd>.B
   495  		{
   496  			goOp:      APRDFFRS,
   497  			fixedBits: 0x2558f000,
   498  			args:      PgZ__Pd_B,
   499  		},
   500  	},
   501  	// PREV
   502  	{
   503  		// PREV <Pn>.<T>, <Pd>.<T>
   504  		{
   505  			goOp:      APREV,
   506  			fixedBits: 0x5344000,
   507  			args:      Pn_T__Pd_T,
   508  		},
   509  	},
   510  	// PSEL
   511  	{
   512  		// PSEL <Pm>.B, <Pn>.B, <Pg>, <Pd>.B
   513  		{
   514  			goOp:      APSEL,
   515  			fixedBits: 0x25004210,
   516  			args:      Pm_B__Pn_B__Pg__Pd_B,
   517  		},
   518  	},
   519  	// PSQDECP
   520  	{
   521  		// PSQDECP <Pm>.<T>, <Xdn>
   522  		{
   523  			goOp:      APSQDECP,
   524  			fixedBits: 0x252a8c00,
   525  			args:      Pm_T__Xdn,
   526  		},
   527  	},
   528  	// PSQDECPW
   529  	{
   530  		// PSQDECPW <Wdn>, <Pm>.<T>, <Xdn>
   531  		{
   532  			goOp:      APSQDECPW,
   533  			fixedBits: 0x252a8800,
   534  			args:      Wdn__Pm_T__Xdn,
   535  		},
   536  	},
   537  	// PSQINCP
   538  	{
   539  		// PSQINCP <Pm>.<T>, <Xdn>
   540  		{
   541  			goOp:      APSQINCP,
   542  			fixedBits: 0x25288c00,
   543  			args:      Pm_T__Xdn,
   544  		},
   545  	},
   546  	// PSQINCPW
   547  	{
   548  		// PSQINCPW <Wdn>, <Pm>.<T>, <Xdn>
   549  		{
   550  			goOp:      APSQINCPW,
   551  			fixedBits: 0x25288800,
   552  			args:      Wdn__Pm_T__Xdn,
   553  		},
   554  	},
   555  	// PSTR
   556  	{
   557  		// PSTR [<Xn|SP>{, #<imm>, MUL VL}], <Pt>
   558  		{
   559  			goOp:      APSTR,
   560  			fixedBits: 0xe5800000,
   561  			args:      XnSP__cimm__MUL_VL___Pt__2,
   562  		},
   563  	},
   564  	// PTRN1
   565  	{
   566  		// PTRN1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
   567  		{
   568  			goOp:      APTRN1,
   569  			fixedBits: 0x5205000,
   570  			args:      Pm_T__Pn_T__Pd_T,
   571  		},
   572  	},
   573  	// PTRN2
   574  	{
   575  		// PTRN2 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
   576  		{
   577  			goOp:      APTRN2,
   578  			fixedBits: 0x5205400,
   579  			args:      Pm_T__Pn_T__Pd_T,
   580  		},
   581  	},
   582  	// PUQDECP
   583  	{
   584  		// PUQDECP <Pm>.<T>, <Xdn>
   585  		{
   586  			goOp:      APUQDECP,
   587  			fixedBits: 0x252b8c00,
   588  			args:      Pm_T__Xdn,
   589  		},
   590  	},
   591  	// PUQDECPW
   592  	{
   593  		// PUQDECPW <Pm>.<T>, <Wdn>
   594  		{
   595  			goOp:      APUQDECPW,
   596  			fixedBits: 0x252b8800,
   597  			args:      Pm_T__Wdn,
   598  		},
   599  	},
   600  	// PUQINCP
   601  	{
   602  		// PUQINCP <Pm>.<T>, <Xdn>
   603  		{
   604  			goOp:      APUQINCP,
   605  			fixedBits: 0x25298c00,
   606  			args:      Pm_T__Xdn,
   607  		},
   608  	},
   609  	// PUQINCPW
   610  	{
   611  		// PUQINCPW <Pm>.<T>, <Wdn>
   612  		{
   613  			goOp:      APUQINCPW,
   614  			fixedBits: 0x25298800,
   615  			args:      Pm_T__Wdn,
   616  		},
   617  	},
   618  	// PUZP1
   619  	{
   620  		// PUZP1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
   621  		{
   622  			goOp:      APUZP1,
   623  			fixedBits: 0x5204800,
   624  			args:      Pm_T__Pn_T__Pd_T,
   625  		},
   626  	},
   627  	// PUZP2
   628  	{
   629  		// PUZP2 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
   630  		{
   631  			goOp:      APUZP2,
   632  			fixedBits: 0x5204c00,
   633  			args:      Pm_T__Pn_T__Pd_T,
   634  		},
   635  	},
   636  	// PWHILEGE
   637  	{
   638  		// PWHILEGE <R><m>, <R><n>, <Pd>.<T>
   639  		{
   640  			goOp:      APWHILEGE,
   641  			fixedBits: 0x25201000,
   642  			args:      Rm__Rn__Pd_T,
   643  		},
   644  		// PWHILEGE <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   645  		{
   646  			goOp:      APWHILEGE,
   647  			fixedBits: 0x25205010,
   648  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   649  		},
   650  		// PWHILEGE <vl>, <Xm>, <Xn>, <PNd>.<T>
   651  		{
   652  			goOp:      APWHILEGE,
   653  			fixedBits: 0x25204010,
   654  			args:      vl__Xm__Xn__PNd_T,
   655  		},
   656  	},
   657  	// PWHILEGEW
   658  	{
   659  		// PWHILEGEW <R><m>, <R><n>, <Pd>.<T>
   660  		{
   661  			goOp:      APWHILEGEW,
   662  			fixedBits: 0x25200000,
   663  			args:      Rm__Rn__Pd_T,
   664  		},
   665  	},
   666  	// PWHILEGT
   667  	{
   668  		// PWHILEGT <R><m>, <R><n>, <Pd>.<T>
   669  		{
   670  			goOp:      APWHILEGT,
   671  			fixedBits: 0x25201010,
   672  			args:      Rm__Rn__Pd_T,
   673  		},
   674  		// PWHILEGT <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   675  		{
   676  			goOp:      APWHILEGT,
   677  			fixedBits: 0x25205011,
   678  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   679  		},
   680  		// PWHILEGT <vl>, <Xm>, <Xn>, <PNd>.<T>
   681  		{
   682  			goOp:      APWHILEGT,
   683  			fixedBits: 0x25204018,
   684  			args:      vl__Xm__Xn__PNd_T,
   685  		},
   686  	},
   687  	// PWHILEGTW
   688  	{
   689  		// PWHILEGTW <R><m>, <R><n>, <Pd>.<T>
   690  		{
   691  			goOp:      APWHILEGTW,
   692  			fixedBits: 0x25200010,
   693  			args:      Rm__Rn__Pd_T,
   694  		},
   695  	},
   696  	// PWHILEHI
   697  	{
   698  		// PWHILEHI <R><m>, <R><n>, <Pd>.<T>
   699  		{
   700  			goOp:      APWHILEHI,
   701  			fixedBits: 0x25201810,
   702  			args:      Rm__Rn__Pd_T,
   703  		},
   704  		// PWHILEHI <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   705  		{
   706  			goOp:      APWHILEHI,
   707  			fixedBits: 0x25205811,
   708  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   709  		},
   710  		// PWHILEHI <vl>, <Xm>, <Xn>, <PNd>.<T>
   711  		{
   712  			goOp:      APWHILEHI,
   713  			fixedBits: 0x25204818,
   714  			args:      vl__Xm__Xn__PNd_T,
   715  		},
   716  	},
   717  	// PWHILEHIW
   718  	{
   719  		// PWHILEHIW <R><m>, <R><n>, <Pd>.<T>
   720  		{
   721  			goOp:      APWHILEHIW,
   722  			fixedBits: 0x25200810,
   723  			args:      Rm__Rn__Pd_T,
   724  		},
   725  	},
   726  	// PWHILEHS
   727  	{
   728  		// PWHILEHS <R><m>, <R><n>, <Pd>.<T>
   729  		{
   730  			goOp:      APWHILEHS,
   731  			fixedBits: 0x25201800,
   732  			args:      Rm__Rn__Pd_T,
   733  		},
   734  		// PWHILEHS <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   735  		{
   736  			goOp:      APWHILEHS,
   737  			fixedBits: 0x25205810,
   738  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   739  		},
   740  		// PWHILEHS <vl>, <Xm>, <Xn>, <PNd>.<T>
   741  		{
   742  			goOp:      APWHILEHS,
   743  			fixedBits: 0x25204810,
   744  			args:      vl__Xm__Xn__PNd_T,
   745  		},
   746  	},
   747  	// PWHILEHSW
   748  	{
   749  		// PWHILEHSW <R><m>, <R><n>, <Pd>.<T>
   750  		{
   751  			goOp:      APWHILEHSW,
   752  			fixedBits: 0x25200800,
   753  			args:      Rm__Rn__Pd_T,
   754  		},
   755  	},
   756  	// PWHILELE
   757  	{
   758  		// PWHILELE <R><m>, <R><n>, <Pd>.<T>
   759  		{
   760  			goOp:      APWHILELE,
   761  			fixedBits: 0x25201410,
   762  			args:      Rm__Rn__Pd_T,
   763  		},
   764  		// PWHILELE <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   765  		{
   766  			goOp:      APWHILELE,
   767  			fixedBits: 0x25205411,
   768  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   769  		},
   770  		// PWHILELE <vl>, <Xm>, <Xn>, <PNd>.<T>
   771  		{
   772  			goOp:      APWHILELE,
   773  			fixedBits: 0x25204418,
   774  			args:      vl__Xm__Xn__PNd_T,
   775  		},
   776  	},
   777  	// PWHILELEW
   778  	{
   779  		// PWHILELEW <R><m>, <R><n>, <Pd>.<T>
   780  		{
   781  			goOp:      APWHILELEW,
   782  			fixedBits: 0x25200410,
   783  			args:      Rm__Rn__Pd_T,
   784  		},
   785  	},
   786  	// PWHILELO
   787  	{
   788  		// PWHILELO <R><m>, <R><n>, <Pd>.<T>
   789  		{
   790  			goOp:      APWHILELO,
   791  			fixedBits: 0x25201c00,
   792  			args:      Rm__Rn__Pd_T,
   793  		},
   794  		// PWHILELO <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   795  		{
   796  			goOp:      APWHILELO,
   797  			fixedBits: 0x25205c10,
   798  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   799  		},
   800  		// PWHILELO <vl>, <Xm>, <Xn>, <PNd>.<T>
   801  		{
   802  			goOp:      APWHILELO,
   803  			fixedBits: 0x25204c10,
   804  			args:      vl__Xm__Xn__PNd_T,
   805  		},
   806  	},
   807  	// PWHILELOW
   808  	{
   809  		// PWHILELOW <R><m>, <R><n>, <Pd>.<T>
   810  		{
   811  			goOp:      APWHILELOW,
   812  			fixedBits: 0x25200c00,
   813  			args:      Rm__Rn__Pd_T,
   814  		},
   815  	},
   816  	// PWHILELS
   817  	{
   818  		// PWHILELS <R><m>, <R><n>, <Pd>.<T>
   819  		{
   820  			goOp:      APWHILELS,
   821  			fixedBits: 0x25201c10,
   822  			args:      Rm__Rn__Pd_T,
   823  		},
   824  		// PWHILELS <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   825  		{
   826  			goOp:      APWHILELS,
   827  			fixedBits: 0x25205c11,
   828  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   829  		},
   830  		// PWHILELS <vl>, <Xm>, <Xn>, <PNd>.<T>
   831  		{
   832  			goOp:      APWHILELS,
   833  			fixedBits: 0x25204c18,
   834  			args:      vl__Xm__Xn__PNd_T,
   835  		},
   836  	},
   837  	// PWHILELSW
   838  	{
   839  		// PWHILELSW <R><m>, <R><n>, <Pd>.<T>
   840  		{
   841  			goOp:      APWHILELSW,
   842  			fixedBits: 0x25200c10,
   843  			args:      Rm__Rn__Pd_T,
   844  		},
   845  	},
   846  	// PWHILELT
   847  	{
   848  		// PWHILELT <R><m>, <R><n>, <Pd>.<T>
   849  		{
   850  			goOp:      APWHILELT,
   851  			fixedBits: 0x25201400,
   852  			args:      Rm__Rn__Pd_T,
   853  		},
   854  		// PWHILELT <Xm>, <Xn>, { <Pd1>.<T>, <Pd2>.<T> }
   855  		{
   856  			goOp:      APWHILELT,
   857  			fixedBits: 0x25205410,
   858  			args:      Xm__Xn___Pd1_T__Pd2_T_,
   859  		},
   860  		// PWHILELT <vl>, <Xm>, <Xn>, <PNd>.<T>
   861  		{
   862  			goOp:      APWHILELT,
   863  			fixedBits: 0x25204410,
   864  			args:      vl__Xm__Xn__PNd_T,
   865  		},
   866  	},
   867  	// PWHILELTW
   868  	{
   869  		// PWHILELTW <R><m>, <R><n>, <Pd>.<T>
   870  		{
   871  			goOp:      APWHILELTW,
   872  			fixedBits: 0x25200400,
   873  			args:      Rm__Rn__Pd_T,
   874  		},
   875  	},
   876  	// PWHILERW
   877  	{
   878  		// PWHILERW <Xm>, <Xn>, <Pd>.<T>
   879  		{
   880  			goOp:      APWHILERW,
   881  			fixedBits: 0x25203010,
   882  			args:      Xm__Xn__Pd_T,
   883  		},
   884  	},
   885  	// PWHILEWR
   886  	{
   887  		// PWHILEWR <Xm>, <Xn>, <Pd>.<T>
   888  		{
   889  			goOp:      APWHILEWR,
   890  			fixedBits: 0x25203000,
   891  			args:      Xm__Xn__Pd_T,
   892  		},
   893  	},
   894  	// PWRFFR
   895  	{
   896  		// PWRFFR <Pn>.B
   897  		{
   898  			goOp:      APWRFFR,
   899  			fixedBits: 0x25289000,
   900  			args:      Pn_B,
   901  		},
   902  	},
   903  	// PZIP1
   904  	{
   905  		// PZIP1 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
   906  		{
   907  			goOp:      APZIP1,
   908  			fixedBits: 0x5204000,
   909  			args:      Pm_T__Pn_T__Pd_T,
   910  		},
   911  	},
   912  	// PZIP2
   913  	{
   914  		// PZIP2 <Pm>.<T>, <Pn>.<T>, <Pd>.<T>
   915  		{
   916  			goOp:      APZIP2,
   917  			fixedBits: 0x5204400,
   918  			args:      Pm_T__Pn_T__Pd_T,
   919  		},
   920  	},
   921  	// RDVL
   922  	{
   923  		// RDVL #<imm>, <Xd>
   924  		{
   925  			goOp:      ARDVL,
   926  			fixedBits: 0x4bf5000,
   927  			args:      cimm__Xd,
   928  		},
   929  	},
   930  	// SETFFR
   931  	{
   932  		// SETFFR
   933  		{
   934  			goOp:      ASETFFR,
   935  			fixedBits: 0x252c9000,
   936  			args:      oc,
   937  		},
   938  	},
   939  	// ZABS
   940  	{
   941  		// ZABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
   942  		{
   943  			goOp:      AZABS,
   944  			fixedBits: 0x416a000,
   945  			args:      Zn_T__PgM__Zd_T__2,
   946  		},
   947  		// ZABS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
   948  		{
   949  			goOp:      AZABS,
   950  			fixedBits: 0x406a000,
   951  			args:      Zn_T__PgZ__Zd_T__2,
   952  		},
   953  	},
   954  	// ZADCLB
   955  	{
   956  		// ZADCLB <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
   957  		{
   958  			goOp:      AZADCLB,
   959  			fixedBits: 0x4500d000,
   960  			args:      Zm_T__Zn_T__Zda_T__1,
   961  		},
   962  	},
   963  	// ZADCLT
   964  	{
   965  		// ZADCLT <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
   966  		{
   967  			goOp:      AZADCLT,
   968  			fixedBits: 0x4500d400,
   969  			args:      Zm_T__Zn_T__Zda_T__1,
   970  		},
   971  	},
   972  	// ZADD
   973  	{
   974  		// ZADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
   975  		{
   976  			goOp:      AZADD,
   977  			fixedBits: 0x4000000,
   978  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
   979  		},
   980  		// ZADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
   981  		{
   982  			goOp:      AZADD,
   983  			fixedBits: 0x4200000,
   984  			args:      Zm_T__Zn_T__Zd_T__1,
   985  		},
   986  		// ZADD #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T>
   987  		{
   988  			goOp:      AZADD,
   989  			fixedBits: 0x2520c000,
   990  			args:      cimm__shift__Zdn_T__Zdn_T,
   991  		},
   992  	},
   993  	// ZADDHNB
   994  	{
   995  		// ZADDHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
   996  		{
   997  			goOp:      AZADDHNB,
   998  			fixedBits: 0x45206000,
   999  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  1000  		},
  1001  	},
  1002  	// ZADDHNT
  1003  	{
  1004  		// ZADDHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  1005  		{
  1006  			goOp:      AZADDHNT,
  1007  			fixedBits: 0x45206400,
  1008  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  1009  		},
  1010  	},
  1011  	// ZADDP
  1012  	{
  1013  		// ZADDP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1014  		{
  1015  			goOp:      AZADDP,
  1016  			fixedBits: 0x4411a000,
  1017  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  1018  		},
  1019  	},
  1020  	// ZADDPT
  1021  	{
  1022  		// ZADDPT <Zm>.D, <Zdn>.D, <Pg>/M, <Zdn>.D
  1023  		{
  1024  			goOp:      AZADDPT,
  1025  			fixedBits: 0x4c40000,
  1026  			args:      Zm_D__Zdn_D__PgM__Zdn_D,
  1027  		},
  1028  		// ZADDPT <Zm>.D, <Zn>.D, <Zd>.D
  1029  		{
  1030  			goOp:      AZADDPT,
  1031  			fixedBits: 0x4e00800,
  1032  			args:      Zm_D__Zn_D__Zd_D,
  1033  		},
  1034  	},
  1035  	// ZADDQP
  1036  	{
  1037  		// ZADDQP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  1038  		{
  1039  			goOp:      AZADDQP,
  1040  			fixedBits: 0x4207800,
  1041  			args:      Zm_T__Zn_T__Zd_T__1,
  1042  		},
  1043  	},
  1044  	// ZADDQV
  1045  	{
  1046  		// ZADDQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  1047  		{
  1048  			goOp:      AZADDQV,
  1049  			fixedBits: 0x4052000,
  1050  			args:      Zn_Tb__Pg__Vd_T__1,
  1051  		},
  1052  	},
  1053  	// ZADDSUBP
  1054  	{
  1055  		// ZADDSUBP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  1056  		{
  1057  			goOp:      AZADDSUBP,
  1058  			fixedBits: 0x4207c00,
  1059  			args:      Zm_T__Zn_T__Zd_T__1,
  1060  		},
  1061  	},
  1062  	// ZADR
  1063  	{
  1064  		// ZADR [<Zn>.D, <Zm>.D, SXTW{<amount>}], <Zd>.D
  1065  		{
  1066  			goOp:      AZADR,
  1067  			fixedBits: 0x420a000,
  1068  			args:      Zn_D__Zm_D__SXTWamount___Zd_D,
  1069  		},
  1070  		// ZADR [<Zn>.D, <Zm>.D, UXTW{<amount>}], <Zd>.D
  1071  		{
  1072  			goOp:      AZADR,
  1073  			fixedBits: 0x460a000,
  1074  			args:      Zn_D__Zm_D__UXTWamount___Zd_D,
  1075  		},
  1076  		// ZADR [<Zn>.<T>, <Zm>.<T>{, <mod> <amount>}], <Zd>.<T>
  1077  		{
  1078  			goOp:      AZADR,
  1079  			fixedBits: 0x4a0a000,
  1080  			args:      Zn_T__Zm_T__mod_amount___Zd_T,
  1081  		},
  1082  	},
  1083  	// ZAESD
  1084  	{
  1085  		// ZAESD <Zm>.B, <Zdn>.B, <Zdn>.B
  1086  		{
  1087  			goOp:      AZAESD,
  1088  			fixedBits: 0x4522e400,
  1089  			args:      Zm_B__Zdn_B__Zdn_B,
  1090  		},
  1091  		// ZAESD <Zm>.Q[<index>], { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }
  1092  		{
  1093  			goOp:      AZAESD,
  1094  			fixedBits: 0x4522ec00,
  1095  			args:      Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_,
  1096  		},
  1097  		// ZAESD <Zm>.Q[<index>], { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }
  1098  		{
  1099  			goOp:      AZAESD,
  1100  			fixedBits: 0x4526ec00,
  1101  			args:      Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_,
  1102  		},
  1103  	},
  1104  	// ZAESDIMC
  1105  	{
  1106  		// ZAESDIMC <Zm>.Q[<index>], { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }
  1107  		{
  1108  			goOp:      AZAESDIMC,
  1109  			fixedBits: 0x4523ec00,
  1110  			args:      Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_,
  1111  		},
  1112  		// ZAESDIMC <Zm>.Q[<index>], { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }
  1113  		{
  1114  			goOp:      AZAESDIMC,
  1115  			fixedBits: 0x4527ec00,
  1116  			args:      Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_,
  1117  		},
  1118  	},
  1119  	// ZAESE
  1120  	{
  1121  		// ZAESE <Zm>.B, <Zdn>.B, <Zdn>.B
  1122  		{
  1123  			goOp:      AZAESE,
  1124  			fixedBits: 0x4522e000,
  1125  			args:      Zm_B__Zdn_B__Zdn_B,
  1126  		},
  1127  		// ZAESE <Zm>.Q[<index>], { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }
  1128  		{
  1129  			goOp:      AZAESE,
  1130  			fixedBits: 0x4522e800,
  1131  			args:      Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_,
  1132  		},
  1133  		// ZAESE <Zm>.Q[<index>], { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }
  1134  		{
  1135  			goOp:      AZAESE,
  1136  			fixedBits: 0x4526e800,
  1137  			args:      Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_,
  1138  		},
  1139  	},
  1140  	// ZAESEMC
  1141  	{
  1142  		// ZAESEMC <Zm>.Q[<index>], { <Zdn1>.B-<Zdn2>.B }, { <Zdn1>.B-<Zdn2>.B }
  1143  		{
  1144  			goOp:      AZAESEMC,
  1145  			fixedBits: 0x4523e800,
  1146  			args:      Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_,
  1147  		},
  1148  		// ZAESEMC <Zm>.Q[<index>], { <Zdn1>.B-<Zdn4>.B }, { <Zdn1>.B-<Zdn4>.B }
  1149  		{
  1150  			goOp:      AZAESEMC,
  1151  			fixedBits: 0x4527e800,
  1152  			args:      Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_,
  1153  		},
  1154  	},
  1155  	// ZAESIMC
  1156  	{
  1157  		// ZAESIMC <Zdn>.B, <Zdn>.B
  1158  		{
  1159  			goOp:      AZAESIMC,
  1160  			fixedBits: 0x4520e400,
  1161  			args:      Zdn_B__Zdn_B,
  1162  		},
  1163  	},
  1164  	// ZAESMC
  1165  	{
  1166  		// ZAESMC <Zdn>.B, <Zdn>.B
  1167  		{
  1168  			goOp:      AZAESMC,
  1169  			fixedBits: 0x4520e000,
  1170  			args:      Zdn_B__Zdn_B,
  1171  		},
  1172  	},
  1173  	// ZAND
  1174  	{
  1175  		// ZAND <Zm>.D, <Zn>.D, <Zd>.D
  1176  		{
  1177  			goOp:      AZAND,
  1178  			fixedBits: 0x4203000,
  1179  			args:      Zm_D__Zn_D__Zd_D,
  1180  		},
  1181  		// ZAND <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1182  		{
  1183  			goOp:      AZAND,
  1184  			fixedBits: 0x41a0000,
  1185  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  1186  		},
  1187  		// ZAND #<const>, <Zdn>.<T>, <Zdn>.<T>
  1188  		{
  1189  			goOp:      AZAND,
  1190  			fixedBits: 0x5800000,
  1191  			args:      cconst__Zdn_T__Zdn_T,
  1192  		},
  1193  	},
  1194  	// ZANDQV
  1195  	{
  1196  		// ZANDQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  1197  		{
  1198  			goOp:      AZANDQV,
  1199  			fixedBits: 0x41e2000,
  1200  			args:      Zn_Tb__Pg__Vd_T__1,
  1201  		},
  1202  	},
  1203  	// ZANDVB
  1204  	{
  1205  		// ZANDVB <Zn>.<T>, <Pg>, <V><d>
  1206  		{
  1207  			goOp:      AZANDVB,
  1208  			fixedBits: 0x41a2000,
  1209  			args:      Zn_T__Pg__Vd__1,
  1210  		},
  1211  	},
  1212  	// ZANDVD
  1213  	{
  1214  		// ZANDVD <Zn>.<T>, <Pg>, <V><d>
  1215  		{
  1216  			goOp:      AZANDVD,
  1217  			fixedBits: 0x4da2000,
  1218  			args:      Zn_T__Pg__Vd__1,
  1219  		},
  1220  	},
  1221  	// ZANDVH
  1222  	{
  1223  		// ZANDVH <Zn>.<T>, <Pg>, <V><d>
  1224  		{
  1225  			goOp:      AZANDVH,
  1226  			fixedBits: 0x45a2000,
  1227  			args:      Zn_T__Pg__Vd__1,
  1228  		},
  1229  	},
  1230  	// ZANDVS
  1231  	{
  1232  		// ZANDVS <Zn>.<T>, <Pg>, <V><d>
  1233  		{
  1234  			goOp:      AZANDVS,
  1235  			fixedBits: 0x49a2000,
  1236  			args:      Zn_T__Pg__Vd__1,
  1237  		},
  1238  	},
  1239  	// ZASR
  1240  	{
  1241  		// ZASR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1242  		{
  1243  			goOp:      AZASR,
  1244  			fixedBits: 0x4188000,
  1245  			args:      Zm_D__Zdn_T__PgM__Zdn_T,
  1246  		},
  1247  		// ZASR <Zm>.D, <Zn>.<T>, <Zd>.<T>
  1248  		{
  1249  			goOp:      AZASR,
  1250  			fixedBits: 0x4208000,
  1251  			args:      Zm_D__Zn_T__Zd_T,
  1252  		},
  1253  		// ZASR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1254  		{
  1255  			goOp:      AZASR,
  1256  			fixedBits: 0x4108000,
  1257  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  1258  		},
  1259  		// ZASR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1260  		{
  1261  			goOp:      AZASR,
  1262  			fixedBits: 0x4008000,
  1263  			args:      cconst__Zdn_T__PgM__Zdn_T__1,
  1264  		},
  1265  		// ZASR #<const>, <Zn>.<T>, <Zd>.<T>
  1266  		{
  1267  			goOp:      AZASR,
  1268  			fixedBits: 0x4209000,
  1269  			args:      cconst__Zn_T__Zd_T__1,
  1270  		},
  1271  	},
  1272  	// ZASRD
  1273  	{
  1274  		// ZASRD #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1275  		{
  1276  			goOp:      AZASRD,
  1277  			fixedBits: 0x4048000,
  1278  			args:      cconst__Zdn_T__PgM__Zdn_T__1,
  1279  		},
  1280  	},
  1281  	// ZASRR
  1282  	{
  1283  		// ZASRR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1284  		{
  1285  			goOp:      AZASRR,
  1286  			fixedBits: 0x4148000,
  1287  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  1288  		},
  1289  	},
  1290  	// ZBCAX
  1291  	{
  1292  		// ZBCAX <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
  1293  		{
  1294  			goOp:      AZBCAX,
  1295  			fixedBits: 0x4603800,
  1296  			args:      Zk_D__Zm_D__Zdn_D__Zdn_D,
  1297  		},
  1298  	},
  1299  	// ZBDEP
  1300  	{
  1301  		// ZBDEP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  1302  		{
  1303  			goOp:      AZBDEP,
  1304  			fixedBits: 0x4500b400,
  1305  			args:      Zm_T__Zn_T__Zd_T__1,
  1306  		},
  1307  	},
  1308  	// ZBEXT
  1309  	{
  1310  		// ZBEXT <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  1311  		{
  1312  			goOp:      AZBEXT,
  1313  			fixedBits: 0x4500b000,
  1314  			args:      Zm_T__Zn_T__Zd_T__1,
  1315  		},
  1316  	},
  1317  	// ZBF1CVT
  1318  	{
  1319  		// ZBF1CVT <Zn>.B, <Zd>.H
  1320  		{
  1321  			goOp:      AZBF1CVT,
  1322  			fixedBits: 0x65083800,
  1323  			args:      Zn_B__Zd_H,
  1324  		},
  1325  	},
  1326  	// ZBF1CVTLT
  1327  	{
  1328  		// ZBF1CVTLT <Zn>.B, <Zd>.H
  1329  		{
  1330  			goOp:      AZBF1CVTLT,
  1331  			fixedBits: 0x65093800,
  1332  			args:      Zn_B__Zd_H,
  1333  		},
  1334  	},
  1335  	// ZBF2CVT
  1336  	{
  1337  		// ZBF2CVT <Zn>.B, <Zd>.H
  1338  		{
  1339  			goOp:      AZBF2CVT,
  1340  			fixedBits: 0x65083c00,
  1341  			args:      Zn_B__Zd_H,
  1342  		},
  1343  	},
  1344  	// ZBF2CVTLT
  1345  	{
  1346  		// ZBF2CVTLT <Zn>.B, <Zd>.H
  1347  		{
  1348  			goOp:      AZBF2CVTLT,
  1349  			fixedBits: 0x65093c00,
  1350  			args:      Zn_B__Zd_H,
  1351  		},
  1352  	},
  1353  	// ZBFADD
  1354  	{
  1355  		// ZBFADD <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1356  		{
  1357  			goOp:      AZBFADD,
  1358  			fixedBits: 0x65008000,
  1359  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1360  		},
  1361  		// ZBFADD <Zm>.H, <Zn>.H, <Zd>.H
  1362  		{
  1363  			goOp:      AZBFADD,
  1364  			fixedBits: 0x65000000,
  1365  			args:      Zm_H__Zn_H__Zd_H,
  1366  		},
  1367  	},
  1368  	// ZBFCLAMP
  1369  	{
  1370  		// ZBFCLAMP <Zm>.H, <Zn>.H, <Zd>.H
  1371  		{
  1372  			goOp:      AZBFCLAMP,
  1373  			fixedBits: 0x64202400,
  1374  			args:      Zm_H__Zn_H__Zd_H,
  1375  		},
  1376  	},
  1377  	// ZBFCVT
  1378  	{
  1379  		// ZBFCVT <Zn>.S, <Pg>/M, <Zd>.H
  1380  		{
  1381  			goOp:      AZBFCVT,
  1382  			fixedBits: 0x658aa000,
  1383  			args:      Zn_S__PgM__Zd_H,
  1384  		},
  1385  		// ZBFCVT <Zn>.S, <Pg>/Z, <Zd>.H
  1386  		{
  1387  			goOp:      AZBFCVT,
  1388  			fixedBits: 0x649ac000,
  1389  			args:      Zn_S__PgZ__Zd_H,
  1390  		},
  1391  	},
  1392  	// ZBFCVTN
  1393  	{
  1394  		// ZBFCVTN { <Zn1>.H-<Zn2>.H }, <Zd>.B
  1395  		{
  1396  			goOp:      AZBFCVTN,
  1397  			fixedBits: 0x650a3800,
  1398  			args:      Zn1_H_Zn2_H___Zd_B,
  1399  		},
  1400  	},
  1401  	// ZBFCVTNT
  1402  	{
  1403  		// ZBFCVTNT <Zn>.S, <Pg>/M, <Zd>.H
  1404  		{
  1405  			goOp:      AZBFCVTNT,
  1406  			fixedBits: 0x648aa000,
  1407  			args:      Zn_S__PgM__Zd_H,
  1408  		},
  1409  		// ZBFCVTNT <Zn>.S, <Pg>/Z, <Zd>.H
  1410  		{
  1411  			goOp:      AZBFCVTNT,
  1412  			fixedBits: 0x6482a000,
  1413  			args:      Zn_S__PgZ__Zd_H,
  1414  		},
  1415  	},
  1416  	// ZBFDOT
  1417  	{
  1418  		// ZBFDOT <Zm>.H, <Zn>.H, <Zda>.S
  1419  		{
  1420  			goOp:      AZBFDOT,
  1421  			fixedBits: 0x64608000,
  1422  			args:      Zm_H__Zn_H__Zda_S,
  1423  		},
  1424  		// ZBFDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  1425  		{
  1426  			goOp:      AZBFDOT,
  1427  			fixedBits: 0x64604000,
  1428  			args:      Zm_H_imm___Zn_H__Zda_S__3,
  1429  		},
  1430  	},
  1431  	// ZBFMAX
  1432  	{
  1433  		// ZBFMAX <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1434  		{
  1435  			goOp:      AZBFMAX,
  1436  			fixedBits: 0x65068000,
  1437  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1438  		},
  1439  	},
  1440  	// ZBFMAXNM
  1441  	{
  1442  		// ZBFMAXNM <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1443  		{
  1444  			goOp:      AZBFMAXNM,
  1445  			fixedBits: 0x65048000,
  1446  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1447  		},
  1448  	},
  1449  	// ZBFMIN
  1450  	{
  1451  		// ZBFMIN <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1452  		{
  1453  			goOp:      AZBFMIN,
  1454  			fixedBits: 0x65078000,
  1455  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1456  		},
  1457  	},
  1458  	// ZBFMINNM
  1459  	{
  1460  		// ZBFMINNM <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1461  		{
  1462  			goOp:      AZBFMINNM,
  1463  			fixedBits: 0x65058000,
  1464  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1465  		},
  1466  	},
  1467  	// ZBFMLA
  1468  	{
  1469  		// ZBFMLA <Zm>.H, <Zn>.H, <Pg>/M, <Zda>.H
  1470  		{
  1471  			goOp:      AZBFMLA,
  1472  			fixedBits: 0x65200000,
  1473  			args:      Zm_H__Zn_H__PgM__Zda_H,
  1474  		},
  1475  		// ZBFMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  1476  		{
  1477  			goOp:      AZBFMLA,
  1478  			fixedBits: 0x64200800,
  1479  			args:      Zm_H_imm___Zn_H__Zda_H__2,
  1480  		},
  1481  	},
  1482  	// ZBFMLALB
  1483  	{
  1484  		// ZBFMLALB <Zm>.H, <Zn>.H, <Zda>.S
  1485  		{
  1486  			goOp:      AZBFMLALB,
  1487  			fixedBits: 0x64e08000,
  1488  			args:      Zm_H__Zn_H__Zda_S,
  1489  		},
  1490  		// ZBFMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  1491  		{
  1492  			goOp:      AZBFMLALB,
  1493  			fixedBits: 0x64e04000,
  1494  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  1495  		},
  1496  	},
  1497  	// ZBFMLALT
  1498  	{
  1499  		// ZBFMLALT <Zm>.H, <Zn>.H, <Zda>.S
  1500  		{
  1501  			goOp:      AZBFMLALT,
  1502  			fixedBits: 0x64e08400,
  1503  			args:      Zm_H__Zn_H__Zda_S,
  1504  		},
  1505  		// ZBFMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  1506  		{
  1507  			goOp:      AZBFMLALT,
  1508  			fixedBits: 0x64e04400,
  1509  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  1510  		},
  1511  	},
  1512  	// ZBFMLS
  1513  	{
  1514  		// ZBFMLS <Zm>.H, <Zn>.H, <Pg>/M, <Zda>.H
  1515  		{
  1516  			goOp:      AZBFMLS,
  1517  			fixedBits: 0x65202000,
  1518  			args:      Zm_H__Zn_H__PgM__Zda_H,
  1519  		},
  1520  		// ZBFMLS <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  1521  		{
  1522  			goOp:      AZBFMLS,
  1523  			fixedBits: 0x64200c00,
  1524  			args:      Zm_H_imm___Zn_H__Zda_H__2,
  1525  		},
  1526  	},
  1527  	// ZBFMLSLB
  1528  	{
  1529  		// ZBFMLSLB <Zm>.H, <Zn>.H, <Zda>.S
  1530  		{
  1531  			goOp:      AZBFMLSLB,
  1532  			fixedBits: 0x64e0a000,
  1533  			args:      Zm_H__Zn_H__Zda_S,
  1534  		},
  1535  		// ZBFMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  1536  		{
  1537  			goOp:      AZBFMLSLB,
  1538  			fixedBits: 0x64e06000,
  1539  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  1540  		},
  1541  	},
  1542  	// ZBFMLSLT
  1543  	{
  1544  		// ZBFMLSLT <Zm>.H, <Zn>.H, <Zda>.S
  1545  		{
  1546  			goOp:      AZBFMLSLT,
  1547  			fixedBits: 0x64e0a400,
  1548  			args:      Zm_H__Zn_H__Zda_S,
  1549  		},
  1550  		// ZBFMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  1551  		{
  1552  			goOp:      AZBFMLSLT,
  1553  			fixedBits: 0x64e06400,
  1554  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  1555  		},
  1556  	},
  1557  	// ZBFMMLA
  1558  	{
  1559  		// ZBFMMLA <Zm>.H, <Zn>.H, <Zda>.H
  1560  		{
  1561  			goOp:      AZBFMMLA,
  1562  			fixedBits: 0x64e0e000,
  1563  			args:      Zm_H__Zn_H__Zda_H,
  1564  		},
  1565  		// ZBFMMLA <Zm>.H, <Zn>.H, <Zda>.S
  1566  		{
  1567  			goOp:      AZBFMMLA,
  1568  			fixedBits: 0x6460e400,
  1569  			args:      Zm_H__Zn_H__Zda_S,
  1570  		},
  1571  	},
  1572  	// ZBFMUL
  1573  	{
  1574  		// ZBFMUL <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1575  		{
  1576  			goOp:      AZBFMUL,
  1577  			fixedBits: 0x65028000,
  1578  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1579  		},
  1580  		// ZBFMUL <Zm>.H, <Zn>.H, <Zd>.H
  1581  		{
  1582  			goOp:      AZBFMUL,
  1583  			fixedBits: 0x65000800,
  1584  			args:      Zm_H__Zn_H__Zd_H,
  1585  		},
  1586  		// ZBFMUL <Zm>.H[<imm>], <Zn>.H, <Zd>.H
  1587  		{
  1588  			goOp:      AZBFMUL,
  1589  			fixedBits: 0x64202800,
  1590  			args:      Zm_H_imm___Zn_H__Zd_H__2,
  1591  		},
  1592  	},
  1593  	// ZBFSCALE
  1594  	{
  1595  		// ZBFSCALE <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1596  		{
  1597  			goOp:      AZBFSCALE,
  1598  			fixedBits: 0x65098000,
  1599  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1600  		},
  1601  	},
  1602  	// ZBFSUB
  1603  	{
  1604  		// ZBFSUB <Zm>.H, <Zdn>.H, <Pg>/M, <Zdn>.H
  1605  		{
  1606  			goOp:      AZBFSUB,
  1607  			fixedBits: 0x65018000,
  1608  			args:      Zm_H__Zdn_H__PgM__Zdn_H,
  1609  		},
  1610  		// ZBFSUB <Zm>.H, <Zn>.H, <Zd>.H
  1611  		{
  1612  			goOp:      AZBFSUB,
  1613  			fixedBits: 0x65000400,
  1614  			args:      Zm_H__Zn_H__Zd_H,
  1615  		},
  1616  	},
  1617  	// ZBGRP
  1618  	{
  1619  		// ZBGRP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  1620  		{
  1621  			goOp:      AZBGRP,
  1622  			fixedBits: 0x4500b800,
  1623  			args:      Zm_T__Zn_T__Zd_T__1,
  1624  		},
  1625  	},
  1626  	// ZBIC
  1627  	{
  1628  		// ZBIC <Zm>.D, <Zn>.D, <Zd>.D
  1629  		{
  1630  			goOp:      AZBIC,
  1631  			fixedBits: 0x4e03000,
  1632  			args:      Zm_D__Zn_D__Zd_D,
  1633  		},
  1634  		// ZBIC <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  1635  		{
  1636  			goOp:      AZBIC,
  1637  			fixedBits: 0x41b0000,
  1638  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  1639  		},
  1640  	},
  1641  	// ZBSL
  1642  	{
  1643  		// ZBSL <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
  1644  		{
  1645  			goOp:      AZBSL,
  1646  			fixedBits: 0x4203c00,
  1647  			args:      Zk_D__Zm_D__Zdn_D__Zdn_D,
  1648  		},
  1649  	},
  1650  	// ZBSL1N
  1651  	{
  1652  		// ZBSL1N <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
  1653  		{
  1654  			goOp:      AZBSL1N,
  1655  			fixedBits: 0x4603c00,
  1656  			args:      Zk_D__Zm_D__Zdn_D__Zdn_D,
  1657  		},
  1658  	},
  1659  	// ZBSL2N
  1660  	{
  1661  		// ZBSL2N <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
  1662  		{
  1663  			goOp:      AZBSL2N,
  1664  			fixedBits: 0x4a03c00,
  1665  			args:      Zk_D__Zm_D__Zdn_D__Zdn_D,
  1666  		},
  1667  	},
  1668  	// ZCADD
  1669  	{
  1670  		// ZCADD <const>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T>
  1671  		{
  1672  			goOp:      AZCADD,
  1673  			fixedBits: 0x4500d800,
  1674  			args:      const__Zm_T__Zdn_T__Zdn_T,
  1675  		},
  1676  	},
  1677  	// ZCDOT
  1678  	{
  1679  		// ZCDOT <const>, <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  1680  		{
  1681  			goOp:      AZCDOT,
  1682  			fixedBits: 0x44a04000,
  1683  			args:      const__Zm_B_imm___Zn_B__Zda_S,
  1684  		},
  1685  		// ZCDOT <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.D
  1686  		{
  1687  			goOp:      AZCDOT,
  1688  			fixedBits: 0x44e04000,
  1689  			args:      const__Zm_H_imm___Zn_H__Zda_D,
  1690  		},
  1691  		// ZCDOT <const>, <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  1692  		{
  1693  			goOp:      AZCDOT,
  1694  			fixedBits: 0x44801000,
  1695  			args:      const__Zm_Tb__Zn_Tb__Zda_T,
  1696  		},
  1697  	},
  1698  	// ZCLASTA
  1699  	{
  1700  		// ZCLASTA <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T>
  1701  		{
  1702  			goOp:      AZCLASTA,
  1703  			fixedBits: 0x5288000,
  1704  			args:      Zm_T__Zdn_T__Pg__Zdn_T,
  1705  		},
  1706  		// ZCLASTA <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
  1707  		{
  1708  			goOp:      AZCLASTA,
  1709  			fixedBits: 0x5f0a000,
  1710  			args:      Zm_T__Rdn__Pg__Rdn,
  1711  		},
  1712  	},
  1713  	// ZCLASTAB
  1714  	{
  1715  		// ZCLASTAB <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1716  		{
  1717  			goOp:      AZCLASTAB,
  1718  			fixedBits: 0x52a8000,
  1719  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1720  		},
  1721  	},
  1722  	// ZCLASTAD
  1723  	{
  1724  		// ZCLASTAD <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1725  		{
  1726  			goOp:      AZCLASTAD,
  1727  			fixedBits: 0x5ea8000,
  1728  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1729  		},
  1730  	},
  1731  	// ZCLASTAH
  1732  	{
  1733  		// ZCLASTAH <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1734  		{
  1735  			goOp:      AZCLASTAH,
  1736  			fixedBits: 0x56a8000,
  1737  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1738  		},
  1739  	},
  1740  	// ZCLASTAS
  1741  	{
  1742  		// ZCLASTAS <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1743  		{
  1744  			goOp:      AZCLASTAS,
  1745  			fixedBits: 0x5aa8000,
  1746  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1747  		},
  1748  	},
  1749  	// ZCLASTAW
  1750  	{
  1751  		// ZCLASTAW <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
  1752  		{
  1753  			goOp:      AZCLASTAW,
  1754  			fixedBits: 0x530a000,
  1755  			args:      Zm_T__Rdn__Pg__Rdn,
  1756  		},
  1757  	},
  1758  	// ZCLASTB
  1759  	{
  1760  		// ZCLASTB <Zm>.<T>, <Zdn>.<T>, <Pg>, <Zdn>.<T>
  1761  		{
  1762  			goOp:      AZCLASTB,
  1763  			fixedBits: 0x5298000,
  1764  			args:      Zm_T__Zdn_T__Pg__Zdn_T,
  1765  		},
  1766  		// ZCLASTB <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
  1767  		{
  1768  			goOp:      AZCLASTB,
  1769  			fixedBits: 0x5f1a000,
  1770  			args:      Zm_T__Rdn__Pg__Rdn,
  1771  		},
  1772  	},
  1773  	// ZCLASTBB
  1774  	{
  1775  		// ZCLASTBB <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1776  		{
  1777  			goOp:      AZCLASTBB,
  1778  			fixedBits: 0x52b8000,
  1779  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1780  		},
  1781  	},
  1782  	// ZCLASTBD
  1783  	{
  1784  		// ZCLASTBD <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1785  		{
  1786  			goOp:      AZCLASTBD,
  1787  			fixedBits: 0x5eb8000,
  1788  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1789  		},
  1790  	},
  1791  	// ZCLASTBH
  1792  	{
  1793  		// ZCLASTBH <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1794  		{
  1795  			goOp:      AZCLASTBH,
  1796  			fixedBits: 0x56b8000,
  1797  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1798  		},
  1799  	},
  1800  	// ZCLASTBS
  1801  	{
  1802  		// ZCLASTBS <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  1803  		{
  1804  			goOp:      AZCLASTBS,
  1805  			fixedBits: 0x5ab8000,
  1806  			args:      Zm_T__Vdn__Pg__Vdn__1,
  1807  		},
  1808  	},
  1809  	// ZCLASTBW
  1810  	{
  1811  		// ZCLASTBW <Zm>.<T>, <R><dn>, <Pg>, <R><dn>
  1812  		{
  1813  			goOp:      AZCLASTBW,
  1814  			fixedBits: 0x531a000,
  1815  			args:      Zm_T__Rdn__Pg__Rdn,
  1816  		},
  1817  	},
  1818  	// ZCLS
  1819  	{
  1820  		// ZCLS <Zn>.<T>, <Pg>/M, <Zd>.<T>
  1821  		{
  1822  			goOp:      AZCLS,
  1823  			fixedBits: 0x418a000,
  1824  			args:      Zn_T__PgM__Zd_T__2,
  1825  		},
  1826  		// ZCLS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  1827  		{
  1828  			goOp:      AZCLS,
  1829  			fixedBits: 0x408a000,
  1830  			args:      Zn_T__PgZ__Zd_T__2,
  1831  		},
  1832  	},
  1833  	// ZCLZ
  1834  	{
  1835  		// ZCLZ <Zn>.<T>, <Pg>/M, <Zd>.<T>
  1836  		{
  1837  			goOp:      AZCLZ,
  1838  			fixedBits: 0x419a000,
  1839  			args:      Zn_T__PgM__Zd_T__2,
  1840  		},
  1841  		// ZCLZ <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  1842  		{
  1843  			goOp:      AZCLZ,
  1844  			fixedBits: 0x409a000,
  1845  			args:      Zn_T__PgZ__Zd_T__2,
  1846  		},
  1847  	},
  1848  	// ZCMLA
  1849  	{
  1850  		// ZCMLA <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  1851  		{
  1852  			goOp:      AZCMLA,
  1853  			fixedBits: 0x44a06000,
  1854  			args:      const__Zm_H_imm___Zn_H__Zda_H__1,
  1855  		},
  1856  		// ZCMLA <const>, <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  1857  		{
  1858  			goOp:      AZCMLA,
  1859  			fixedBits: 0x44e06000,
  1860  			args:      const__Zm_S_imm___Zn_S__Zda_S__1,
  1861  		},
  1862  		// ZCMLA <const>, <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  1863  		{
  1864  			goOp:      AZCMLA,
  1865  			fixedBits: 0x44002000,
  1866  			args:      const__Zm_T__Zn_T__Zda_T,
  1867  		},
  1868  	},
  1869  	// ZCMPEQ
  1870  	{
  1871  		// ZCMPEQ <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1872  		{
  1873  			goOp:      AZCMPEQ,
  1874  			fixedBits: 0x24002000,
  1875  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  1876  		},
  1877  		// ZCMPEQ <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1878  		{
  1879  			goOp:      AZCMPEQ,
  1880  			fixedBits: 0x2400a000,
  1881  			args:      Zm_T__Zn_T__PgZ__Pd_T__2,
  1882  		},
  1883  		// ZCMPEQ #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1884  		{
  1885  			goOp:      AZCMPEQ,
  1886  			fixedBits: 0x25008000,
  1887  			args:      cimm__Zn_T__PgZ__Pd_T__1,
  1888  		},
  1889  	},
  1890  	// ZCMPGE
  1891  	{
  1892  		// ZCMPGE <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1893  		{
  1894  			goOp:      AZCMPGE,
  1895  			fixedBits: 0x24004000,
  1896  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  1897  		},
  1898  		// ZCMPGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1899  		{
  1900  			goOp:      AZCMPGE,
  1901  			fixedBits: 0x24008000,
  1902  			args:      Zm_T__Zn_T__PgZ__Pd_T__2,
  1903  		},
  1904  		// ZCMPGE #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1905  		{
  1906  			goOp:      AZCMPGE,
  1907  			fixedBits: 0x25000000,
  1908  			args:      cimm__Zn_T__PgZ__Pd_T__1,
  1909  		},
  1910  	},
  1911  	// ZCMPGT
  1912  	{
  1913  		// ZCMPGT <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1914  		{
  1915  			goOp:      AZCMPGT,
  1916  			fixedBits: 0x24004010,
  1917  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  1918  		},
  1919  		// ZCMPGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1920  		{
  1921  			goOp:      AZCMPGT,
  1922  			fixedBits: 0x24008010,
  1923  			args:      Zm_T__Zn_T__PgZ__Pd_T__2,
  1924  		},
  1925  		// ZCMPGT #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1926  		{
  1927  			goOp:      AZCMPGT,
  1928  			fixedBits: 0x25000010,
  1929  			args:      cimm__Zn_T__PgZ__Pd_T__1,
  1930  		},
  1931  	},
  1932  	// ZCMPHI
  1933  	{
  1934  		// ZCMPHI <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1935  		{
  1936  			goOp:      AZCMPHI,
  1937  			fixedBits: 0x2400c010,
  1938  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  1939  		},
  1940  		// ZCMPHI <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1941  		{
  1942  			goOp:      AZCMPHI,
  1943  			fixedBits: 0x24000010,
  1944  			args:      Zm_T__Zn_T__PgZ__Pd_T__2,
  1945  		},
  1946  		// ZCMPHI #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1947  		{
  1948  			goOp:      AZCMPHI,
  1949  			fixedBits: 0x24200010,
  1950  			args:      cimm__Zn_T__PgZ__Pd_T__2,
  1951  		},
  1952  	},
  1953  	// ZCMPHS
  1954  	{
  1955  		// ZCMPHS <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1956  		{
  1957  			goOp:      AZCMPHS,
  1958  			fixedBits: 0x2400c000,
  1959  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  1960  		},
  1961  		// ZCMPHS <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1962  		{
  1963  			goOp:      AZCMPHS,
  1964  			fixedBits: 0x24000000,
  1965  			args:      Zm_T__Zn_T__PgZ__Pd_T__2,
  1966  		},
  1967  		// ZCMPHS #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1968  		{
  1969  			goOp:      AZCMPHS,
  1970  			fixedBits: 0x24200000,
  1971  			args:      cimm__Zn_T__PgZ__Pd_T__2,
  1972  		},
  1973  	},
  1974  	// ZCMPLE
  1975  	{
  1976  		// ZCMPLE <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1977  		{
  1978  			goOp:      AZCMPLE,
  1979  			fixedBits: 0x24006010,
  1980  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  1981  		},
  1982  		// ZCMPLE #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1983  		{
  1984  			goOp:      AZCMPLE,
  1985  			fixedBits: 0x25002010,
  1986  			args:      cimm__Zn_T__PgZ__Pd_T__1,
  1987  		},
  1988  	},
  1989  	// ZCMPLO
  1990  	{
  1991  		// ZCMPLO <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1992  		{
  1993  			goOp:      AZCMPLO,
  1994  			fixedBits: 0x2400e000,
  1995  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  1996  		},
  1997  		// ZCMPLO #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  1998  		{
  1999  			goOp:      AZCMPLO,
  2000  			fixedBits: 0x24202000,
  2001  			args:      cimm__Zn_T__PgZ__Pd_T__2,
  2002  		},
  2003  	},
  2004  	// ZCMPLS
  2005  	{
  2006  		// ZCMPLS <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2007  		{
  2008  			goOp:      AZCMPLS,
  2009  			fixedBits: 0x2400e010,
  2010  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  2011  		},
  2012  		// ZCMPLS #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2013  		{
  2014  			goOp:      AZCMPLS,
  2015  			fixedBits: 0x24202010,
  2016  			args:      cimm__Zn_T__PgZ__Pd_T__2,
  2017  		},
  2018  	},
  2019  	// ZCMPLT
  2020  	{
  2021  		// ZCMPLT <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2022  		{
  2023  			goOp:      AZCMPLT,
  2024  			fixedBits: 0x24006000,
  2025  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  2026  		},
  2027  		// ZCMPLT #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2028  		{
  2029  			goOp:      AZCMPLT,
  2030  			fixedBits: 0x25002000,
  2031  			args:      cimm__Zn_T__PgZ__Pd_T__1,
  2032  		},
  2033  	},
  2034  	// ZCMPNE
  2035  	{
  2036  		// ZCMPNE <Zm>.D, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2037  		{
  2038  			goOp:      AZCMPNE,
  2039  			fixedBits: 0x24002010,
  2040  			args:      Zm_D__Zn_T__PgZ__Pd_T,
  2041  		},
  2042  		// ZCMPNE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2043  		{
  2044  			goOp:      AZCMPNE,
  2045  			fixedBits: 0x2400a010,
  2046  			args:      Zm_T__Zn_T__PgZ__Pd_T__2,
  2047  		},
  2048  		// ZCMPNE #<imm>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2049  		{
  2050  			goOp:      AZCMPNE,
  2051  			fixedBits: 0x25008010,
  2052  			args:      cimm__Zn_T__PgZ__Pd_T__1,
  2053  		},
  2054  	},
  2055  	// ZCNOT
  2056  	{
  2057  		// ZCNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
  2058  		{
  2059  			goOp:      AZCNOT,
  2060  			fixedBits: 0x41ba000,
  2061  			args:      Zn_T__PgM__Zd_T__2,
  2062  		},
  2063  		// ZCNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  2064  		{
  2065  			goOp:      AZCNOT,
  2066  			fixedBits: 0x40ba000,
  2067  			args:      Zn_T__PgZ__Zd_T__2,
  2068  		},
  2069  	},
  2070  	// ZCNT
  2071  	{
  2072  		// ZCNT <Zn>.<T>, <Pg>/M, <Zd>.<T>
  2073  		{
  2074  			goOp:      AZCNT,
  2075  			fixedBits: 0x41aa000,
  2076  			args:      Zn_T__PgM__Zd_T__2,
  2077  		},
  2078  		// ZCNT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  2079  		{
  2080  			goOp:      AZCNT,
  2081  			fixedBits: 0x40aa000,
  2082  			args:      Zn_T__PgZ__Zd_T__2,
  2083  		},
  2084  	},
  2085  	// ZCOMPACT
  2086  	{
  2087  		// ZCOMPACT <Zn>.<T>, <Pg>, <Zd>.<T>
  2088  		{
  2089  			goOp:      AZCOMPACT,
  2090  			fixedBits: 0x5218000,
  2091  			args:      Zn_T__Pg__Zd_T__1,
  2092  		},
  2093  		// ZCOMPACT <Zn>.<T>, <Pg>, <Zd>.<T>
  2094  		{
  2095  			goOp:      AZCOMPACT,
  2096  			fixedBits: 0x5a18000,
  2097  			args:      Zn_T__Pg__Zd_T__2,
  2098  		},
  2099  	},
  2100  	// ZCPY
  2101  	{
  2102  		// ZCPY <R><n|SP>, <Pg>/M, <Zd>.<T>
  2103  		{
  2104  			goOp:      AZCPY,
  2105  			fixedBits: 0x5e8a000,
  2106  			args:      RnSP__PgM__Zd_T,
  2107  		},
  2108  		// ZCPY #<imm>{, <shift>}, <Pg>/M, <Zd>.<T>
  2109  		{
  2110  			goOp:      AZCPY,
  2111  			fixedBits: 0x5104000,
  2112  			args:      cimm__shift__PgM__Zd_T,
  2113  		},
  2114  		// ZCPY #<imm>{, <shift>}, <Pg>/Z, <Zd>.<T>
  2115  		{
  2116  			goOp:      AZCPY,
  2117  			fixedBits: 0x5100000,
  2118  			args:      cimm__shift__PgZ__Zd_T,
  2119  		},
  2120  	},
  2121  	// ZCPYB
  2122  	{
  2123  		// ZCPYB <V><n>, <Pg>/M, <Zd>.<T>
  2124  		{
  2125  			goOp:      AZCPYB,
  2126  			fixedBits: 0x5208000,
  2127  			args:      Vn__PgM__Zd_T,
  2128  		},
  2129  	},
  2130  	// ZCPYD
  2131  	{
  2132  		// ZCPYD <V><n>, <Pg>/M, <Zd>.<T>
  2133  		{
  2134  			goOp:      AZCPYD,
  2135  			fixedBits: 0x5e08000,
  2136  			args:      Vn__PgM__Zd_T,
  2137  		},
  2138  	},
  2139  	// ZCPYH
  2140  	{
  2141  		// ZCPYH <V><n>, <Pg>/M, <Zd>.<T>
  2142  		{
  2143  			goOp:      AZCPYH,
  2144  			fixedBits: 0x5608000,
  2145  			args:      Vn__PgM__Zd_T,
  2146  		},
  2147  	},
  2148  	// ZCPYS
  2149  	{
  2150  		// ZCPYS <V><n>, <Pg>/M, <Zd>.<T>
  2151  		{
  2152  			goOp:      AZCPYS,
  2153  			fixedBits: 0x5a08000,
  2154  			args:      Vn__PgM__Zd_T,
  2155  		},
  2156  	},
  2157  	// ZCPYW
  2158  	{
  2159  		// ZCPYW <R><n|SP>, <Pg>/M, <Zd>.<T>
  2160  		{
  2161  			goOp:      AZCPYW,
  2162  			fixedBits: 0x528a000,
  2163  			args:      RnSP__PgM__Zd_T,
  2164  		},
  2165  	},
  2166  	// ZDECP
  2167  	{
  2168  		// ZDECP <Pm>.<T>, <Zdn>.<T>
  2169  		{
  2170  			goOp:      AZDECP,
  2171  			fixedBits: 0x252d8000,
  2172  			args:      Pm_T__Zdn_T,
  2173  		},
  2174  	},
  2175  	// ZDUP
  2176  	{
  2177  		// ZDUP <R><n|SP>, <Zd>.<T>
  2178  		{
  2179  			goOp:      AZDUP,
  2180  			fixedBits: 0x5e03800,
  2181  			args:      RnSP__Zd_T,
  2182  		},
  2183  		// ZDUP <Zn>.<T>[<imm>], <Zd>.<T>
  2184  		{
  2185  			goOp:      AZDUP,
  2186  			fixedBits: 0x5202000,
  2187  			args:      Zn_T_imm___Zd_T__1,
  2188  		},
  2189  		// ZDUP #<imm>{, <shift>}, <Zd>.<T>
  2190  		{
  2191  			goOp:      AZDUP,
  2192  			fixedBits: 0x2538c000,
  2193  			args:      cimm__shift__Zd_T,
  2194  		},
  2195  	},
  2196  	// ZDUPM
  2197  	{
  2198  		// ZDUPM #<const>, <Zd>.<T>
  2199  		{
  2200  			goOp:      AZDUPM,
  2201  			fixedBits: 0x5c00000,
  2202  			args:      cconst__Zd_T__1,
  2203  		},
  2204  	},
  2205  	// ZDUPQ
  2206  	{
  2207  		// ZDUPQ <Zn>.<T>[<imm>], <Zd>.<T>
  2208  		{
  2209  			goOp:      AZDUPQ,
  2210  			fixedBits: 0x5202400,
  2211  			args:      Zn_T_imm___Zd_T__2,
  2212  		},
  2213  	},
  2214  	// ZDUPW
  2215  	{
  2216  		// ZDUPW <R><n|SP>, <Zd>.<T>
  2217  		{
  2218  			goOp:      AZDUPW,
  2219  			fixedBits: 0x5203800,
  2220  			args:      RnSP__Zd_T,
  2221  		},
  2222  	},
  2223  	// ZEOR
  2224  	{
  2225  		// ZEOR <Zm>.D, <Zn>.D, <Zd>.D
  2226  		{
  2227  			goOp:      AZEOR,
  2228  			fixedBits: 0x4a03000,
  2229  			args:      Zm_D__Zn_D__Zd_D,
  2230  		},
  2231  		// ZEOR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2232  		{
  2233  			goOp:      AZEOR,
  2234  			fixedBits: 0x4190000,
  2235  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  2236  		},
  2237  		// ZEOR #<const>, <Zdn>.<T>, <Zdn>.<T>
  2238  		{
  2239  			goOp:      AZEOR,
  2240  			fixedBits: 0x5400000,
  2241  			args:      cconst__Zdn_T__Zdn_T,
  2242  		},
  2243  	},
  2244  	// ZEOR3
  2245  	{
  2246  		// ZEOR3 <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
  2247  		{
  2248  			goOp:      AZEOR3,
  2249  			fixedBits: 0x4203800,
  2250  			args:      Zk_D__Zm_D__Zdn_D__Zdn_D,
  2251  		},
  2252  	},
  2253  	// ZEORBT
  2254  	{
  2255  		// ZEORBT <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  2256  		{
  2257  			goOp:      AZEORBT,
  2258  			fixedBits: 0x45009000,
  2259  			args:      Zm_T__Zn_T__Zd_T__1,
  2260  		},
  2261  	},
  2262  	// ZEORQV
  2263  	{
  2264  		// ZEORQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  2265  		{
  2266  			goOp:      AZEORQV,
  2267  			fixedBits: 0x41d2000,
  2268  			args:      Zn_Tb__Pg__Vd_T__1,
  2269  		},
  2270  	},
  2271  	// ZEORTB
  2272  	{
  2273  		// ZEORTB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  2274  		{
  2275  			goOp:      AZEORTB,
  2276  			fixedBits: 0x45009400,
  2277  			args:      Zm_T__Zn_T__Zd_T__1,
  2278  		},
  2279  	},
  2280  	// ZEORVB
  2281  	{
  2282  		// ZEORVB <Zn>.<T>, <Pg>, <V><d>
  2283  		{
  2284  			goOp:      AZEORVB,
  2285  			fixedBits: 0x4192000,
  2286  			args:      Zn_T__Pg__Vd__1,
  2287  		},
  2288  	},
  2289  	// ZEORVD
  2290  	{
  2291  		// ZEORVD <Zn>.<T>, <Pg>, <V><d>
  2292  		{
  2293  			goOp:      AZEORVD,
  2294  			fixedBits: 0x4d92000,
  2295  			args:      Zn_T__Pg__Vd__1,
  2296  		},
  2297  	},
  2298  	// ZEORVH
  2299  	{
  2300  		// ZEORVH <Zn>.<T>, <Pg>, <V><d>
  2301  		{
  2302  			goOp:      AZEORVH,
  2303  			fixedBits: 0x4592000,
  2304  			args:      Zn_T__Pg__Vd__1,
  2305  		},
  2306  	},
  2307  	// ZEORVS
  2308  	{
  2309  		// ZEORVS <Zn>.<T>, <Pg>, <V><d>
  2310  		{
  2311  			goOp:      AZEORVS,
  2312  			fixedBits: 0x4992000,
  2313  			args:      Zn_T__Pg__Vd__1,
  2314  		},
  2315  	},
  2316  	// ZEXPAND
  2317  	{
  2318  		// ZEXPAND <Zn>.<T>, <Pg>, <Zd>.<T>
  2319  		{
  2320  			goOp:      AZEXPAND,
  2321  			fixedBits: 0x5318000,
  2322  			args:      Zn_T__Pg__Zd_T__3,
  2323  		},
  2324  	},
  2325  	// ZEXT
  2326  	{
  2327  		// ZEXT #<imm>, <Zm>.B, <Zdn>.B, <Zdn>.B
  2328  		{
  2329  			goOp:      AZEXT,
  2330  			fixedBits: 0x5200000,
  2331  			args:      cimm__Zm_B__Zdn_B__Zdn_B__1,
  2332  		},
  2333  		// ZEXT #<imm>, { <Zn1>.B, <Zn2>.B }, <Zd>.B
  2334  		{
  2335  			goOp:      AZEXT,
  2336  			fixedBits: 0x5600000,
  2337  			args:      cimm___Zn1_B__Zn2_B___Zd_B,
  2338  		},
  2339  	},
  2340  	// ZEXTQ
  2341  	{
  2342  		// ZEXTQ #<imm>, <Zm>.B, <Zdn>.B, <Zdn>.B
  2343  		{
  2344  			goOp:      AZEXTQ,
  2345  			fixedBits: 0x5602400,
  2346  			args:      cimm__Zm_B__Zdn_B__Zdn_B__2,
  2347  		},
  2348  	},
  2349  	// ZF1CVT
  2350  	{
  2351  		// ZF1CVT <Zn>.B, <Zd>.H
  2352  		{
  2353  			goOp:      AZF1CVT,
  2354  			fixedBits: 0x65083000,
  2355  			args:      Zn_B__Zd_H,
  2356  		},
  2357  	},
  2358  	// ZF1CVTLT
  2359  	{
  2360  		// ZF1CVTLT <Zn>.B, <Zd>.H
  2361  		{
  2362  			goOp:      AZF1CVTLT,
  2363  			fixedBits: 0x65093000,
  2364  			args:      Zn_B__Zd_H,
  2365  		},
  2366  	},
  2367  	// ZF2CVT
  2368  	{
  2369  		// ZF2CVT <Zn>.B, <Zd>.H
  2370  		{
  2371  			goOp:      AZF2CVT,
  2372  			fixedBits: 0x65083400,
  2373  			args:      Zn_B__Zd_H,
  2374  		},
  2375  	},
  2376  	// ZF2CVTLT
  2377  	{
  2378  		// ZF2CVTLT <Zn>.B, <Zd>.H
  2379  		{
  2380  			goOp:      AZF2CVTLT,
  2381  			fixedBits: 0x65093400,
  2382  			args:      Zn_B__Zd_H,
  2383  		},
  2384  	},
  2385  	// ZFABD
  2386  	{
  2387  		// ZFABD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2388  		{
  2389  			goOp:      AZFABD,
  2390  			fixedBits: 0x65088000,
  2391  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  2392  		},
  2393  	},
  2394  	// ZFABS
  2395  	{
  2396  		// ZFABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
  2397  		{
  2398  			goOp:      AZFABS,
  2399  			fixedBits: 0x41ca000,
  2400  			args:      Zn_T__PgM__Zd_T__1,
  2401  		},
  2402  		// ZFABS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  2403  		{
  2404  			goOp:      AZFABS,
  2405  			fixedBits: 0x40ca000,
  2406  			args:      Zn_T__PgZ__Zd_T__1,
  2407  		},
  2408  	},
  2409  	// ZFACGE
  2410  	{
  2411  		// ZFACGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2412  		{
  2413  			goOp:      AZFACGE,
  2414  			fixedBits: 0x6500c010,
  2415  			args:      Zm_T__Zn_T__PgZ__Pd_T__1,
  2416  		},
  2417  	},
  2418  	// ZFACGT
  2419  	{
  2420  		// ZFACGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2421  		{
  2422  			goOp:      AZFACGT,
  2423  			fixedBits: 0x6500e010,
  2424  			args:      Zm_T__Zn_T__PgZ__Pd_T__1,
  2425  		},
  2426  	},
  2427  	// ZFADD
  2428  	{
  2429  		// ZFADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2430  		{
  2431  			goOp:      AZFADD,
  2432  			fixedBits: 0x65008000,
  2433  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  2434  		},
  2435  		// ZFADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  2436  		{
  2437  			goOp:      AZFADD,
  2438  			fixedBits: 0x65000000,
  2439  			args:      Zm_T__Zn_T__Zd_T__2,
  2440  		},
  2441  		// ZFADD <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2442  		{
  2443  			goOp:      AZFADD,
  2444  			fixedBits: 0x65188000,
  2445  			args:      const__Zdn_T__PgM__Zdn_T__2,
  2446  		},
  2447  	},
  2448  	// ZFADDAD
  2449  	{
  2450  		// ZFADDAD <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  2451  		{
  2452  			goOp:      AZFADDAD,
  2453  			fixedBits: 0x65d82000,
  2454  			args:      Zm_T__Vdn__Pg__Vdn__2,
  2455  		},
  2456  	},
  2457  	// ZFADDAH
  2458  	{
  2459  		// ZFADDAH <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  2460  		{
  2461  			goOp:      AZFADDAH,
  2462  			fixedBits: 0x65582000,
  2463  			args:      Zm_T__Vdn__Pg__Vdn__2,
  2464  		},
  2465  	},
  2466  	// ZFADDAS
  2467  	{
  2468  		// ZFADDAS <Zm>.<T>, <V><dn>, <Pg>, <V><dn>
  2469  		{
  2470  			goOp:      AZFADDAS,
  2471  			fixedBits: 0x65982000,
  2472  			args:      Zm_T__Vdn__Pg__Vdn__2,
  2473  		},
  2474  	},
  2475  	// ZFADDP
  2476  	{
  2477  		// ZFADDP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2478  		{
  2479  			goOp:      AZFADDP,
  2480  			fixedBits: 0x64108000,
  2481  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  2482  		},
  2483  	},
  2484  	// ZFADDQV
  2485  	{
  2486  		// ZFADDQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  2487  		{
  2488  			goOp:      AZFADDQV,
  2489  			fixedBits: 0x6410a000,
  2490  			args:      Zn_Tb__Pg__Vd_T__2,
  2491  		},
  2492  	},
  2493  	// ZFADDVD
  2494  	{
  2495  		// ZFADDVD <Zn>.<T>, <Pg>, <V><d>
  2496  		{
  2497  			goOp:      AZFADDVD,
  2498  			fixedBits: 0x65c02000,
  2499  			args:      Zn_T__Pg__Vd__2,
  2500  		},
  2501  	},
  2502  	// ZFADDVH
  2503  	{
  2504  		// ZFADDVH <Zn>.<T>, <Pg>, <V><d>
  2505  		{
  2506  			goOp:      AZFADDVH,
  2507  			fixedBits: 0x65402000,
  2508  			args:      Zn_T__Pg__Vd__2,
  2509  		},
  2510  	},
  2511  	// ZFADDVS
  2512  	{
  2513  		// ZFADDVS <Zn>.<T>, <Pg>, <V><d>
  2514  		{
  2515  			goOp:      AZFADDVS,
  2516  			fixedBits: 0x65802000,
  2517  			args:      Zn_T__Pg__Vd__2,
  2518  		},
  2519  	},
  2520  	// ZFAMAX
  2521  	{
  2522  		// ZFAMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2523  		{
  2524  			goOp:      AZFAMAX,
  2525  			fixedBits: 0x650e8000,
  2526  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  2527  		},
  2528  	},
  2529  	// ZFAMIN
  2530  	{
  2531  		// ZFAMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2532  		{
  2533  			goOp:      AZFAMIN,
  2534  			fixedBits: 0x650f8000,
  2535  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  2536  		},
  2537  	},
  2538  	// ZFCADD
  2539  	{
  2540  		// ZFCADD <const>, <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  2541  		{
  2542  			goOp:      AZFCADD,
  2543  			fixedBits: 0x64008000,
  2544  			args:      const__Zm_T__Zdn_T__PgM__Zdn_T,
  2545  		},
  2546  	},
  2547  	// ZFCLAMP
  2548  	{
  2549  		// ZFCLAMP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  2550  		{
  2551  			goOp:      AZFCLAMP,
  2552  			fixedBits: 0x64202400,
  2553  			args:      Zm_T__Zn_T__Zd_T__2,
  2554  		},
  2555  	},
  2556  	// ZFCMEQ
  2557  	{
  2558  		// ZFCMEQ <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2559  		{
  2560  			goOp:      AZFCMEQ,
  2561  			fixedBits: 0x65006000,
  2562  			args:      Zm_T__Zn_T__PgZ__Pd_T__1,
  2563  		},
  2564  		// ZFCMEQ #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2565  		{
  2566  			goOp:      AZFCMEQ,
  2567  			fixedBits: 0x65122000,
  2568  			args:      c0_0__Zn_T__PgZ__Pd_T,
  2569  		},
  2570  	},
  2571  	// ZFCMGE
  2572  	{
  2573  		// ZFCMGE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2574  		{
  2575  			goOp:      AZFCMGE,
  2576  			fixedBits: 0x65004000,
  2577  			args:      Zm_T__Zn_T__PgZ__Pd_T__1,
  2578  		},
  2579  		// ZFCMGE #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2580  		{
  2581  			goOp:      AZFCMGE,
  2582  			fixedBits: 0x65102000,
  2583  			args:      c0_0__Zn_T__PgZ__Pd_T,
  2584  		},
  2585  	},
  2586  	// ZFCMGT
  2587  	{
  2588  		// ZFCMGT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2589  		{
  2590  			goOp:      AZFCMGT,
  2591  			fixedBits: 0x65004010,
  2592  			args:      Zm_T__Zn_T__PgZ__Pd_T__1,
  2593  		},
  2594  		// ZFCMGT #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2595  		{
  2596  			goOp:      AZFCMGT,
  2597  			fixedBits: 0x65102010,
  2598  			args:      c0_0__Zn_T__PgZ__Pd_T,
  2599  		},
  2600  	},
  2601  	// ZFCMLA
  2602  	{
  2603  		// ZFCMLA <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  2604  		{
  2605  			goOp:      AZFCMLA,
  2606  			fixedBits: 0x64a01000,
  2607  			args:      const__Zm_H_imm___Zn_H__Zda_H__2,
  2608  		},
  2609  		// ZFCMLA <const>, <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  2610  		{
  2611  			goOp:      AZFCMLA,
  2612  			fixedBits: 0x64e01000,
  2613  			args:      const__Zm_S_imm___Zn_S__Zda_S__2,
  2614  		},
  2615  		// ZFCMLA <const>, <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
  2616  		{
  2617  			goOp:      AZFCMLA,
  2618  			fixedBits: 0x64000000,
  2619  			args:      const__Zm_T__Zn_T__PgM__Zda_T,
  2620  		},
  2621  	},
  2622  	// ZFCMLE
  2623  	{
  2624  		// ZFCMLE #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2625  		{
  2626  			goOp:      AZFCMLE,
  2627  			fixedBits: 0x65112010,
  2628  			args:      c0_0__Zn_T__PgZ__Pd_T,
  2629  		},
  2630  	},
  2631  	// ZFCMLT
  2632  	{
  2633  		// ZFCMLT #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2634  		{
  2635  			goOp:      AZFCMLT,
  2636  			fixedBits: 0x65112000,
  2637  			args:      c0_0__Zn_T__PgZ__Pd_T,
  2638  		},
  2639  	},
  2640  	// ZFCMNE
  2641  	{
  2642  		// ZFCMNE <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2643  		{
  2644  			goOp:      AZFCMNE,
  2645  			fixedBits: 0x65006010,
  2646  			args:      Zm_T__Zn_T__PgZ__Pd_T__1,
  2647  		},
  2648  		// ZFCMNE #0.0, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2649  		{
  2650  			goOp:      AZFCMNE,
  2651  			fixedBits: 0x65132000,
  2652  			args:      c0_0__Zn_T__PgZ__Pd_T,
  2653  		},
  2654  	},
  2655  	// ZFCMUO
  2656  	{
  2657  		// ZFCMUO <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  2658  		{
  2659  			goOp:      AZFCMUO,
  2660  			fixedBits: 0x6500c000,
  2661  			args:      Zm_T__Zn_T__PgZ__Pd_T__1,
  2662  		},
  2663  	},
  2664  	// ZFCPY
  2665  	{
  2666  		// ZFCPY #<const>, <Pg>/M, <Zd>.<T>
  2667  		{
  2668  			goOp:      AZFCPY,
  2669  			fixedBits: 0x510c000,
  2670  			args:      cconst__PgM__Zd_T,
  2671  		},
  2672  	},
  2673  	// ZFCVT
  2674  	{
  2675  		// ZFCVT <Zn>.D, <Pg>/M, <Zd>.H
  2676  		{
  2677  			goOp:      AZFCVT,
  2678  			fixedBits: 0x65c8a000,
  2679  			args:      Zn_D__PgM__Zd_H,
  2680  		},
  2681  		// ZFCVT <Zn>.D, <Pg>/M, <Zd>.S
  2682  		{
  2683  			goOp:      AZFCVT,
  2684  			fixedBits: 0x65caa000,
  2685  			args:      Zn_D__PgM__Zd_S,
  2686  		},
  2687  		// ZFCVT <Zn>.D, <Pg>/Z, <Zd>.H
  2688  		{
  2689  			goOp:      AZFCVT,
  2690  			fixedBits: 0x64da8000,
  2691  			args:      Zn_D__PgZ__Zd_H,
  2692  		},
  2693  		// ZFCVT <Zn>.D, <Pg>/Z, <Zd>.S
  2694  		{
  2695  			goOp:      AZFCVT,
  2696  			fixedBits: 0x64dac000,
  2697  			args:      Zn_D__PgZ__Zd_S,
  2698  		},
  2699  		// ZFCVT <Zn>.H, <Pg>/M, <Zd>.D
  2700  		{
  2701  			goOp:      AZFCVT,
  2702  			fixedBits: 0x65c9a000,
  2703  			args:      Zn_H__PgM__Zd_D,
  2704  		},
  2705  		// ZFCVT <Zn>.H, <Pg>/M, <Zd>.S
  2706  		{
  2707  			goOp:      AZFCVT,
  2708  			fixedBits: 0x6589a000,
  2709  			args:      Zn_H__PgM__Zd_S,
  2710  		},
  2711  		// ZFCVT <Zn>.H, <Pg>/Z, <Zd>.D
  2712  		{
  2713  			goOp:      AZFCVT,
  2714  			fixedBits: 0x64daa000,
  2715  			args:      Zn_H__PgZ__Zd_D,
  2716  		},
  2717  		// ZFCVT <Zn>.H, <Pg>/Z, <Zd>.S
  2718  		{
  2719  			goOp:      AZFCVT,
  2720  			fixedBits: 0x649aa000,
  2721  			args:      Zn_H__PgZ__Zd_S,
  2722  		},
  2723  		// ZFCVT <Zn>.S, <Pg>/M, <Zd>.D
  2724  		{
  2725  			goOp:      AZFCVT,
  2726  			fixedBits: 0x65cba000,
  2727  			args:      Zn_S__PgM__Zd_D,
  2728  		},
  2729  		// ZFCVT <Zn>.S, <Pg>/M, <Zd>.H
  2730  		{
  2731  			goOp:      AZFCVT,
  2732  			fixedBits: 0x6588a000,
  2733  			args:      Zn_S__PgM__Zd_H,
  2734  		},
  2735  		// ZFCVT <Zn>.S, <Pg>/Z, <Zd>.D
  2736  		{
  2737  			goOp:      AZFCVT,
  2738  			fixedBits: 0x64dae000,
  2739  			args:      Zn_S__PgZ__Zd_D,
  2740  		},
  2741  		// ZFCVT <Zn>.S, <Pg>/Z, <Zd>.H
  2742  		{
  2743  			goOp:      AZFCVT,
  2744  			fixedBits: 0x649a8000,
  2745  			args:      Zn_S__PgZ__Zd_H,
  2746  		},
  2747  	},
  2748  	// ZFCVTLT
  2749  	{
  2750  		// ZFCVTLT <Zn>.H, <Pg>/M, <Zd>.S
  2751  		{
  2752  			goOp:      AZFCVTLT,
  2753  			fixedBits: 0x6489a000,
  2754  			args:      Zn_H__PgM__Zd_S,
  2755  		},
  2756  		// ZFCVTLT <Zn>.H, <Pg>/Z, <Zd>.S
  2757  		{
  2758  			goOp:      AZFCVTLT,
  2759  			fixedBits: 0x6481a000,
  2760  			args:      Zn_H__PgZ__Zd_S,
  2761  		},
  2762  		// ZFCVTLT <Zn>.S, <Pg>/M, <Zd>.D
  2763  		{
  2764  			goOp:      AZFCVTLT,
  2765  			fixedBits: 0x64cba000,
  2766  			args:      Zn_S__PgM__Zd_D,
  2767  		},
  2768  		// ZFCVTLT <Zn>.S, <Pg>/Z, <Zd>.D
  2769  		{
  2770  			goOp:      AZFCVTLT,
  2771  			fixedBits: 0x64c3a000,
  2772  			args:      Zn_S__PgZ__Zd_D,
  2773  		},
  2774  	},
  2775  	// ZFCVTN
  2776  	{
  2777  		// ZFCVTN { <Zn1>.H-<Zn2>.H }, <Zd>.B
  2778  		{
  2779  			goOp:      AZFCVTN,
  2780  			fixedBits: 0x650a3000,
  2781  			args:      Zn1_H_Zn2_H___Zd_B,
  2782  		},
  2783  	},
  2784  	// ZFCVTNB
  2785  	{
  2786  		// ZFCVTNB { <Zn1>.S-<Zn2>.S }, <Zd>.B
  2787  		{
  2788  			goOp:      AZFCVTNB,
  2789  			fixedBits: 0x650a3400,
  2790  			args:      Zn1_S_Zn2_S___Zd_B,
  2791  		},
  2792  	},
  2793  	// ZFCVTNT
  2794  	{
  2795  		// ZFCVTNT <Zn>.D, <Pg>/M, <Zd>.S
  2796  		{
  2797  			goOp:      AZFCVTNT,
  2798  			fixedBits: 0x64caa000,
  2799  			args:      Zn_D__PgM__Zd_S,
  2800  		},
  2801  		// ZFCVTNT <Zn>.D, <Pg>/Z, <Zd>.S
  2802  		{
  2803  			goOp:      AZFCVTNT,
  2804  			fixedBits: 0x64c2a000,
  2805  			args:      Zn_D__PgZ__Zd_S,
  2806  		},
  2807  		// ZFCVTNT <Zn>.S, <Pg>/M, <Zd>.H
  2808  		{
  2809  			goOp:      AZFCVTNT,
  2810  			fixedBits: 0x6488a000,
  2811  			args:      Zn_S__PgM__Zd_H,
  2812  		},
  2813  		// ZFCVTNT <Zn>.S, <Pg>/Z, <Zd>.H
  2814  		{
  2815  			goOp:      AZFCVTNT,
  2816  			fixedBits: 0x6480a000,
  2817  			args:      Zn_S__PgZ__Zd_H,
  2818  		},
  2819  		// ZFCVTNT { <Zn1>.S-<Zn2>.S }, <Zd>.B
  2820  		{
  2821  			goOp:      AZFCVTNT,
  2822  			fixedBits: 0x650a3c00,
  2823  			args:      Zn1_S_Zn2_S___Zd_B,
  2824  		},
  2825  	},
  2826  	// ZFCVTX
  2827  	{
  2828  		// ZFCVTX <Zn>.D, <Pg>/M, <Zd>.S
  2829  		{
  2830  			goOp:      AZFCVTX,
  2831  			fixedBits: 0x650aa000,
  2832  			args:      Zn_D__PgM__Zd_S,
  2833  		},
  2834  		// ZFCVTX <Zn>.D, <Pg>/Z, <Zd>.S
  2835  		{
  2836  			goOp:      AZFCVTX,
  2837  			fixedBits: 0x641ac000,
  2838  			args:      Zn_D__PgZ__Zd_S,
  2839  		},
  2840  	},
  2841  	// ZFCVTXNT
  2842  	{
  2843  		// ZFCVTXNT <Zn>.D, <Pg>/M, <Zd>.S
  2844  		{
  2845  			goOp:      AZFCVTXNT,
  2846  			fixedBits: 0x640aa000,
  2847  			args:      Zn_D__PgM__Zd_S,
  2848  		},
  2849  		// ZFCVTXNT <Zn>.D, <Pg>/Z, <Zd>.S
  2850  		{
  2851  			goOp:      AZFCVTXNT,
  2852  			fixedBits: 0x6402a000,
  2853  			args:      Zn_D__PgZ__Zd_S,
  2854  		},
  2855  	},
  2856  	// ZFCVTZS
  2857  	{
  2858  		// ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.D
  2859  		{
  2860  			goOp:      AZFCVTZS,
  2861  			fixedBits: 0x65dea000,
  2862  			args:      Zn_D__PgM__Zd_D,
  2863  		},
  2864  		// ZFCVTZS <Zn>.D, <Pg>/M, <Zd>.S
  2865  		{
  2866  			goOp:      AZFCVTZS,
  2867  			fixedBits: 0x65d8a000,
  2868  			args:      Zn_D__PgM__Zd_S,
  2869  		},
  2870  		// ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.D
  2871  		{
  2872  			goOp:      AZFCVTZS,
  2873  			fixedBits: 0x64dfc000,
  2874  			args:      Zn_D__PgZ__Zd_D,
  2875  		},
  2876  		// ZFCVTZS <Zn>.D, <Pg>/Z, <Zd>.S
  2877  		{
  2878  			goOp:      AZFCVTZS,
  2879  			fixedBits: 0x64de8000,
  2880  			args:      Zn_D__PgZ__Zd_S,
  2881  		},
  2882  		// ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.D
  2883  		{
  2884  			goOp:      AZFCVTZS,
  2885  			fixedBits: 0x655ea000,
  2886  			args:      Zn_H__PgM__Zd_D,
  2887  		},
  2888  		// ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.H
  2889  		{
  2890  			goOp:      AZFCVTZS,
  2891  			fixedBits: 0x655aa000,
  2892  			args:      Zn_H__PgM__Zd_H,
  2893  		},
  2894  		// ZFCVTZS <Zn>.H, <Pg>/M, <Zd>.S
  2895  		{
  2896  			goOp:      AZFCVTZS,
  2897  			fixedBits: 0x655ca000,
  2898  			args:      Zn_H__PgM__Zd_S,
  2899  		},
  2900  		// ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.D
  2901  		{
  2902  			goOp:      AZFCVTZS,
  2903  			fixedBits: 0x645fc000,
  2904  			args:      Zn_H__PgZ__Zd_D,
  2905  		},
  2906  		// ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.H
  2907  		{
  2908  			goOp:      AZFCVTZS,
  2909  			fixedBits: 0x645ec000,
  2910  			args:      Zn_H__PgZ__Zd_H,
  2911  		},
  2912  		// ZFCVTZS <Zn>.H, <Pg>/Z, <Zd>.S
  2913  		{
  2914  			goOp:      AZFCVTZS,
  2915  			fixedBits: 0x645f8000,
  2916  			args:      Zn_H__PgZ__Zd_S,
  2917  		},
  2918  		// ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.D
  2919  		{
  2920  			goOp:      AZFCVTZS,
  2921  			fixedBits: 0x65dca000,
  2922  			args:      Zn_S__PgM__Zd_D,
  2923  		},
  2924  		// ZFCVTZS <Zn>.S, <Pg>/M, <Zd>.S
  2925  		{
  2926  			goOp:      AZFCVTZS,
  2927  			fixedBits: 0x659ca000,
  2928  			args:      Zn_S__PgM__Zd_S,
  2929  		},
  2930  		// ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.D
  2931  		{
  2932  			goOp:      AZFCVTZS,
  2933  			fixedBits: 0x64df8000,
  2934  			args:      Zn_S__PgZ__Zd_D,
  2935  		},
  2936  		// ZFCVTZS <Zn>.S, <Pg>/Z, <Zd>.S
  2937  		{
  2938  			goOp:      AZFCVTZS,
  2939  			fixedBits: 0x649f8000,
  2940  			args:      Zn_S__PgZ__Zd_S,
  2941  		},
  2942  	},
  2943  	// ZFCVTZSN
  2944  	{
  2945  		// ZFCVTZSN { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zd>.<T>
  2946  		{
  2947  			goOp:      AZFCVTZSN,
  2948  			fixedBits: 0x650d3000,
  2949  			args:      Zn1_Tb_Zn2_Tb___Zd_T,
  2950  		},
  2951  	},
  2952  	// ZFCVTZU
  2953  	{
  2954  		// ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.D
  2955  		{
  2956  			goOp:      AZFCVTZU,
  2957  			fixedBits: 0x65dfa000,
  2958  			args:      Zn_D__PgM__Zd_D,
  2959  		},
  2960  		// ZFCVTZU <Zn>.D, <Pg>/M, <Zd>.S
  2961  		{
  2962  			goOp:      AZFCVTZU,
  2963  			fixedBits: 0x65d9a000,
  2964  			args:      Zn_D__PgM__Zd_S,
  2965  		},
  2966  		// ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.D
  2967  		{
  2968  			goOp:      AZFCVTZU,
  2969  			fixedBits: 0x64dfe000,
  2970  			args:      Zn_D__PgZ__Zd_D,
  2971  		},
  2972  		// ZFCVTZU <Zn>.D, <Pg>/Z, <Zd>.S
  2973  		{
  2974  			goOp:      AZFCVTZU,
  2975  			fixedBits: 0x64dea000,
  2976  			args:      Zn_D__PgZ__Zd_S,
  2977  		},
  2978  		// ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.D
  2979  		{
  2980  			goOp:      AZFCVTZU,
  2981  			fixedBits: 0x655fa000,
  2982  			args:      Zn_H__PgM__Zd_D,
  2983  		},
  2984  		// ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.H
  2985  		{
  2986  			goOp:      AZFCVTZU,
  2987  			fixedBits: 0x655ba000,
  2988  			args:      Zn_H__PgM__Zd_H,
  2989  		},
  2990  		// ZFCVTZU <Zn>.H, <Pg>/M, <Zd>.S
  2991  		{
  2992  			goOp:      AZFCVTZU,
  2993  			fixedBits: 0x655da000,
  2994  			args:      Zn_H__PgM__Zd_S,
  2995  		},
  2996  		// ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.D
  2997  		{
  2998  			goOp:      AZFCVTZU,
  2999  			fixedBits: 0x645fe000,
  3000  			args:      Zn_H__PgZ__Zd_D,
  3001  		},
  3002  		// ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.H
  3003  		{
  3004  			goOp:      AZFCVTZU,
  3005  			fixedBits: 0x645ee000,
  3006  			args:      Zn_H__PgZ__Zd_H,
  3007  		},
  3008  		// ZFCVTZU <Zn>.H, <Pg>/Z, <Zd>.S
  3009  		{
  3010  			goOp:      AZFCVTZU,
  3011  			fixedBits: 0x645fa000,
  3012  			args:      Zn_H__PgZ__Zd_S,
  3013  		},
  3014  		// ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.D
  3015  		{
  3016  			goOp:      AZFCVTZU,
  3017  			fixedBits: 0x65dda000,
  3018  			args:      Zn_S__PgM__Zd_D,
  3019  		},
  3020  		// ZFCVTZU <Zn>.S, <Pg>/M, <Zd>.S
  3021  		{
  3022  			goOp:      AZFCVTZU,
  3023  			fixedBits: 0x659da000,
  3024  			args:      Zn_S__PgM__Zd_S,
  3025  		},
  3026  		// ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.D
  3027  		{
  3028  			goOp:      AZFCVTZU,
  3029  			fixedBits: 0x64dfa000,
  3030  			args:      Zn_S__PgZ__Zd_D,
  3031  		},
  3032  		// ZFCVTZU <Zn>.S, <Pg>/Z, <Zd>.S
  3033  		{
  3034  			goOp:      AZFCVTZU,
  3035  			fixedBits: 0x649fa000,
  3036  			args:      Zn_S__PgZ__Zd_S,
  3037  		},
  3038  	},
  3039  	// ZFCVTZUN
  3040  	{
  3041  		// ZFCVTZUN { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zd>.<T>
  3042  		{
  3043  			goOp:      AZFCVTZUN,
  3044  			fixedBits: 0x650d3400,
  3045  			args:      Zn1_Tb_Zn2_Tb___Zd_T,
  3046  		},
  3047  	},
  3048  	// ZFDIV
  3049  	{
  3050  		// ZFDIV <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3051  		{
  3052  			goOp:      AZFDIV,
  3053  			fixedBits: 0x650d8000,
  3054  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  3055  		},
  3056  	},
  3057  	// ZFDIVR
  3058  	{
  3059  		// ZFDIVR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3060  		{
  3061  			goOp:      AZFDIVR,
  3062  			fixedBits: 0x650c8000,
  3063  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  3064  		},
  3065  	},
  3066  	// ZFDOT
  3067  	{
  3068  		// ZFDOT <Zm>.B, <Zn>.B, <Zda>.H
  3069  		{
  3070  			goOp:      AZFDOT,
  3071  			fixedBits: 0x64208400,
  3072  			args:      Zm_B__Zn_B__Zda_H,
  3073  		},
  3074  		// ZFDOT <Zm>.B, <Zn>.B, <Zda>.S
  3075  		{
  3076  			goOp:      AZFDOT,
  3077  			fixedBits: 0x64608400,
  3078  			args:      Zm_B__Zn_B__Zda_S,
  3079  		},
  3080  		// ZFDOT <Zm>.H, <Zn>.H, <Zda>.S
  3081  		{
  3082  			goOp:      AZFDOT,
  3083  			fixedBits: 0x64208000,
  3084  			args:      Zm_H__Zn_H__Zda_S,
  3085  		},
  3086  		// ZFDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H
  3087  		{
  3088  			goOp:      AZFDOT,
  3089  			fixedBits: 0x64204400,
  3090  			args:      Zm_B_imm___Zn_B__Zda_H__3,
  3091  		},
  3092  		// ZFDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  3093  		{
  3094  			goOp:      AZFDOT,
  3095  			fixedBits: 0x64604400,
  3096  			args:      Zm_B_imm___Zn_B__Zda_S__2,
  3097  		},
  3098  		// ZFDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  3099  		{
  3100  			goOp:      AZFDOT,
  3101  			fixedBits: 0x64204000,
  3102  			args:      Zm_H_imm___Zn_H__Zda_S__3,
  3103  		},
  3104  	},
  3105  	// ZFDUP
  3106  	{
  3107  		// ZFDUP #<const>, <Zd>.<T>
  3108  		{
  3109  			goOp:      AZFDUP,
  3110  			fixedBits: 0x2539c000,
  3111  			args:      cconst__Zd_T__2,
  3112  		},
  3113  	},
  3114  	// ZFEXPA
  3115  	{
  3116  		// ZFEXPA <Zn>.<T>, <Zd>.<T>
  3117  		{
  3118  			goOp:      AZFEXPA,
  3119  			fixedBits: 0x420b800,
  3120  			args:      Zn_T__Zd_T__1,
  3121  		},
  3122  	},
  3123  	// ZFLOGB
  3124  	{
  3125  		// ZFLOGB <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3126  		{
  3127  			goOp:      AZFLOGB,
  3128  			fixedBits: 0x6518a000,
  3129  			args:      Zn_T__PgM__Zd_T__6,
  3130  		},
  3131  		// ZFLOGB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3132  		{
  3133  			goOp:      AZFLOGB,
  3134  			fixedBits: 0x641e8000,
  3135  			args:      Zn_T__PgZ__Zd_T__6,
  3136  		},
  3137  	},
  3138  	// ZFMAD
  3139  	{
  3140  		// ZFMAD <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
  3141  		{
  3142  			goOp:      AZFMAD,
  3143  			fixedBits: 0x65208000,
  3144  			args:      Za_T__Zm_T__PgM__Zdn_T__1,
  3145  		},
  3146  	},
  3147  	// ZFMAX
  3148  	{
  3149  		// ZFMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3150  		{
  3151  			goOp:      AZFMAX,
  3152  			fixedBits: 0x65068000,
  3153  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  3154  		},
  3155  		// ZFMAX <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3156  		{
  3157  			goOp:      AZFMAX,
  3158  			fixedBits: 0x651e8000,
  3159  			args:      const__Zdn_T__PgM__Zdn_T__1,
  3160  		},
  3161  	},
  3162  	// ZFMAXNM
  3163  	{
  3164  		// ZFMAXNM <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3165  		{
  3166  			goOp:      AZFMAXNM,
  3167  			fixedBits: 0x65048000,
  3168  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  3169  		},
  3170  		// ZFMAXNM <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3171  		{
  3172  			goOp:      AZFMAXNM,
  3173  			fixedBits: 0x651c8000,
  3174  			args:      const__Zdn_T__PgM__Zdn_T__1,
  3175  		},
  3176  	},
  3177  	// ZFMAXNMP
  3178  	{
  3179  		// ZFMAXNMP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3180  		{
  3181  			goOp:      AZFMAXNMP,
  3182  			fixedBits: 0x64148000,
  3183  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  3184  		},
  3185  	},
  3186  	// ZFMAXNMQV
  3187  	{
  3188  		// ZFMAXNMQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  3189  		{
  3190  			goOp:      AZFMAXNMQV,
  3191  			fixedBits: 0x6414a000,
  3192  			args:      Zn_Tb__Pg__Vd_T__2,
  3193  		},
  3194  	},
  3195  	// ZFMAXNMVD
  3196  	{
  3197  		// ZFMAXNMVD <Zn>.<T>, <Pg>, <V><d>
  3198  		{
  3199  			goOp:      AZFMAXNMVD,
  3200  			fixedBits: 0x65c42000,
  3201  			args:      Zn_T__Pg__Vd__2,
  3202  		},
  3203  	},
  3204  	// ZFMAXNMVH
  3205  	{
  3206  		// ZFMAXNMVH <Zn>.<T>, <Pg>, <V><d>
  3207  		{
  3208  			goOp:      AZFMAXNMVH,
  3209  			fixedBits: 0x65442000,
  3210  			args:      Zn_T__Pg__Vd__2,
  3211  		},
  3212  	},
  3213  	// ZFMAXNMVS
  3214  	{
  3215  		// ZFMAXNMVS <Zn>.<T>, <Pg>, <V><d>
  3216  		{
  3217  			goOp:      AZFMAXNMVS,
  3218  			fixedBits: 0x65842000,
  3219  			args:      Zn_T__Pg__Vd__2,
  3220  		},
  3221  	},
  3222  	// ZFMAXP
  3223  	{
  3224  		// ZFMAXP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3225  		{
  3226  			goOp:      AZFMAXP,
  3227  			fixedBits: 0x64168000,
  3228  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  3229  		},
  3230  	},
  3231  	// ZFMAXQV
  3232  	{
  3233  		// ZFMAXQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  3234  		{
  3235  			goOp:      AZFMAXQV,
  3236  			fixedBits: 0x6416a000,
  3237  			args:      Zn_Tb__Pg__Vd_T__2,
  3238  		},
  3239  	},
  3240  	// ZFMAXVD
  3241  	{
  3242  		// ZFMAXVD <Zn>.<T>, <Pg>, <V><d>
  3243  		{
  3244  			goOp:      AZFMAXVD,
  3245  			fixedBits: 0x65c62000,
  3246  			args:      Zn_T__Pg__Vd__2,
  3247  		},
  3248  	},
  3249  	// ZFMAXVH
  3250  	{
  3251  		// ZFMAXVH <Zn>.<T>, <Pg>, <V><d>
  3252  		{
  3253  			goOp:      AZFMAXVH,
  3254  			fixedBits: 0x65462000,
  3255  			args:      Zn_T__Pg__Vd__2,
  3256  		},
  3257  	},
  3258  	// ZFMAXVS
  3259  	{
  3260  		// ZFMAXVS <Zn>.<T>, <Pg>, <V><d>
  3261  		{
  3262  			goOp:      AZFMAXVS,
  3263  			fixedBits: 0x65862000,
  3264  			args:      Zn_T__Pg__Vd__2,
  3265  		},
  3266  	},
  3267  	// ZFMIN
  3268  	{
  3269  		// ZFMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3270  		{
  3271  			goOp:      AZFMIN,
  3272  			fixedBits: 0x65078000,
  3273  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  3274  		},
  3275  		// ZFMIN <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3276  		{
  3277  			goOp:      AZFMIN,
  3278  			fixedBits: 0x651f8000,
  3279  			args:      const__Zdn_T__PgM__Zdn_T__1,
  3280  		},
  3281  	},
  3282  	// ZFMINNM
  3283  	{
  3284  		// ZFMINNM <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3285  		{
  3286  			goOp:      AZFMINNM,
  3287  			fixedBits: 0x65058000,
  3288  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  3289  		},
  3290  		// ZFMINNM <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3291  		{
  3292  			goOp:      AZFMINNM,
  3293  			fixedBits: 0x651d8000,
  3294  			args:      const__Zdn_T__PgM__Zdn_T__1,
  3295  		},
  3296  	},
  3297  	// ZFMINNMP
  3298  	{
  3299  		// ZFMINNMP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3300  		{
  3301  			goOp:      AZFMINNMP,
  3302  			fixedBits: 0x64158000,
  3303  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  3304  		},
  3305  	},
  3306  	// ZFMINNMQV
  3307  	{
  3308  		// ZFMINNMQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  3309  		{
  3310  			goOp:      AZFMINNMQV,
  3311  			fixedBits: 0x6415a000,
  3312  			args:      Zn_Tb__Pg__Vd_T__2,
  3313  		},
  3314  	},
  3315  	// ZFMINNMVD
  3316  	{
  3317  		// ZFMINNMVD <Zn>.<T>, <Pg>, <V><d>
  3318  		{
  3319  			goOp:      AZFMINNMVD,
  3320  			fixedBits: 0x65c52000,
  3321  			args:      Zn_T__Pg__Vd__2,
  3322  		},
  3323  	},
  3324  	// ZFMINNMVH
  3325  	{
  3326  		// ZFMINNMVH <Zn>.<T>, <Pg>, <V><d>
  3327  		{
  3328  			goOp:      AZFMINNMVH,
  3329  			fixedBits: 0x65452000,
  3330  			args:      Zn_T__Pg__Vd__2,
  3331  		},
  3332  	},
  3333  	// ZFMINNMVS
  3334  	{
  3335  		// ZFMINNMVS <Zn>.<T>, <Pg>, <V><d>
  3336  		{
  3337  			goOp:      AZFMINNMVS,
  3338  			fixedBits: 0x65852000,
  3339  			args:      Zn_T__Pg__Vd__2,
  3340  		},
  3341  	},
  3342  	// ZFMINP
  3343  	{
  3344  		// ZFMINP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3345  		{
  3346  			goOp:      AZFMINP,
  3347  			fixedBits: 0x64178000,
  3348  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  3349  		},
  3350  	},
  3351  	// ZFMINQV
  3352  	{
  3353  		// ZFMINQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  3354  		{
  3355  			goOp:      AZFMINQV,
  3356  			fixedBits: 0x6417a000,
  3357  			args:      Zn_Tb__Pg__Vd_T__2,
  3358  		},
  3359  	},
  3360  	// ZFMINVD
  3361  	{
  3362  		// ZFMINVD <Zn>.<T>, <Pg>, <V><d>
  3363  		{
  3364  			goOp:      AZFMINVD,
  3365  			fixedBits: 0x65c72000,
  3366  			args:      Zn_T__Pg__Vd__2,
  3367  		},
  3368  	},
  3369  	// ZFMINVH
  3370  	{
  3371  		// ZFMINVH <Zn>.<T>, <Pg>, <V><d>
  3372  		{
  3373  			goOp:      AZFMINVH,
  3374  			fixedBits: 0x65472000,
  3375  			args:      Zn_T__Pg__Vd__2,
  3376  		},
  3377  	},
  3378  	// ZFMINVS
  3379  	{
  3380  		// ZFMINVS <Zn>.<T>, <Pg>, <V><d>
  3381  		{
  3382  			goOp:      AZFMINVS,
  3383  			fixedBits: 0x65872000,
  3384  			args:      Zn_T__Pg__Vd__2,
  3385  		},
  3386  	},
  3387  	// ZFMLA
  3388  	{
  3389  		// ZFMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
  3390  		{
  3391  			goOp:      AZFMLA,
  3392  			fixedBits: 0x65200000,
  3393  			args:      Zm_T__Zn_T__PgM__Zda_T__1,
  3394  		},
  3395  		// ZFMLA <Zm>.D[<imm>], <Zn>.D, <Zda>.D
  3396  		{
  3397  			goOp:      AZFMLA,
  3398  			fixedBits: 0x64e00000,
  3399  			args:      Zm_D_imm___Zn_D__Zda_D__2,
  3400  		},
  3401  		// ZFMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  3402  		{
  3403  			goOp:      AZFMLA,
  3404  			fixedBits: 0x64200000,
  3405  			args:      Zm_H_imm___Zn_H__Zda_H__3,
  3406  		},
  3407  		// ZFMLA <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  3408  		{
  3409  			goOp:      AZFMLA,
  3410  			fixedBits: 0x64a00000,
  3411  			args:      Zm_S_imm___Zn_S__Zda_S__2,
  3412  		},
  3413  	},
  3414  	// ZFMLALB
  3415  	{
  3416  		// ZFMLALB <Zm>.B, <Zn>.B, <Zda>.H
  3417  		{
  3418  			goOp:      AZFMLALB,
  3419  			fixedBits: 0x64a08800,
  3420  			args:      Zm_B__Zn_B__Zda_H,
  3421  		},
  3422  		// ZFMLALB <Zm>.H, <Zn>.H, <Zda>.S
  3423  		{
  3424  			goOp:      AZFMLALB,
  3425  			fixedBits: 0x64a08000,
  3426  			args:      Zm_H__Zn_H__Zda_S,
  3427  		},
  3428  		// ZFMLALB <Zm>.B[<imm>], <Zn>.B, <Zda>.H
  3429  		{
  3430  			goOp:      AZFMLALB,
  3431  			fixedBits: 0x64205000,
  3432  			args:      Zm_B_imm___Zn_B__Zda_H__1,
  3433  		},
  3434  		// ZFMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  3435  		{
  3436  			goOp:      AZFMLALB,
  3437  			fixedBits: 0x64a04000,
  3438  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  3439  		},
  3440  	},
  3441  	// ZFMLALLBB
  3442  	{
  3443  		// ZFMLALLBB <Zm>.B, <Zn>.B, <Zda>.S
  3444  		{
  3445  			goOp:      AZFMLALLBB,
  3446  			fixedBits: 0x64208800,
  3447  			args:      Zm_B__Zn_B__Zda_S,
  3448  		},
  3449  		// ZFMLALLBB <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  3450  		{
  3451  			goOp:      AZFMLALLBB,
  3452  			fixedBits: 0x6420c000,
  3453  			args:      Zm_B_imm___Zn_B__Zda_S__1,
  3454  		},
  3455  	},
  3456  	// ZFMLALLBT
  3457  	{
  3458  		// ZFMLALLBT <Zm>.B, <Zn>.B, <Zda>.S
  3459  		{
  3460  			goOp:      AZFMLALLBT,
  3461  			fixedBits: 0x64209800,
  3462  			args:      Zm_B__Zn_B__Zda_S,
  3463  		},
  3464  		// ZFMLALLBT <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  3465  		{
  3466  			goOp:      AZFMLALLBT,
  3467  			fixedBits: 0x6460c000,
  3468  			args:      Zm_B_imm___Zn_B__Zda_S__1,
  3469  		},
  3470  	},
  3471  	// ZFMLALLTB
  3472  	{
  3473  		// ZFMLALLTB <Zm>.B, <Zn>.B, <Zda>.S
  3474  		{
  3475  			goOp:      AZFMLALLTB,
  3476  			fixedBits: 0x6420a800,
  3477  			args:      Zm_B__Zn_B__Zda_S,
  3478  		},
  3479  		// ZFMLALLTB <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  3480  		{
  3481  			goOp:      AZFMLALLTB,
  3482  			fixedBits: 0x64a0c000,
  3483  			args:      Zm_B_imm___Zn_B__Zda_S__1,
  3484  		},
  3485  	},
  3486  	// ZFMLALLTT
  3487  	{
  3488  		// ZFMLALLTT <Zm>.B, <Zn>.B, <Zda>.S
  3489  		{
  3490  			goOp:      AZFMLALLTT,
  3491  			fixedBits: 0x6420b800,
  3492  			args:      Zm_B__Zn_B__Zda_S,
  3493  		},
  3494  		// ZFMLALLTT <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  3495  		{
  3496  			goOp:      AZFMLALLTT,
  3497  			fixedBits: 0x64e0c000,
  3498  			args:      Zm_B_imm___Zn_B__Zda_S__1,
  3499  		},
  3500  	},
  3501  	// ZFMLALT
  3502  	{
  3503  		// ZFMLALT <Zm>.B, <Zn>.B, <Zda>.H
  3504  		{
  3505  			goOp:      AZFMLALT,
  3506  			fixedBits: 0x64a09800,
  3507  			args:      Zm_B__Zn_B__Zda_H,
  3508  		},
  3509  		// ZFMLALT <Zm>.H, <Zn>.H, <Zda>.S
  3510  		{
  3511  			goOp:      AZFMLALT,
  3512  			fixedBits: 0x64a08400,
  3513  			args:      Zm_H__Zn_H__Zda_S,
  3514  		},
  3515  		// ZFMLALT <Zm>.B[<imm>], <Zn>.B, <Zda>.H
  3516  		{
  3517  			goOp:      AZFMLALT,
  3518  			fixedBits: 0x64a05000,
  3519  			args:      Zm_B_imm___Zn_B__Zda_H__1,
  3520  		},
  3521  		// ZFMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  3522  		{
  3523  			goOp:      AZFMLALT,
  3524  			fixedBits: 0x64a04400,
  3525  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  3526  		},
  3527  	},
  3528  	// ZFMLS
  3529  	{
  3530  		// ZFMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
  3531  		{
  3532  			goOp:      AZFMLS,
  3533  			fixedBits: 0x65202000,
  3534  			args:      Zm_T__Zn_T__PgM__Zda_T__1,
  3535  		},
  3536  		// ZFMLS <Zm>.D[<imm>], <Zn>.D, <Zda>.D
  3537  		{
  3538  			goOp:      AZFMLS,
  3539  			fixedBits: 0x64e00400,
  3540  			args:      Zm_D_imm___Zn_D__Zda_D__2,
  3541  		},
  3542  		// ZFMLS <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  3543  		{
  3544  			goOp:      AZFMLS,
  3545  			fixedBits: 0x64200400,
  3546  			args:      Zm_H_imm___Zn_H__Zda_H__3,
  3547  		},
  3548  		// ZFMLS <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  3549  		{
  3550  			goOp:      AZFMLS,
  3551  			fixedBits: 0x64a00400,
  3552  			args:      Zm_S_imm___Zn_S__Zda_S__2,
  3553  		},
  3554  	},
  3555  	// ZFMLSLB
  3556  	{
  3557  		// ZFMLSLB <Zm>.H, <Zn>.H, <Zda>.S
  3558  		{
  3559  			goOp:      AZFMLSLB,
  3560  			fixedBits: 0x64a0a000,
  3561  			args:      Zm_H__Zn_H__Zda_S,
  3562  		},
  3563  		// ZFMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  3564  		{
  3565  			goOp:      AZFMLSLB,
  3566  			fixedBits: 0x64a06000,
  3567  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  3568  		},
  3569  	},
  3570  	// ZFMLSLT
  3571  	{
  3572  		// ZFMLSLT <Zm>.H, <Zn>.H, <Zda>.S
  3573  		{
  3574  			goOp:      AZFMLSLT,
  3575  			fixedBits: 0x64a0a400,
  3576  			args:      Zm_H__Zn_H__Zda_S,
  3577  		},
  3578  		// ZFMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  3579  		{
  3580  			goOp:      AZFMLSLT,
  3581  			fixedBits: 0x64a06400,
  3582  			args:      Zm_H_imm___Zn_H__Zda_S__2,
  3583  		},
  3584  	},
  3585  	// ZFMMLA
  3586  	{
  3587  		// ZFMMLA <Zm>.B, <Zn>.B, <Zda>.H
  3588  		{
  3589  			goOp:      AZFMMLA,
  3590  			fixedBits: 0x6460e000,
  3591  			args:      Zm_B__Zn_B__Zda_H,
  3592  		},
  3593  		// ZFMMLA <Zm>.B, <Zn>.B, <Zda>.S
  3594  		{
  3595  			goOp:      AZFMMLA,
  3596  			fixedBits: 0x6420e000,
  3597  			args:      Zm_B__Zn_B__Zda_S,
  3598  		},
  3599  		// ZFMMLA <Zm>.D, <Zn>.D, <Zda>.D
  3600  		{
  3601  			goOp:      AZFMMLA,
  3602  			fixedBits: 0x64e0e400,
  3603  			args:      Zm_D__Zn_D__Zda_D,
  3604  		},
  3605  		// ZFMMLA <Zm>.H, <Zn>.H, <Zda>.H
  3606  		{
  3607  			goOp:      AZFMMLA,
  3608  			fixedBits: 0x64a0e000,
  3609  			args:      Zm_H__Zn_H__Zda_H,
  3610  		},
  3611  		// ZFMMLA <Zm>.H, <Zn>.H, <Zda>.S
  3612  		{
  3613  			goOp:      AZFMMLA,
  3614  			fixedBits: 0x6420e400,
  3615  			args:      Zm_H__Zn_H__Zda_S,
  3616  		},
  3617  		// ZFMMLA <Zm>.S, <Zn>.S, <Zda>.S
  3618  		{
  3619  			goOp:      AZFMMLA,
  3620  			fixedBits: 0x64a0e400,
  3621  			args:      Zm_S__Zn_S__Zda_S,
  3622  		},
  3623  	},
  3624  	// ZFMSB
  3625  	{
  3626  		// ZFMSB <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
  3627  		{
  3628  			goOp:      AZFMSB,
  3629  			fixedBits: 0x6520a000,
  3630  			args:      Za_T__Zm_T__PgM__Zdn_T__1,
  3631  		},
  3632  	},
  3633  	// ZFMUL
  3634  	{
  3635  		// ZFMUL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3636  		{
  3637  			goOp:      AZFMUL,
  3638  			fixedBits: 0x65028000,
  3639  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  3640  		},
  3641  		// ZFMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  3642  		{
  3643  			goOp:      AZFMUL,
  3644  			fixedBits: 0x65000800,
  3645  			args:      Zm_T__Zn_T__Zd_T__2,
  3646  		},
  3647  		// ZFMUL <Zm>.D[<imm>], <Zn>.D, <Zd>.D
  3648  		{
  3649  			goOp:      AZFMUL,
  3650  			fixedBits: 0x64e02000,
  3651  			args:      Zm_D_imm___Zn_D__Zd_D__2,
  3652  		},
  3653  		// ZFMUL <Zm>.H[<imm>], <Zn>.H, <Zd>.H
  3654  		{
  3655  			goOp:      AZFMUL,
  3656  			fixedBits: 0x64202000,
  3657  			args:      Zm_H_imm___Zn_H__Zd_H__3,
  3658  		},
  3659  		// ZFMUL <Zm>.S[<imm>], <Zn>.S, <Zd>.S
  3660  		{
  3661  			goOp:      AZFMUL,
  3662  			fixedBits: 0x64a02000,
  3663  			args:      Zm_S_imm___Zn_S__Zd_S__2,
  3664  		},
  3665  		// ZFMUL <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3666  		{
  3667  			goOp:      AZFMUL,
  3668  			fixedBits: 0x651a8000,
  3669  			args:      const__Zdn_T__PgM__Zdn_T__3,
  3670  		},
  3671  	},
  3672  	// ZFMULX
  3673  	{
  3674  		// ZFMULX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3675  		{
  3676  			goOp:      AZFMULX,
  3677  			fixedBits: 0x650a8000,
  3678  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  3679  		},
  3680  	},
  3681  	// ZFNEG
  3682  	{
  3683  		// ZFNEG <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3684  		{
  3685  			goOp:      AZFNEG,
  3686  			fixedBits: 0x41da000,
  3687  			args:      Zn_T__PgM__Zd_T__1,
  3688  		},
  3689  		// ZFNEG <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3690  		{
  3691  			goOp:      AZFNEG,
  3692  			fixedBits: 0x40da000,
  3693  			args:      Zn_T__PgZ__Zd_T__1,
  3694  		},
  3695  	},
  3696  	// ZFNMAD
  3697  	{
  3698  		// ZFNMAD <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
  3699  		{
  3700  			goOp:      AZFNMAD,
  3701  			fixedBits: 0x6520c000,
  3702  			args:      Za_T__Zm_T__PgM__Zdn_T__1,
  3703  		},
  3704  	},
  3705  	// ZFNMLA
  3706  	{
  3707  		// ZFNMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
  3708  		{
  3709  			goOp:      AZFNMLA,
  3710  			fixedBits: 0x65204000,
  3711  			args:      Zm_T__Zn_T__PgM__Zda_T__1,
  3712  		},
  3713  	},
  3714  	// ZFNMLS
  3715  	{
  3716  		// ZFNMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
  3717  		{
  3718  			goOp:      AZFNMLS,
  3719  			fixedBits: 0x65206000,
  3720  			args:      Zm_T__Zn_T__PgM__Zda_T__1,
  3721  		},
  3722  	},
  3723  	// ZFNMSB
  3724  	{
  3725  		// ZFNMSB <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
  3726  		{
  3727  			goOp:      AZFNMSB,
  3728  			fixedBits: 0x6520e000,
  3729  			args:      Za_T__Zm_T__PgM__Zdn_T__1,
  3730  		},
  3731  	},
  3732  	// ZFRECPE
  3733  	{
  3734  		// ZFRECPE <Zn>.<T>, <Zd>.<T>
  3735  		{
  3736  			goOp:      AZFRECPE,
  3737  			fixedBits: 0x650e3000,
  3738  			args:      Zn_T__Zd_T__1,
  3739  		},
  3740  	},
  3741  	// ZFRECPS
  3742  	{
  3743  		// ZFRECPS <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  3744  		{
  3745  			goOp:      AZFRECPS,
  3746  			fixedBits: 0x65001800,
  3747  			args:      Zm_T__Zn_T__Zd_T__3,
  3748  		},
  3749  	},
  3750  	// ZFRECPX
  3751  	{
  3752  		// ZFRECPX <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3753  		{
  3754  			goOp:      AZFRECPX,
  3755  			fixedBits: 0x650ca000,
  3756  			args:      Zn_T__PgM__Zd_T__1,
  3757  		},
  3758  		// ZFRECPX <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3759  		{
  3760  			goOp:      AZFRECPX,
  3761  			fixedBits: 0x641b8000,
  3762  			args:      Zn_T__PgZ__Zd_T__1,
  3763  		},
  3764  	},
  3765  	// ZFRINT32X
  3766  	{
  3767  		// ZFRINT32X <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3768  		{
  3769  			goOp:      AZFRINT32X,
  3770  			fixedBits: 0x6511a000,
  3771  			args:      Zn_T__PgM__Zd_T__3,
  3772  		},
  3773  		// ZFRINT32X <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3774  		{
  3775  			goOp:      AZFRINT32X,
  3776  			fixedBits: 0x641ca000,
  3777  			args:      Zn_T__PgZ__Zd_T__3,
  3778  		},
  3779  	},
  3780  	// ZFRINT32Z
  3781  	{
  3782  		// ZFRINT32Z <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3783  		{
  3784  			goOp:      AZFRINT32Z,
  3785  			fixedBits: 0x6510a000,
  3786  			args:      Zn_T__PgM__Zd_T__3,
  3787  		},
  3788  		// ZFRINT32Z <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3789  		{
  3790  			goOp:      AZFRINT32Z,
  3791  			fixedBits: 0x641c8000,
  3792  			args:      Zn_T__PgZ__Zd_T__3,
  3793  		},
  3794  	},
  3795  	// ZFRINT64X
  3796  	{
  3797  		// ZFRINT64X <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3798  		{
  3799  			goOp:      AZFRINT64X,
  3800  			fixedBits: 0x6515a000,
  3801  			args:      Zn_T__PgM__Zd_T__3,
  3802  		},
  3803  		// ZFRINT64X <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3804  		{
  3805  			goOp:      AZFRINT64X,
  3806  			fixedBits: 0x641da000,
  3807  			args:      Zn_T__PgZ__Zd_T__3,
  3808  		},
  3809  	},
  3810  	// ZFRINT64Z
  3811  	{
  3812  		// ZFRINT64Z <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3813  		{
  3814  			goOp:      AZFRINT64Z,
  3815  			fixedBits: 0x6514a000,
  3816  			args:      Zn_T__PgM__Zd_T__3,
  3817  		},
  3818  		// ZFRINT64Z <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3819  		{
  3820  			goOp:      AZFRINT64Z,
  3821  			fixedBits: 0x641d8000,
  3822  			args:      Zn_T__PgZ__Zd_T__3,
  3823  		},
  3824  	},
  3825  	// ZFRINTA
  3826  	{
  3827  		// ZFRINTA <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3828  		{
  3829  			goOp:      AZFRINTA,
  3830  			fixedBits: 0x6504a000,
  3831  			args:      Zn_T__PgM__Zd_T__1,
  3832  		},
  3833  		// ZFRINTA <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3834  		{
  3835  			goOp:      AZFRINTA,
  3836  			fixedBits: 0x64198000,
  3837  			args:      Zn_T__PgZ__Zd_T__1,
  3838  		},
  3839  	},
  3840  	// ZFRINTI
  3841  	{
  3842  		// ZFRINTI <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3843  		{
  3844  			goOp:      AZFRINTI,
  3845  			fixedBits: 0x6507a000,
  3846  			args:      Zn_T__PgM__Zd_T__1,
  3847  		},
  3848  		// ZFRINTI <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3849  		{
  3850  			goOp:      AZFRINTI,
  3851  			fixedBits: 0x6419e000,
  3852  			args:      Zn_T__PgZ__Zd_T__1,
  3853  		},
  3854  	},
  3855  	// ZFRINTM
  3856  	{
  3857  		// ZFRINTM <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3858  		{
  3859  			goOp:      AZFRINTM,
  3860  			fixedBits: 0x6502a000,
  3861  			args:      Zn_T__PgM__Zd_T__1,
  3862  		},
  3863  		// ZFRINTM <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3864  		{
  3865  			goOp:      AZFRINTM,
  3866  			fixedBits: 0x6418c000,
  3867  			args:      Zn_T__PgZ__Zd_T__1,
  3868  		},
  3869  	},
  3870  	// ZFRINTN
  3871  	{
  3872  		// ZFRINTN <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3873  		{
  3874  			goOp:      AZFRINTN,
  3875  			fixedBits: 0x6500a000,
  3876  			args:      Zn_T__PgM__Zd_T__1,
  3877  		},
  3878  		// ZFRINTN <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3879  		{
  3880  			goOp:      AZFRINTN,
  3881  			fixedBits: 0x64188000,
  3882  			args:      Zn_T__PgZ__Zd_T__1,
  3883  		},
  3884  	},
  3885  	// ZFRINTP
  3886  	{
  3887  		// ZFRINTP <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3888  		{
  3889  			goOp:      AZFRINTP,
  3890  			fixedBits: 0x6501a000,
  3891  			args:      Zn_T__PgM__Zd_T__1,
  3892  		},
  3893  		// ZFRINTP <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3894  		{
  3895  			goOp:      AZFRINTP,
  3896  			fixedBits: 0x6418a000,
  3897  			args:      Zn_T__PgZ__Zd_T__1,
  3898  		},
  3899  	},
  3900  	// ZFRINTX
  3901  	{
  3902  		// ZFRINTX <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3903  		{
  3904  			goOp:      AZFRINTX,
  3905  			fixedBits: 0x6506a000,
  3906  			args:      Zn_T__PgM__Zd_T__1,
  3907  		},
  3908  		// ZFRINTX <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3909  		{
  3910  			goOp:      AZFRINTX,
  3911  			fixedBits: 0x6419c000,
  3912  			args:      Zn_T__PgZ__Zd_T__1,
  3913  		},
  3914  	},
  3915  	// ZFRINTZ
  3916  	{
  3917  		// ZFRINTZ <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3918  		{
  3919  			goOp:      AZFRINTZ,
  3920  			fixedBits: 0x6503a000,
  3921  			args:      Zn_T__PgM__Zd_T__1,
  3922  		},
  3923  		// ZFRINTZ <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3924  		{
  3925  			goOp:      AZFRINTZ,
  3926  			fixedBits: 0x6418e000,
  3927  			args:      Zn_T__PgZ__Zd_T__1,
  3928  		},
  3929  	},
  3930  	// ZFRSQRTE
  3931  	{
  3932  		// ZFRSQRTE <Zn>.<T>, <Zd>.<T>
  3933  		{
  3934  			goOp:      AZFRSQRTE,
  3935  			fixedBits: 0x650f3000,
  3936  			args:      Zn_T__Zd_T__1,
  3937  		},
  3938  	},
  3939  	// ZFRSQRTS
  3940  	{
  3941  		// ZFRSQRTS <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  3942  		{
  3943  			goOp:      AZFRSQRTS,
  3944  			fixedBits: 0x65001c00,
  3945  			args:      Zm_T__Zn_T__Zd_T__3,
  3946  		},
  3947  	},
  3948  	// ZFSCALE
  3949  	{
  3950  		// ZFSCALE <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3951  		{
  3952  			goOp:      AZFSCALE,
  3953  			fixedBits: 0x65098000,
  3954  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  3955  		},
  3956  	},
  3957  	// ZFSQRT
  3958  	{
  3959  		// ZFSQRT <Zn>.<T>, <Pg>/M, <Zd>.<T>
  3960  		{
  3961  			goOp:      AZFSQRT,
  3962  			fixedBits: 0x650da000,
  3963  			args:      Zn_T__PgM__Zd_T__1,
  3964  		},
  3965  		// ZFSQRT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  3966  		{
  3967  			goOp:      AZFSQRT,
  3968  			fixedBits: 0x641ba000,
  3969  			args:      Zn_T__PgZ__Zd_T__1,
  3970  		},
  3971  	},
  3972  	// ZFSUB
  3973  	{
  3974  		// ZFSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3975  		{
  3976  			goOp:      AZFSUB,
  3977  			fixedBits: 0x65018000,
  3978  			args:      Zm_T__Zdn_T__PgM__Zdn_T__3,
  3979  		},
  3980  		// ZFSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  3981  		{
  3982  			goOp:      AZFSUB,
  3983  			fixedBits: 0x65000400,
  3984  			args:      Zm_T__Zn_T__Zd_T__2,
  3985  		},
  3986  		// ZFSUB <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3987  		{
  3988  			goOp:      AZFSUB,
  3989  			fixedBits: 0x65198000,
  3990  			args:      const__Zdn_T__PgM__Zdn_T__2,
  3991  		},
  3992  	},
  3993  	// ZFSUBR
  3994  	{
  3995  		// ZFSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  3996  		{
  3997  			goOp:      AZFSUBR,
  3998  			fixedBits: 0x65038000,
  3999  			args:      Zm_T__Zdn_T__PgM__Zdn_T__2,
  4000  		},
  4001  		// ZFSUBR <const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  4002  		{
  4003  			goOp:      AZFSUBR,
  4004  			fixedBits: 0x651b8000,
  4005  			args:      const__Zdn_T__PgM__Zdn_T__2,
  4006  		},
  4007  	},
  4008  	// ZFTMAD
  4009  	{
  4010  		// ZFTMAD #<imm>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T>
  4011  		{
  4012  			goOp:      AZFTMAD,
  4013  			fixedBits: 0x65108000,
  4014  			args:      cimm__Zm_T__Zdn_T__Zdn_T,
  4015  		},
  4016  	},
  4017  	// ZFTSMUL
  4018  	{
  4019  		// ZFTSMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  4020  		{
  4021  			goOp:      AZFTSMUL,
  4022  			fixedBits: 0x65000c00,
  4023  			args:      Zm_T__Zn_T__Zd_T__3,
  4024  		},
  4025  	},
  4026  	// ZFTSSEL
  4027  	{
  4028  		// ZFTSSEL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  4029  		{
  4030  			goOp:      AZFTSSEL,
  4031  			fixedBits: 0x420b000,
  4032  			args:      Zm_T__Zn_T__Zd_T__3,
  4033  		},
  4034  	},
  4035  	// ZHISTCNT
  4036  	{
  4037  		// ZHISTCNT <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  4038  		{
  4039  			goOp:      AZHISTCNT,
  4040  			fixedBits: 0x45a0c000,
  4041  			args:      Zm_T__Zn_T__PgZ__Zd_T,
  4042  		},
  4043  	},
  4044  	// ZHISTSEG
  4045  	{
  4046  		// ZHISTSEG <Zm>.B, <Zn>.B, <Zd>.B
  4047  		{
  4048  			goOp:      AZHISTSEG,
  4049  			fixedBits: 0x4520a000,
  4050  			args:      Zm_B__Zn_B__Zd_B,
  4051  		},
  4052  	},
  4053  	// ZINCP
  4054  	{
  4055  		// ZINCP <Pm>.<T>, <Zdn>.<T>
  4056  		{
  4057  			goOp:      AZINCP,
  4058  			fixedBits: 0x252c8000,
  4059  			args:      Pm_T__Zdn_T,
  4060  		},
  4061  	},
  4062  	// ZINDEX
  4063  	{
  4064  		// ZINDEX <R><m>, <R><n>, <Zd>.<T>
  4065  		{
  4066  			goOp:      AZINDEX,
  4067  			fixedBits: 0x4e04c00,
  4068  			args:      Rm__Rn__Zd_T,
  4069  		},
  4070  		// ZINDEX <R><m>, #<imm>, <Zd>.<T>
  4071  		{
  4072  			goOp:      AZINDEX,
  4073  			fixedBits: 0x4e04800,
  4074  			args:      Rm__cimm__Zd_T,
  4075  		},
  4076  		// ZINDEX #<imm2>, #<imm1>, <Zd>.<T>
  4077  		{
  4078  			goOp:      AZINDEX,
  4079  			fixedBits: 0x4204000,
  4080  			args:      cimm2__cimm1__Zd_T,
  4081  		},
  4082  		// ZINDEX #<imm>, <R><n>, <Zd>.<T>
  4083  		{
  4084  			goOp:      AZINDEX,
  4085  			fixedBits: 0x4e04400,
  4086  			args:      cimm__Rn__Zd_T,
  4087  		},
  4088  	},
  4089  	// ZINDEXW
  4090  	{
  4091  		// ZINDEXW <R><m>, <R><n>, <Zd>.<T>
  4092  		{
  4093  			goOp:      AZINDEXW,
  4094  			fixedBits: 0x4204c00,
  4095  			args:      Rm__Rn__Zd_T,
  4096  		},
  4097  		// ZINDEXW <R><m>, #<imm>, <Zd>.<T>
  4098  		{
  4099  			goOp:      AZINDEXW,
  4100  			fixedBits: 0x4204800,
  4101  			args:      Rm__cimm__Zd_T,
  4102  		},
  4103  		// ZINDEXW #<imm>, <R><n>, <Zd>.<T>
  4104  		{
  4105  			goOp:      AZINDEXW,
  4106  			fixedBits: 0x4204400,
  4107  			args:      cimm__Rn__Zd_T,
  4108  		},
  4109  	},
  4110  	// ZINSR
  4111  	{
  4112  		// ZINSR <R><m>, <Zdn>.<T>
  4113  		{
  4114  			goOp:      AZINSR,
  4115  			fixedBits: 0x5e43800,
  4116  			args:      Rm__Zdn_T,
  4117  		},
  4118  	},
  4119  	// ZINSRB
  4120  	{
  4121  		// ZINSRB <V><m>, <Zdn>.<T>
  4122  		{
  4123  			goOp:      AZINSRB,
  4124  			fixedBits: 0x5343800,
  4125  			args:      Vm__Zdn_T,
  4126  		},
  4127  	},
  4128  	// ZINSRD
  4129  	{
  4130  		// ZINSRD <V><m>, <Zdn>.<T>
  4131  		{
  4132  			goOp:      AZINSRD,
  4133  			fixedBits: 0x5f43800,
  4134  			args:      Vm__Zdn_T,
  4135  		},
  4136  	},
  4137  	// ZINSRH
  4138  	{
  4139  		// ZINSRH <V><m>, <Zdn>.<T>
  4140  		{
  4141  			goOp:      AZINSRH,
  4142  			fixedBits: 0x5743800,
  4143  			args:      Vm__Zdn_T,
  4144  		},
  4145  	},
  4146  	// ZINSRS
  4147  	{
  4148  		// ZINSRS <V><m>, <Zdn>.<T>
  4149  		{
  4150  			goOp:      AZINSRS,
  4151  			fixedBits: 0x5b43800,
  4152  			args:      Vm__Zdn_T,
  4153  		},
  4154  	},
  4155  	// ZINSRW
  4156  	{
  4157  		// ZINSRW <R><m>, <Zdn>.<T>
  4158  		{
  4159  			goOp:      AZINSRW,
  4160  			fixedBits: 0x5243800,
  4161  			args:      Rm__Zdn_T,
  4162  		},
  4163  	},
  4164  	// ZLASTA
  4165  	{
  4166  		// ZLASTA <Zn>.<T>, <Pg>, <R><d>
  4167  		{
  4168  			goOp:      AZLASTA,
  4169  			fixedBits: 0x5e0a000,
  4170  			args:      Zn_T__Pg__Rd,
  4171  		},
  4172  	},
  4173  	// ZLASTAB
  4174  	{
  4175  		// ZLASTAB <Zn>.<T>, <Pg>, <V><d>
  4176  		{
  4177  			goOp:      AZLASTAB,
  4178  			fixedBits: 0x5228000,
  4179  			args:      Zn_T__Pg__Vd__1,
  4180  		},
  4181  	},
  4182  	// ZLASTAD
  4183  	{
  4184  		// ZLASTAD <Zn>.<T>, <Pg>, <V><d>
  4185  		{
  4186  			goOp:      AZLASTAD,
  4187  			fixedBits: 0x5e28000,
  4188  			args:      Zn_T__Pg__Vd__1,
  4189  		},
  4190  	},
  4191  	// ZLASTAH
  4192  	{
  4193  		// ZLASTAH <Zn>.<T>, <Pg>, <V><d>
  4194  		{
  4195  			goOp:      AZLASTAH,
  4196  			fixedBits: 0x5628000,
  4197  			args:      Zn_T__Pg__Vd__1,
  4198  		},
  4199  	},
  4200  	// ZLASTAS
  4201  	{
  4202  		// ZLASTAS <Zn>.<T>, <Pg>, <V><d>
  4203  		{
  4204  			goOp:      AZLASTAS,
  4205  			fixedBits: 0x5a28000,
  4206  			args:      Zn_T__Pg__Vd__1,
  4207  		},
  4208  	},
  4209  	// ZLASTAW
  4210  	{
  4211  		// ZLASTAW <Zn>.<T>, <Pg>, <R><d>
  4212  		{
  4213  			goOp:      AZLASTAW,
  4214  			fixedBits: 0x520a000,
  4215  			args:      Zn_T__Pg__Rd,
  4216  		},
  4217  	},
  4218  	// ZLASTB
  4219  	{
  4220  		// ZLASTB <Zn>.<T>, <Pg>, <R><d>
  4221  		{
  4222  			goOp:      AZLASTB,
  4223  			fixedBits: 0x5e1a000,
  4224  			args:      Zn_T__Pg__Rd,
  4225  		},
  4226  	},
  4227  	// ZLASTBB
  4228  	{
  4229  		// ZLASTBB <Zn>.<T>, <Pg>, <V><d>
  4230  		{
  4231  			goOp:      AZLASTBB,
  4232  			fixedBits: 0x5238000,
  4233  			args:      Zn_T__Pg__Vd__1,
  4234  		},
  4235  	},
  4236  	// ZLASTBD
  4237  	{
  4238  		// ZLASTBD <Zn>.<T>, <Pg>, <V><d>
  4239  		{
  4240  			goOp:      AZLASTBD,
  4241  			fixedBits: 0x5e38000,
  4242  			args:      Zn_T__Pg__Vd__1,
  4243  		},
  4244  	},
  4245  	// ZLASTBH
  4246  	{
  4247  		// ZLASTBH <Zn>.<T>, <Pg>, <V><d>
  4248  		{
  4249  			goOp:      AZLASTBH,
  4250  			fixedBits: 0x5638000,
  4251  			args:      Zn_T__Pg__Vd__1,
  4252  		},
  4253  	},
  4254  	// ZLASTBS
  4255  	{
  4256  		// ZLASTBS <Zn>.<T>, <Pg>, <V><d>
  4257  		{
  4258  			goOp:      AZLASTBS,
  4259  			fixedBits: 0x5a38000,
  4260  			args:      Zn_T__Pg__Vd__1,
  4261  		},
  4262  	},
  4263  	// ZLASTBW
  4264  	{
  4265  		// ZLASTBW <Zn>.<T>, <Pg>, <R><d>
  4266  		{
  4267  			goOp:      AZLASTBW,
  4268  			fixedBits: 0x521a000,
  4269  			args:      Zn_T__Pg__Rd,
  4270  		},
  4271  	},
  4272  	// ZLD1B
  4273  	{
  4274  		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
  4275  		{
  4276  			goOp:      AZLD1B,
  4277  			fixedBits: 0xa4004000,
  4278  			args:      XnSP__Xm___PgZ___Zt_B_,
  4279  		},
  4280  		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.D }
  4281  		{
  4282  			goOp:      AZLD1B,
  4283  			fixedBits: 0xa4604000,
  4284  			args:      XnSP__Xm___PgZ___Zt_D_,
  4285  		},
  4286  		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.H }
  4287  		{
  4288  			goOp:      AZLD1B,
  4289  			fixedBits: 0xa4204000,
  4290  			args:      XnSP__Xm___PgZ___Zt_H_,
  4291  		},
  4292  		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.S }
  4293  		{
  4294  			goOp:      AZLD1B,
  4295  			fixedBits: 0xa4404000,
  4296  			args:      XnSP__Xm___PgZ___Zt_S_,
  4297  		},
  4298  		// ZLD1B [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  4299  		{
  4300  			goOp:      AZLD1B,
  4301  			fixedBits: 0xc440c000,
  4302  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  4303  		},
  4304  		// ZLD1B [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  4305  		{
  4306  			goOp:      AZLD1B,
  4307  			fixedBits: 0xc4004000,
  4308  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  4309  		},
  4310  		// ZLD1B [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  4311  		{
  4312  			goOp:      AZLD1B,
  4313  			fixedBits: 0x84004000,
  4314  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  4315  		},
  4316  		// ZLD1B [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4317  		{
  4318  			goOp:      AZLD1B,
  4319  			fixedBits: 0xc420c000,
  4320  			args:      Zn_D__cimm___PgZ___Zt_D___1,
  4321  		},
  4322  		// ZLD1B [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4323  		{
  4324  			goOp:      AZLD1B,
  4325  			fixedBits: 0x8420c000,
  4326  			args:      Zn_S__cimm___PgZ___Zt_S___1,
  4327  		},
  4328  		// ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.B }
  4329  		{
  4330  			goOp:      AZLD1B,
  4331  			fixedBits: 0xa400a000,
  4332  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_B_,
  4333  		},
  4334  		// ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  4335  		{
  4336  			goOp:      AZLD1B,
  4337  			fixedBits: 0xa460a000,
  4338  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  4339  		},
  4340  		// ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
  4341  		{
  4342  			goOp:      AZLD1B,
  4343  			fixedBits: 0xa420a000,
  4344  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_H_,
  4345  		},
  4346  		// ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  4347  		{
  4348  			goOp:      AZLD1B,
  4349  			fixedBits: 0xa440a000,
  4350  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  4351  		},
  4352  		// ZLD1B [<Xn|SP>, <Xm>], <PNg>/Z, { <Zt1>.B-<Zt2>.B }
  4353  		{
  4354  			goOp:      AZLD1B,
  4355  			fixedBits: 0xa0000000,
  4356  			args:      XnSP__Xm___PNgZ___Zt1_B_Zt2_B_,
  4357  		},
  4358  		// ZLD1B [<Xn|SP>, <Xm>], <PNg>/Z, { <Zt1>.B-<Zt4>.B }
  4359  		{
  4360  			goOp:      AZLD1B,
  4361  			fixedBits: 0xa0008000,
  4362  			args:      XnSP__Xm___PNgZ___Zt1_B_Zt4_B_,
  4363  		},
  4364  		// ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.B-<Zt2>.B }
  4365  		{
  4366  			goOp:      AZLD1B,
  4367  			fixedBits: 0xa0400000,
  4368  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt2_B_,
  4369  		},
  4370  		// ZLD1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.B-<Zt4>.B }
  4371  		{
  4372  			goOp:      AZLD1B,
  4373  			fixedBits: 0xa0408000,
  4374  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt4_B_,
  4375  		},
  4376  	},
  4377  	// ZLD1D
  4378  	{
  4379  		// ZLD1D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.D }
  4380  		{
  4381  			goOp:      AZLD1D,
  4382  			fixedBits: 0xa5e04000,
  4383  			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
  4384  		},
  4385  		// ZLD1D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.Q }
  4386  		{
  4387  			goOp:      AZLD1D,
  4388  			fixedBits: 0xa5808000,
  4389  			args:      XnSP__Xm__LSL_c3___PgZ___Zt_Q_,
  4390  		},
  4391  		// ZLD1D [<Xn|SP>, <Zm>.D, LSL #3], <Pg>/Z, { <Zt>.D }
  4392  		{
  4393  			goOp:      AZLD1D,
  4394  			fixedBits: 0xc5e0c000,
  4395  			args:      XnSP__Zm_D__LSL_c3___PgZ___Zt_D_,
  4396  		},
  4397  		// ZLD1D [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  4398  		{
  4399  			goOp:      AZLD1D,
  4400  			fixedBits: 0xc5c0c000,
  4401  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  4402  		},
  4403  		// ZLD1D [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  4404  		{
  4405  			goOp:      AZLD1D,
  4406  			fixedBits: 0xc5804000,
  4407  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  4408  		},
  4409  		// ZLD1D [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>/Z, { <Zt>.D }
  4410  		{
  4411  			goOp:      AZLD1D,
  4412  			fixedBits: 0xc5a04000,
  4413  			args:      XnSP__Zm_D__mod_c3___PgZ___Zt_D_,
  4414  		},
  4415  		// ZLD1D [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4416  		{
  4417  			goOp:      AZLD1D,
  4418  			fixedBits: 0xc5a0c000,
  4419  			args:      Zn_D__cimm___PgZ___Zt_D___4,
  4420  		},
  4421  		// ZLD1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  4422  		{
  4423  			goOp:      AZLD1D,
  4424  			fixedBits: 0xa5e0a000,
  4425  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  4426  		},
  4427  		// ZLD1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.Q }
  4428  		{
  4429  			goOp:      AZLD1D,
  4430  			fixedBits: 0xa5902000,
  4431  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_Q_,
  4432  		},
  4433  		// ZLD1D [<Xn|SP>, <Xm>, LSL #3], <PNg>/Z, { <Zt1>.D-<Zt2>.D }
  4434  		{
  4435  			goOp:      AZLD1D,
  4436  			fixedBits: 0xa0006000,
  4437  			args:      XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt2_D_,
  4438  		},
  4439  		// ZLD1D [<Xn|SP>, <Xm>, LSL #3], <PNg>/Z, { <Zt1>.D-<Zt4>.D }
  4440  		{
  4441  			goOp:      AZLD1D,
  4442  			fixedBits: 0xa000e000,
  4443  			args:      XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt4_D_,
  4444  		},
  4445  		// ZLD1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.D-<Zt2>.D }
  4446  		{
  4447  			goOp:      AZLD1D,
  4448  			fixedBits: 0xa0406000,
  4449  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt2_D_,
  4450  		},
  4451  		// ZLD1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.D-<Zt4>.D }
  4452  		{
  4453  			goOp:      AZLD1D,
  4454  			fixedBits: 0xa040e000,
  4455  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt4_D_,
  4456  		},
  4457  	},
  4458  	// ZLD1H
  4459  	{
  4460  		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.D }
  4461  		{
  4462  			goOp:      AZLD1H,
  4463  			fixedBits: 0xa4e04000,
  4464  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D_,
  4465  		},
  4466  		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
  4467  		{
  4468  			goOp:      AZLD1H,
  4469  			fixedBits: 0xa4a04000,
  4470  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
  4471  		},
  4472  		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.S }
  4473  		{
  4474  			goOp:      AZLD1H,
  4475  			fixedBits: 0xa4c04000,
  4476  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S_,
  4477  		},
  4478  		// ZLD1H [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
  4479  		{
  4480  			goOp:      AZLD1H,
  4481  			fixedBits: 0xc4e0c000,
  4482  			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
  4483  		},
  4484  		// ZLD1H [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  4485  		{
  4486  			goOp:      AZLD1H,
  4487  			fixedBits: 0xc4c0c000,
  4488  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  4489  		},
  4490  		// ZLD1H [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  4491  		{
  4492  			goOp:      AZLD1H,
  4493  			fixedBits: 0xc4804000,
  4494  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  4495  		},
  4496  		// ZLD1H [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
  4497  		{
  4498  			goOp:      AZLD1H,
  4499  			fixedBits: 0xc4a04000,
  4500  			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
  4501  		},
  4502  		// ZLD1H [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  4503  		{
  4504  			goOp:      AZLD1H,
  4505  			fixedBits: 0x84804000,
  4506  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  4507  		},
  4508  		// ZLD1H [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
  4509  		{
  4510  			goOp:      AZLD1H,
  4511  			fixedBits: 0x84a04000,
  4512  			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
  4513  		},
  4514  		// ZLD1H [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4515  		{
  4516  			goOp:      AZLD1H,
  4517  			fixedBits: 0xc4a0c000,
  4518  			args:      Zn_D__cimm___PgZ___Zt_D___2,
  4519  		},
  4520  		// ZLD1H [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4521  		{
  4522  			goOp:      AZLD1H,
  4523  			fixedBits: 0x84a0c000,
  4524  			args:      Zn_S__cimm___PgZ___Zt_S___2,
  4525  		},
  4526  		// ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  4527  		{
  4528  			goOp:      AZLD1H,
  4529  			fixedBits: 0xa4e0a000,
  4530  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  4531  		},
  4532  		// ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
  4533  		{
  4534  			goOp:      AZLD1H,
  4535  			fixedBits: 0xa4a0a000,
  4536  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_H_,
  4537  		},
  4538  		// ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  4539  		{
  4540  			goOp:      AZLD1H,
  4541  			fixedBits: 0xa4c0a000,
  4542  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  4543  		},
  4544  		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <PNg>/Z, { <Zt1>.H-<Zt2>.H }
  4545  		{
  4546  			goOp:      AZLD1H,
  4547  			fixedBits: 0xa0002000,
  4548  			args:      XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt2_H_,
  4549  		},
  4550  		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <PNg>/Z, { <Zt1>.H-<Zt4>.H }
  4551  		{
  4552  			goOp:      AZLD1H,
  4553  			fixedBits: 0xa000a000,
  4554  			args:      XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt4_H_,
  4555  		},
  4556  		// ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.H-<Zt2>.H }
  4557  		{
  4558  			goOp:      AZLD1H,
  4559  			fixedBits: 0xa0402000,
  4560  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt2_H_,
  4561  		},
  4562  		// ZLD1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.H-<Zt4>.H }
  4563  		{
  4564  			goOp:      AZLD1H,
  4565  			fixedBits: 0xa040a000,
  4566  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt4_H_,
  4567  		},
  4568  	},
  4569  	// ZLD1Q
  4570  	{
  4571  		// ZLD1Q [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.Q }
  4572  		{
  4573  			goOp:      AZLD1Q,
  4574  			fixedBits: 0xc400a000,
  4575  			args:      Zn_D__Xm___PgZ___Zt_Q_,
  4576  		},
  4577  	},
  4578  	// ZLD1RB
  4579  	{
  4580  		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.B }
  4581  		{
  4582  			goOp:      AZLD1RB,
  4583  			fixedBits: 0x84408000,
  4584  			args:      XnSP__cimm___PgZ___Zt_B___1,
  4585  		},
  4586  		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4587  		{
  4588  			goOp:      AZLD1RB,
  4589  			fixedBits: 0x8440e000,
  4590  			args:      XnSP__cimm___PgZ___Zt_D___1,
  4591  		},
  4592  		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
  4593  		{
  4594  			goOp:      AZLD1RB,
  4595  			fixedBits: 0x8440a000,
  4596  			args:      XnSP__cimm___PgZ___Zt_H___1,
  4597  		},
  4598  		// ZLD1RB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4599  		{
  4600  			goOp:      AZLD1RB,
  4601  			fixedBits: 0x8440c000,
  4602  			args:      XnSP__cimm___PgZ___Zt_S___1,
  4603  		},
  4604  	},
  4605  	// ZLD1RD
  4606  	{
  4607  		// ZLD1RD [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4608  		{
  4609  			goOp:      AZLD1RD,
  4610  			fixedBits: 0x85c0e000,
  4611  			args:      XnSP__cimm___PgZ___Zt_D___4,
  4612  		},
  4613  	},
  4614  	// ZLD1RH
  4615  	{
  4616  		// ZLD1RH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4617  		{
  4618  			goOp:      AZLD1RH,
  4619  			fixedBits: 0x84c0e000,
  4620  			args:      XnSP__cimm___PgZ___Zt_D___2,
  4621  		},
  4622  		// ZLD1RH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
  4623  		{
  4624  			goOp:      AZLD1RH,
  4625  			fixedBits: 0x84c0a000,
  4626  			args:      XnSP__cimm___PgZ___Zt_H___2,
  4627  		},
  4628  		// ZLD1RH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4629  		{
  4630  			goOp:      AZLD1RH,
  4631  			fixedBits: 0x84c0c000,
  4632  			args:      XnSP__cimm___PgZ___Zt_S___2,
  4633  		},
  4634  	},
  4635  	// ZLD1ROB
  4636  	{
  4637  		// ZLD1ROB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
  4638  		{
  4639  			goOp:      AZLD1ROB,
  4640  			fixedBits: 0xa4200000,
  4641  			args:      XnSP__Xm___PgZ___Zt_B_,
  4642  		},
  4643  		// ZLD1ROB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.B }
  4644  		{
  4645  			goOp:      AZLD1ROB,
  4646  			fixedBits: 0xa4202000,
  4647  			args:      XnSP__cimm___PgZ___Zt_B___2,
  4648  		},
  4649  	},
  4650  	// ZLD1ROD
  4651  	{
  4652  		// ZLD1ROD [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.D }
  4653  		{
  4654  			goOp:      AZLD1ROD,
  4655  			fixedBits: 0xa5a00000,
  4656  			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
  4657  		},
  4658  		// ZLD1ROD [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4659  		{
  4660  			goOp:      AZLD1ROD,
  4661  			fixedBits: 0xa5a02000,
  4662  			args:      XnSP__cimm___PgZ___Zt_D___5,
  4663  		},
  4664  	},
  4665  	// ZLD1ROH
  4666  	{
  4667  		// ZLD1ROH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
  4668  		{
  4669  			goOp:      AZLD1ROH,
  4670  			fixedBits: 0xa4a00000,
  4671  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
  4672  		},
  4673  		// ZLD1ROH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
  4674  		{
  4675  			goOp:      AZLD1ROH,
  4676  			fixedBits: 0xa4a02000,
  4677  			args:      XnSP__cimm___PgZ___Zt_H___3,
  4678  		},
  4679  	},
  4680  	// ZLD1ROW
  4681  	{
  4682  		// ZLD1ROW [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.S }
  4683  		{
  4684  			goOp:      AZLD1ROW,
  4685  			fixedBits: 0xa5200000,
  4686  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
  4687  		},
  4688  		// ZLD1ROW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4689  		{
  4690  			goOp:      AZLD1ROW,
  4691  			fixedBits: 0xa5202000,
  4692  			args:      XnSP__cimm___PgZ___Zt_S___3,
  4693  		},
  4694  	},
  4695  	// ZLD1RQB
  4696  	{
  4697  		// ZLD1RQB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
  4698  		{
  4699  			goOp:      AZLD1RQB,
  4700  			fixedBits: 0xa4000000,
  4701  			args:      XnSP__Xm___PgZ___Zt_B_,
  4702  		},
  4703  		// ZLD1RQB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.B }
  4704  		{
  4705  			goOp:      AZLD1RQB,
  4706  			fixedBits: 0xa4002000,
  4707  			args:      XnSP__cimm___PgZ___Zt_B___3,
  4708  		},
  4709  	},
  4710  	// ZLD1RQD
  4711  	{
  4712  		// ZLD1RQD [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.D }
  4713  		{
  4714  			goOp:      AZLD1RQD,
  4715  			fixedBits: 0xa5800000,
  4716  			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
  4717  		},
  4718  		// ZLD1RQD [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4719  		{
  4720  			goOp:      AZLD1RQD,
  4721  			fixedBits: 0xa5802000,
  4722  			args:      XnSP__cimm___PgZ___Zt_D___6,
  4723  		},
  4724  	},
  4725  	// ZLD1RQH
  4726  	{
  4727  		// ZLD1RQH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
  4728  		{
  4729  			goOp:      AZLD1RQH,
  4730  			fixedBits: 0xa4800000,
  4731  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
  4732  		},
  4733  		// ZLD1RQH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
  4734  		{
  4735  			goOp:      AZLD1RQH,
  4736  			fixedBits: 0xa4802000,
  4737  			args:      XnSP__cimm___PgZ___Zt_H___4,
  4738  		},
  4739  	},
  4740  	// ZLD1RQW
  4741  	{
  4742  		// ZLD1RQW [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.S }
  4743  		{
  4744  			goOp:      AZLD1RQW,
  4745  			fixedBits: 0xa5000000,
  4746  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
  4747  		},
  4748  		// ZLD1RQW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4749  		{
  4750  			goOp:      AZLD1RQW,
  4751  			fixedBits: 0xa5002000,
  4752  			args:      XnSP__cimm___PgZ___Zt_S___4,
  4753  		},
  4754  	},
  4755  	// ZLD1RSB
  4756  	{
  4757  		// ZLD1RSB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4758  		{
  4759  			goOp:      AZLD1RSB,
  4760  			fixedBits: 0x85c08000,
  4761  			args:      XnSP__cimm___PgZ___Zt_D___1,
  4762  		},
  4763  		// ZLD1RSB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.H }
  4764  		{
  4765  			goOp:      AZLD1RSB,
  4766  			fixedBits: 0x85c0c000,
  4767  			args:      XnSP__cimm___PgZ___Zt_H___1,
  4768  		},
  4769  		// ZLD1RSB [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4770  		{
  4771  			goOp:      AZLD1RSB,
  4772  			fixedBits: 0x85c0a000,
  4773  			args:      XnSP__cimm___PgZ___Zt_S___1,
  4774  		},
  4775  	},
  4776  	// ZLD1RSH
  4777  	{
  4778  		// ZLD1RSH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4779  		{
  4780  			goOp:      AZLD1RSH,
  4781  			fixedBits: 0x85408000,
  4782  			args:      XnSP__cimm___PgZ___Zt_D___2,
  4783  		},
  4784  		// ZLD1RSH [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4785  		{
  4786  			goOp:      AZLD1RSH,
  4787  			fixedBits: 0x8540a000,
  4788  			args:      XnSP__cimm___PgZ___Zt_S___2,
  4789  		},
  4790  	},
  4791  	// ZLD1RSW
  4792  	{
  4793  		// ZLD1RSW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4794  		{
  4795  			goOp:      AZLD1RSW,
  4796  			fixedBits: 0x84c08000,
  4797  			args:      XnSP__cimm___PgZ___Zt_D___3,
  4798  		},
  4799  	},
  4800  	// ZLD1RW
  4801  	{
  4802  		// ZLD1RW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4803  		{
  4804  			goOp:      AZLD1RW,
  4805  			fixedBits: 0x8540e000,
  4806  			args:      XnSP__cimm___PgZ___Zt_D___3,
  4807  		},
  4808  		// ZLD1RW [<Xn|SP>{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4809  		{
  4810  			goOp:      AZLD1RW,
  4811  			fixedBits: 0x8540c000,
  4812  			args:      XnSP__cimm___PgZ___Zt_S___5,
  4813  		},
  4814  	},
  4815  	// ZLD1SB
  4816  	{
  4817  		// ZLD1SB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.D }
  4818  		{
  4819  			goOp:      AZLD1SB,
  4820  			fixedBits: 0xa5804000,
  4821  			args:      XnSP__Xm___PgZ___Zt_D_,
  4822  		},
  4823  		// ZLD1SB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.H }
  4824  		{
  4825  			goOp:      AZLD1SB,
  4826  			fixedBits: 0xa5c04000,
  4827  			args:      XnSP__Xm___PgZ___Zt_H_,
  4828  		},
  4829  		// ZLD1SB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.S }
  4830  		{
  4831  			goOp:      AZLD1SB,
  4832  			fixedBits: 0xa5a04000,
  4833  			args:      XnSP__Xm___PgZ___Zt_S_,
  4834  		},
  4835  		// ZLD1SB [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  4836  		{
  4837  			goOp:      AZLD1SB,
  4838  			fixedBits: 0xc4408000,
  4839  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  4840  		},
  4841  		// ZLD1SB [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  4842  		{
  4843  			goOp:      AZLD1SB,
  4844  			fixedBits: 0xc4000000,
  4845  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  4846  		},
  4847  		// ZLD1SB [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  4848  		{
  4849  			goOp:      AZLD1SB,
  4850  			fixedBits: 0x84000000,
  4851  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  4852  		},
  4853  		// ZLD1SB [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4854  		{
  4855  			goOp:      AZLD1SB,
  4856  			fixedBits: 0xc4208000,
  4857  			args:      Zn_D__cimm___PgZ___Zt_D___1,
  4858  		},
  4859  		// ZLD1SB [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4860  		{
  4861  			goOp:      AZLD1SB,
  4862  			fixedBits: 0x84208000,
  4863  			args:      Zn_S__cimm___PgZ___Zt_S___1,
  4864  		},
  4865  		// ZLD1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  4866  		{
  4867  			goOp:      AZLD1SB,
  4868  			fixedBits: 0xa580a000,
  4869  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  4870  		},
  4871  		// ZLD1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
  4872  		{
  4873  			goOp:      AZLD1SB,
  4874  			fixedBits: 0xa5c0a000,
  4875  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_H_,
  4876  		},
  4877  		// ZLD1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  4878  		{
  4879  			goOp:      AZLD1SB,
  4880  			fixedBits: 0xa5a0a000,
  4881  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  4882  		},
  4883  	},
  4884  	// ZLD1SH
  4885  	{
  4886  		// ZLD1SH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.D }
  4887  		{
  4888  			goOp:      AZLD1SH,
  4889  			fixedBits: 0xa5004000,
  4890  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D_,
  4891  		},
  4892  		// ZLD1SH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.S }
  4893  		{
  4894  			goOp:      AZLD1SH,
  4895  			fixedBits: 0xa5204000,
  4896  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S_,
  4897  		},
  4898  		// ZLD1SH [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
  4899  		{
  4900  			goOp:      AZLD1SH,
  4901  			fixedBits: 0xc4e08000,
  4902  			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
  4903  		},
  4904  		// ZLD1SH [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  4905  		{
  4906  			goOp:      AZLD1SH,
  4907  			fixedBits: 0xc4c08000,
  4908  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  4909  		},
  4910  		// ZLD1SH [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  4911  		{
  4912  			goOp:      AZLD1SH,
  4913  			fixedBits: 0xc4800000,
  4914  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  4915  		},
  4916  		// ZLD1SH [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
  4917  		{
  4918  			goOp:      AZLD1SH,
  4919  			fixedBits: 0xc4a00000,
  4920  			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
  4921  		},
  4922  		// ZLD1SH [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  4923  		{
  4924  			goOp:      AZLD1SH,
  4925  			fixedBits: 0x84800000,
  4926  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  4927  		},
  4928  		// ZLD1SH [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
  4929  		{
  4930  			goOp:      AZLD1SH,
  4931  			fixedBits: 0x84a00000,
  4932  			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
  4933  		},
  4934  		// ZLD1SH [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4935  		{
  4936  			goOp:      AZLD1SH,
  4937  			fixedBits: 0xc4a08000,
  4938  			args:      Zn_D__cimm___PgZ___Zt_D___2,
  4939  		},
  4940  		// ZLD1SH [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  4941  		{
  4942  			goOp:      AZLD1SH,
  4943  			fixedBits: 0x84a08000,
  4944  			args:      Zn_S__cimm___PgZ___Zt_S___2,
  4945  		},
  4946  		// ZLD1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  4947  		{
  4948  			goOp:      AZLD1SH,
  4949  			fixedBits: 0xa500a000,
  4950  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  4951  		},
  4952  		// ZLD1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  4953  		{
  4954  			goOp:      AZLD1SH,
  4955  			fixedBits: 0xa520a000,
  4956  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  4957  		},
  4958  	},
  4959  	// ZLD1SW
  4960  	{
  4961  		// ZLD1SW [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.D }
  4962  		{
  4963  			goOp:      AZLD1SW,
  4964  			fixedBits: 0xa4804000,
  4965  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_D_,
  4966  		},
  4967  		// ZLD1SW [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
  4968  		{
  4969  			goOp:      AZLD1SW,
  4970  			fixedBits: 0xc5608000,
  4971  			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
  4972  		},
  4973  		// ZLD1SW [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  4974  		{
  4975  			goOp:      AZLD1SW,
  4976  			fixedBits: 0xc5408000,
  4977  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  4978  		},
  4979  		// ZLD1SW [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  4980  		{
  4981  			goOp:      AZLD1SW,
  4982  			fixedBits: 0xc5000000,
  4983  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  4984  		},
  4985  		// ZLD1SW [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
  4986  		{
  4987  			goOp:      AZLD1SW,
  4988  			fixedBits: 0xc5200000,
  4989  			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
  4990  		},
  4991  		// ZLD1SW [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  4992  		{
  4993  			goOp:      AZLD1SW,
  4994  			fixedBits: 0xc5208000,
  4995  			args:      Zn_D__cimm___PgZ___Zt_D___3,
  4996  		},
  4997  		// ZLD1SW [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  4998  		{
  4999  			goOp:      AZLD1SW,
  5000  			fixedBits: 0xa480a000,
  5001  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5002  		},
  5003  	},
  5004  	// ZLD1W
  5005  	{
  5006  		// ZLD1W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.D }
  5007  		{
  5008  			goOp:      AZLD1W,
  5009  			fixedBits: 0xa5604000,
  5010  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_D_,
  5011  		},
  5012  		// ZLD1W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.Q }
  5013  		{
  5014  			goOp:      AZLD1W,
  5015  			fixedBits: 0xa5008000,
  5016  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_Q_,
  5017  		},
  5018  		// ZLD1W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.S }
  5019  		{
  5020  			goOp:      AZLD1W,
  5021  			fixedBits: 0xa5404000,
  5022  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
  5023  		},
  5024  		// ZLD1W [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
  5025  		{
  5026  			goOp:      AZLD1W,
  5027  			fixedBits: 0xc560c000,
  5028  			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
  5029  		},
  5030  		// ZLD1W [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5031  		{
  5032  			goOp:      AZLD1W,
  5033  			fixedBits: 0xc540c000,
  5034  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5035  		},
  5036  		// ZLD1W [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5037  		{
  5038  			goOp:      AZLD1W,
  5039  			fixedBits: 0xc5004000,
  5040  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5041  		},
  5042  		// ZLD1W [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
  5043  		{
  5044  			goOp:      AZLD1W,
  5045  			fixedBits: 0xc5204000,
  5046  			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
  5047  		},
  5048  		// ZLD1W [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  5049  		{
  5050  			goOp:      AZLD1W,
  5051  			fixedBits: 0x85004000,
  5052  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  5053  		},
  5054  		// ZLD1W [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>/Z, { <Zt>.S }
  5055  		{
  5056  			goOp:      AZLD1W,
  5057  			fixedBits: 0x85204000,
  5058  			args:      XnSP__Zm_S__mod_c2___PgZ___Zt_S_,
  5059  		},
  5060  		// ZLD1W [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5061  		{
  5062  			goOp:      AZLD1W,
  5063  			fixedBits: 0xc520c000,
  5064  			args:      Zn_D__cimm___PgZ___Zt_D___3,
  5065  		},
  5066  		// ZLD1W [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  5067  		{
  5068  			goOp:      AZLD1W,
  5069  			fixedBits: 0x8520c000,
  5070  			args:      Zn_S__cimm___PgZ___Zt_S___3,
  5071  		},
  5072  		// ZLD1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5073  		{
  5074  			goOp:      AZLD1W,
  5075  			fixedBits: 0xa560a000,
  5076  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5077  		},
  5078  		// ZLD1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.Q }
  5079  		{
  5080  			goOp:      AZLD1W,
  5081  			fixedBits: 0xa5102000,
  5082  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_Q_,
  5083  		},
  5084  		// ZLD1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  5085  		{
  5086  			goOp:      AZLD1W,
  5087  			fixedBits: 0xa540a000,
  5088  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  5089  		},
  5090  		// ZLD1W [<Xn|SP>, <Xm>, LSL #2], <PNg>/Z, { <Zt1>.S-<Zt2>.S }
  5091  		{
  5092  			goOp:      AZLD1W,
  5093  			fixedBits: 0xa0004000,
  5094  			args:      XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt2_S_,
  5095  		},
  5096  		// ZLD1W [<Xn|SP>, <Xm>, LSL #2], <PNg>/Z, { <Zt1>.S-<Zt4>.S }
  5097  		{
  5098  			goOp:      AZLD1W,
  5099  			fixedBits: 0xa000c000,
  5100  			args:      XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt4_S_,
  5101  		},
  5102  		// ZLD1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.S-<Zt2>.S }
  5103  		{
  5104  			goOp:      AZLD1W,
  5105  			fixedBits: 0xa0404000,
  5106  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt2_S_,
  5107  		},
  5108  		// ZLD1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.S-<Zt4>.S }
  5109  		{
  5110  			goOp:      AZLD1W,
  5111  			fixedBits: 0xa040c000,
  5112  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt4_S_,
  5113  		},
  5114  	},
  5115  	// ZLD2B
  5116  	{
  5117  		// ZLD2B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt1>.B, <Zt2>.B }
  5118  		{
  5119  			goOp:      AZLD2B,
  5120  			fixedBits: 0xa420c000,
  5121  			args:      XnSP__Xm___PgZ___Zt1_B__Zt2_B_,
  5122  		},
  5123  		// ZLD2B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.B, <Zt2>.B }
  5124  		{
  5125  			goOp:      AZLD2B,
  5126  			fixedBits: 0xa420e000,
  5127  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B_,
  5128  		},
  5129  	},
  5130  	// ZLD2D
  5131  	{
  5132  		// ZLD2D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt1>.D, <Zt2>.D }
  5133  		{
  5134  			goOp:      AZLD2D,
  5135  			fixedBits: 0xa5a0c000,
  5136  			args:      XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_,
  5137  		},
  5138  		// ZLD2D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.D, <Zt2>.D }
  5139  		{
  5140  			goOp:      AZLD2D,
  5141  			fixedBits: 0xa5a0e000,
  5142  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D_,
  5143  		},
  5144  	},
  5145  	// ZLD2H
  5146  	{
  5147  		// ZLD2H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt1>.H, <Zt2>.H }
  5148  		{
  5149  			goOp:      AZLD2H,
  5150  			fixedBits: 0xa4a0c000,
  5151  			args:      XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_,
  5152  		},
  5153  		// ZLD2H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.H, <Zt2>.H }
  5154  		{
  5155  			goOp:      AZLD2H,
  5156  			fixedBits: 0xa4a0e000,
  5157  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H_,
  5158  		},
  5159  	},
  5160  	// ZLD2Q
  5161  	{
  5162  		// ZLD2Q [<Xn|SP>, <Xm>, LSL #4], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q }
  5163  		{
  5164  			goOp:      AZLD2Q,
  5165  			fixedBits: 0xa4a08000,
  5166  			args:      XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_,
  5167  		},
  5168  		// ZLD2Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q }
  5169  		{
  5170  			goOp:      AZLD2Q,
  5171  			fixedBits: 0xa490e000,
  5172  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q_,
  5173  		},
  5174  	},
  5175  	// ZLD2W
  5176  	{
  5177  		// ZLD2W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt1>.S, <Zt2>.S }
  5178  		{
  5179  			goOp:      AZLD2W,
  5180  			fixedBits: 0xa520c000,
  5181  			args:      XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_,
  5182  		},
  5183  		// ZLD2W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.S, <Zt2>.S }
  5184  		{
  5185  			goOp:      AZLD2W,
  5186  			fixedBits: 0xa520e000,
  5187  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S_,
  5188  		},
  5189  	},
  5190  	// ZLD3B
  5191  	{
  5192  		// ZLD3B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
  5193  		{
  5194  			goOp:      AZLD3B,
  5195  			fixedBits: 0xa440c000,
  5196  			args:      XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_,
  5197  		},
  5198  		// ZLD3B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
  5199  		{
  5200  			goOp:      AZLD3B,
  5201  			fixedBits: 0xa440e000,
  5202  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B_,
  5203  		},
  5204  	},
  5205  	// ZLD3D
  5206  	{
  5207  		// ZLD3D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
  5208  		{
  5209  			goOp:      AZLD3D,
  5210  			fixedBits: 0xa5c0c000,
  5211  			args:      XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_,
  5212  		},
  5213  		// ZLD3D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
  5214  		{
  5215  			goOp:      AZLD3D,
  5216  			fixedBits: 0xa5c0e000,
  5217  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D_,
  5218  		},
  5219  	},
  5220  	// ZLD3H
  5221  	{
  5222  		// ZLD3H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
  5223  		{
  5224  			goOp:      AZLD3H,
  5225  			fixedBits: 0xa4c0c000,
  5226  			args:      XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_,
  5227  		},
  5228  		// ZLD3H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
  5229  		{
  5230  			goOp:      AZLD3H,
  5231  			fixedBits: 0xa4c0e000,
  5232  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H_,
  5233  		},
  5234  	},
  5235  	// ZLD3Q
  5236  	{
  5237  		// ZLD3Q [<Xn|SP>, <Xm>, LSL #4], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
  5238  		{
  5239  			goOp:      AZLD3Q,
  5240  			fixedBits: 0xa5208000,
  5241  			args:      XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_,
  5242  		},
  5243  		// ZLD3Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
  5244  		{
  5245  			goOp:      AZLD3Q,
  5246  			fixedBits: 0xa510e000,
  5247  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_,
  5248  		},
  5249  	},
  5250  	// ZLD3W
  5251  	{
  5252  		// ZLD3W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
  5253  		{
  5254  			goOp:      AZLD3W,
  5255  			fixedBits: 0xa540c000,
  5256  			args:      XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_,
  5257  		},
  5258  		// ZLD3W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
  5259  		{
  5260  			goOp:      AZLD3W,
  5261  			fixedBits: 0xa540e000,
  5262  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S_,
  5263  		},
  5264  	},
  5265  	// ZLD4B
  5266  	{
  5267  		// ZLD4B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
  5268  		{
  5269  			goOp:      AZLD4B,
  5270  			fixedBits: 0xa460c000,
  5271  			args:      XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
  5272  		},
  5273  		// ZLD4B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
  5274  		{
  5275  			goOp:      AZLD4B,
  5276  			fixedBits: 0xa460e000,
  5277  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
  5278  		},
  5279  	},
  5280  	// ZLD4D
  5281  	{
  5282  		// ZLD4D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
  5283  		{
  5284  			goOp:      AZLD4D,
  5285  			fixedBits: 0xa5e0c000,
  5286  			args:      XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
  5287  		},
  5288  		// ZLD4D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
  5289  		{
  5290  			goOp:      AZLD4D,
  5291  			fixedBits: 0xa5e0e000,
  5292  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
  5293  		},
  5294  	},
  5295  	// ZLD4H
  5296  	{
  5297  		// ZLD4H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
  5298  		{
  5299  			goOp:      AZLD4H,
  5300  			fixedBits: 0xa4e0c000,
  5301  			args:      XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
  5302  		},
  5303  		// ZLD4H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
  5304  		{
  5305  			goOp:      AZLD4H,
  5306  			fixedBits: 0xa4e0e000,
  5307  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
  5308  		},
  5309  	},
  5310  	// ZLD4Q
  5311  	{
  5312  		// ZLD4Q [<Xn|SP>, <Xm>, LSL #4], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
  5313  		{
  5314  			goOp:      AZLD4Q,
  5315  			fixedBits: 0xa5a08000,
  5316  			args:      XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
  5317  		},
  5318  		// ZLD4Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
  5319  		{
  5320  			goOp:      AZLD4Q,
  5321  			fixedBits: 0xa590e000,
  5322  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
  5323  		},
  5324  	},
  5325  	// ZLD4W
  5326  	{
  5327  		// ZLD4W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
  5328  		{
  5329  			goOp:      AZLD4W,
  5330  			fixedBits: 0xa560c000,
  5331  			args:      XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
  5332  		},
  5333  		// ZLD4W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
  5334  		{
  5335  			goOp:      AZLD4W,
  5336  			fixedBits: 0xa560e000,
  5337  			args:      XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
  5338  		},
  5339  	},
  5340  	// ZLDFF1B
  5341  	{
  5342  		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.B }
  5343  		{
  5344  			goOp:      AZLDFF1B,
  5345  			fixedBits: 0xa4006000,
  5346  			args:      XnSP__Xm___PgZ___Zt_B__V2,
  5347  		},
  5348  		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.D }
  5349  		{
  5350  			goOp:      AZLDFF1B,
  5351  			fixedBits: 0xa4606000,
  5352  			args:      XnSP__Xm___PgZ___Zt_D__V2,
  5353  		},
  5354  		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.H }
  5355  		{
  5356  			goOp:      AZLDFF1B,
  5357  			fixedBits: 0xa4206000,
  5358  			args:      XnSP__Xm___PgZ___Zt_H__V2,
  5359  		},
  5360  		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.S }
  5361  		{
  5362  			goOp:      AZLDFF1B,
  5363  			fixedBits: 0xa4406000,
  5364  			args:      XnSP__Xm___PgZ___Zt_S__V2,
  5365  		},
  5366  		// ZLDFF1B [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5367  		{
  5368  			goOp:      AZLDFF1B,
  5369  			fixedBits: 0xc440e000,
  5370  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5371  		},
  5372  		// ZLDFF1B [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5373  		{
  5374  			goOp:      AZLDFF1B,
  5375  			fixedBits: 0xc4006000,
  5376  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5377  		},
  5378  		// ZLDFF1B [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  5379  		{
  5380  			goOp:      AZLDFF1B,
  5381  			fixedBits: 0x84006000,
  5382  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  5383  		},
  5384  		// ZLDFF1B [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5385  		{
  5386  			goOp:      AZLDFF1B,
  5387  			fixedBits: 0xc420e000,
  5388  			args:      Zn_D__cimm___PgZ___Zt_D___1,
  5389  		},
  5390  		// ZLDFF1B [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  5391  		{
  5392  			goOp:      AZLDFF1B,
  5393  			fixedBits: 0x8420e000,
  5394  			args:      Zn_S__cimm___PgZ___Zt_S___1,
  5395  		},
  5396  	},
  5397  	// ZLDFF1D
  5398  	{
  5399  		// ZLDFF1D [<Xn|SP>{, <Xm>, LSL #3}], <Pg>/Z, { <Zt>.D }
  5400  		{
  5401  			goOp:      AZLDFF1D,
  5402  			fixedBits: 0xa5e06000,
  5403  			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D__V2,
  5404  		},
  5405  		// ZLDFF1D [<Xn|SP>, <Zm>.D, LSL #3], <Pg>/Z, { <Zt>.D }
  5406  		{
  5407  			goOp:      AZLDFF1D,
  5408  			fixedBits: 0xc5e0e000,
  5409  			args:      XnSP__Zm_D__LSL_c3___PgZ___Zt_D_,
  5410  		},
  5411  		// ZLDFF1D [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5412  		{
  5413  			goOp:      AZLDFF1D,
  5414  			fixedBits: 0xc5c0e000,
  5415  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5416  		},
  5417  		// ZLDFF1D [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5418  		{
  5419  			goOp:      AZLDFF1D,
  5420  			fixedBits: 0xc5806000,
  5421  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5422  		},
  5423  		// ZLDFF1D [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>/Z, { <Zt>.D }
  5424  		{
  5425  			goOp:      AZLDFF1D,
  5426  			fixedBits: 0xc5a06000,
  5427  			args:      XnSP__Zm_D__mod_c3___PgZ___Zt_D_,
  5428  		},
  5429  		// ZLDFF1D [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5430  		{
  5431  			goOp:      AZLDFF1D,
  5432  			fixedBits: 0xc5a0e000,
  5433  			args:      Zn_D__cimm___PgZ___Zt_D___4,
  5434  		},
  5435  	},
  5436  	// ZLDFF1H
  5437  	{
  5438  		// ZLDFF1H [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.D }
  5439  		{
  5440  			goOp:      AZLDFF1H,
  5441  			fixedBits: 0xa4e06000,
  5442  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D__V2,
  5443  		},
  5444  		// ZLDFF1H [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.H }
  5445  		{
  5446  			goOp:      AZLDFF1H,
  5447  			fixedBits: 0xa4a06000,
  5448  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H__V2,
  5449  		},
  5450  		// ZLDFF1H [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.S }
  5451  		{
  5452  			goOp:      AZLDFF1H,
  5453  			fixedBits: 0xa4c06000,
  5454  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S__V2,
  5455  		},
  5456  		// ZLDFF1H [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
  5457  		{
  5458  			goOp:      AZLDFF1H,
  5459  			fixedBits: 0xc4e0e000,
  5460  			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
  5461  		},
  5462  		// ZLDFF1H [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5463  		{
  5464  			goOp:      AZLDFF1H,
  5465  			fixedBits: 0xc4c0e000,
  5466  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5467  		},
  5468  		// ZLDFF1H [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5469  		{
  5470  			goOp:      AZLDFF1H,
  5471  			fixedBits: 0xc4806000,
  5472  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5473  		},
  5474  		// ZLDFF1H [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
  5475  		{
  5476  			goOp:      AZLDFF1H,
  5477  			fixedBits: 0xc4a06000,
  5478  			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
  5479  		},
  5480  		// ZLDFF1H [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  5481  		{
  5482  			goOp:      AZLDFF1H,
  5483  			fixedBits: 0x84806000,
  5484  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  5485  		},
  5486  		// ZLDFF1H [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
  5487  		{
  5488  			goOp:      AZLDFF1H,
  5489  			fixedBits: 0x84a06000,
  5490  			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
  5491  		},
  5492  		// ZLDFF1H [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5493  		{
  5494  			goOp:      AZLDFF1H,
  5495  			fixedBits: 0xc4a0e000,
  5496  			args:      Zn_D__cimm___PgZ___Zt_D___2,
  5497  		},
  5498  		// ZLDFF1H [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  5499  		{
  5500  			goOp:      AZLDFF1H,
  5501  			fixedBits: 0x84a0e000,
  5502  			args:      Zn_S__cimm___PgZ___Zt_S___2,
  5503  		},
  5504  	},
  5505  	// ZLDFF1SB
  5506  	{
  5507  		// ZLDFF1SB [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.D }
  5508  		{
  5509  			goOp:      AZLDFF1SB,
  5510  			fixedBits: 0xa5806000,
  5511  			args:      XnSP__Xm___PgZ___Zt_D__V2,
  5512  		},
  5513  		// ZLDFF1SB [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.H }
  5514  		{
  5515  			goOp:      AZLDFF1SB,
  5516  			fixedBits: 0xa5c06000,
  5517  			args:      XnSP__Xm___PgZ___Zt_H__V2,
  5518  		},
  5519  		// ZLDFF1SB [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.S }
  5520  		{
  5521  			goOp:      AZLDFF1SB,
  5522  			fixedBits: 0xa5a06000,
  5523  			args:      XnSP__Xm___PgZ___Zt_S__V2,
  5524  		},
  5525  		// ZLDFF1SB [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5526  		{
  5527  			goOp:      AZLDFF1SB,
  5528  			fixedBits: 0xc440a000,
  5529  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5530  		},
  5531  		// ZLDFF1SB [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5532  		{
  5533  			goOp:      AZLDFF1SB,
  5534  			fixedBits: 0xc4002000,
  5535  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5536  		},
  5537  		// ZLDFF1SB [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  5538  		{
  5539  			goOp:      AZLDFF1SB,
  5540  			fixedBits: 0x84002000,
  5541  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  5542  		},
  5543  		// ZLDFF1SB [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5544  		{
  5545  			goOp:      AZLDFF1SB,
  5546  			fixedBits: 0xc420a000,
  5547  			args:      Zn_D__cimm___PgZ___Zt_D___1,
  5548  		},
  5549  		// ZLDFF1SB [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  5550  		{
  5551  			goOp:      AZLDFF1SB,
  5552  			fixedBits: 0x8420a000,
  5553  			args:      Zn_S__cimm___PgZ___Zt_S___1,
  5554  		},
  5555  	},
  5556  	// ZLDFF1SH
  5557  	{
  5558  		// ZLDFF1SH [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.D }
  5559  		{
  5560  			goOp:      AZLDFF1SH,
  5561  			fixedBits: 0xa5006000,
  5562  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D__V2,
  5563  		},
  5564  		// ZLDFF1SH [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.S }
  5565  		{
  5566  			goOp:      AZLDFF1SH,
  5567  			fixedBits: 0xa5206000,
  5568  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S__V2,
  5569  		},
  5570  		// ZLDFF1SH [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
  5571  		{
  5572  			goOp:      AZLDFF1SH,
  5573  			fixedBits: 0xc4e0a000,
  5574  			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
  5575  		},
  5576  		// ZLDFF1SH [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5577  		{
  5578  			goOp:      AZLDFF1SH,
  5579  			fixedBits: 0xc4c0a000,
  5580  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5581  		},
  5582  		// ZLDFF1SH [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5583  		{
  5584  			goOp:      AZLDFF1SH,
  5585  			fixedBits: 0xc4802000,
  5586  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5587  		},
  5588  		// ZLDFF1SH [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
  5589  		{
  5590  			goOp:      AZLDFF1SH,
  5591  			fixedBits: 0xc4a02000,
  5592  			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
  5593  		},
  5594  		// ZLDFF1SH [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  5595  		{
  5596  			goOp:      AZLDFF1SH,
  5597  			fixedBits: 0x84802000,
  5598  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  5599  		},
  5600  		// ZLDFF1SH [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
  5601  		{
  5602  			goOp:      AZLDFF1SH,
  5603  			fixedBits: 0x84a02000,
  5604  			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
  5605  		},
  5606  		// ZLDFF1SH [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5607  		{
  5608  			goOp:      AZLDFF1SH,
  5609  			fixedBits: 0xc4a0a000,
  5610  			args:      Zn_D__cimm___PgZ___Zt_D___2,
  5611  		},
  5612  		// ZLDFF1SH [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  5613  		{
  5614  			goOp:      AZLDFF1SH,
  5615  			fixedBits: 0x84a0a000,
  5616  			args:      Zn_S__cimm___PgZ___Zt_S___2,
  5617  		},
  5618  	},
  5619  	// ZLDFF1SW
  5620  	{
  5621  		// ZLDFF1SW [<Xn|SP>{, <Xm>, LSL #2}], <Pg>/Z, { <Zt>.D }
  5622  		{
  5623  			goOp:      AZLDFF1SW,
  5624  			fixedBits: 0xa4806000,
  5625  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_D__V2,
  5626  		},
  5627  		// ZLDFF1SW [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
  5628  		{
  5629  			goOp:      AZLDFF1SW,
  5630  			fixedBits: 0xc560a000,
  5631  			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
  5632  		},
  5633  		// ZLDFF1SW [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5634  		{
  5635  			goOp:      AZLDFF1SW,
  5636  			fixedBits: 0xc540a000,
  5637  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5638  		},
  5639  		// ZLDFF1SW [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5640  		{
  5641  			goOp:      AZLDFF1SW,
  5642  			fixedBits: 0xc5002000,
  5643  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5644  		},
  5645  		// ZLDFF1SW [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
  5646  		{
  5647  			goOp:      AZLDFF1SW,
  5648  			fixedBits: 0xc5202000,
  5649  			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
  5650  		},
  5651  		// ZLDFF1SW [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5652  		{
  5653  			goOp:      AZLDFF1SW,
  5654  			fixedBits: 0xc520a000,
  5655  			args:      Zn_D__cimm___PgZ___Zt_D___3,
  5656  		},
  5657  	},
  5658  	// ZLDFF1W
  5659  	{
  5660  		// ZLDFF1W [<Xn|SP>{, <Xm>, LSL #2}], <Pg>/Z, { <Zt>.D }
  5661  		{
  5662  			goOp:      AZLDFF1W,
  5663  			fixedBits: 0xa5606000,
  5664  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_D__V2,
  5665  		},
  5666  		// ZLDFF1W [<Xn|SP>{, <Xm>, LSL #2}], <Pg>/Z, { <Zt>.S }
  5667  		{
  5668  			goOp:      AZLDFF1W,
  5669  			fixedBits: 0xa5406000,
  5670  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S__V2,
  5671  		},
  5672  		// ZLDFF1W [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
  5673  		{
  5674  			goOp:      AZLDFF1W,
  5675  			fixedBits: 0xc560e000,
  5676  			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
  5677  		},
  5678  		// ZLDFF1W [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
  5679  		{
  5680  			goOp:      AZLDFF1W,
  5681  			fixedBits: 0xc540e000,
  5682  			args:      XnSP__Zm_D___PgZ___Zt_D_,
  5683  		},
  5684  		// ZLDFF1W [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
  5685  		{
  5686  			goOp:      AZLDFF1W,
  5687  			fixedBits: 0xc5006000,
  5688  			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
  5689  		},
  5690  		// ZLDFF1W [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
  5691  		{
  5692  			goOp:      AZLDFF1W,
  5693  			fixedBits: 0xc5206000,
  5694  			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
  5695  		},
  5696  		// ZLDFF1W [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
  5697  		{
  5698  			goOp:      AZLDFF1W,
  5699  			fixedBits: 0x85006000,
  5700  			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
  5701  		},
  5702  		// ZLDFF1W [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>/Z, { <Zt>.S }
  5703  		{
  5704  			goOp:      AZLDFF1W,
  5705  			fixedBits: 0x85206000,
  5706  			args:      XnSP__Zm_S__mod_c2___PgZ___Zt_S_,
  5707  		},
  5708  		// ZLDFF1W [<Zn>.D{, #<imm>}], <Pg>/Z, { <Zt>.D }
  5709  		{
  5710  			goOp:      AZLDFF1W,
  5711  			fixedBits: 0xc520e000,
  5712  			args:      Zn_D__cimm___PgZ___Zt_D___3,
  5713  		},
  5714  		// ZLDFF1W [<Zn>.S{, #<imm>}], <Pg>/Z, { <Zt>.S }
  5715  		{
  5716  			goOp:      AZLDFF1W,
  5717  			fixedBits: 0x8520e000,
  5718  			args:      Zn_S__cimm___PgZ___Zt_S___3,
  5719  		},
  5720  	},
  5721  	// ZLDNF1B
  5722  	{
  5723  		// ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.B }
  5724  		{
  5725  			goOp:      AZLDNF1B,
  5726  			fixedBits: 0xa410a000,
  5727  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_B_,
  5728  		},
  5729  		// ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5730  		{
  5731  			goOp:      AZLDNF1B,
  5732  			fixedBits: 0xa470a000,
  5733  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5734  		},
  5735  		// ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
  5736  		{
  5737  			goOp:      AZLDNF1B,
  5738  			fixedBits: 0xa430a000,
  5739  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_H_,
  5740  		},
  5741  		// ZLDNF1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  5742  		{
  5743  			goOp:      AZLDNF1B,
  5744  			fixedBits: 0xa450a000,
  5745  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  5746  		},
  5747  	},
  5748  	// ZLDNF1D
  5749  	{
  5750  		// ZLDNF1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5751  		{
  5752  			goOp:      AZLDNF1D,
  5753  			fixedBits: 0xa5f0a000,
  5754  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5755  		},
  5756  	},
  5757  	// ZLDNF1H
  5758  	{
  5759  		// ZLDNF1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5760  		{
  5761  			goOp:      AZLDNF1H,
  5762  			fixedBits: 0xa4f0a000,
  5763  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5764  		},
  5765  		// ZLDNF1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
  5766  		{
  5767  			goOp:      AZLDNF1H,
  5768  			fixedBits: 0xa4b0a000,
  5769  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_H_,
  5770  		},
  5771  		// ZLDNF1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  5772  		{
  5773  			goOp:      AZLDNF1H,
  5774  			fixedBits: 0xa4d0a000,
  5775  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  5776  		},
  5777  	},
  5778  	// ZLDNF1SB
  5779  	{
  5780  		// ZLDNF1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5781  		{
  5782  			goOp:      AZLDNF1SB,
  5783  			fixedBits: 0xa590a000,
  5784  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5785  		},
  5786  		// ZLDNF1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
  5787  		{
  5788  			goOp:      AZLDNF1SB,
  5789  			fixedBits: 0xa5d0a000,
  5790  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_H_,
  5791  		},
  5792  		// ZLDNF1SB [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  5793  		{
  5794  			goOp:      AZLDNF1SB,
  5795  			fixedBits: 0xa5b0a000,
  5796  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  5797  		},
  5798  	},
  5799  	// ZLDNF1SH
  5800  	{
  5801  		// ZLDNF1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5802  		{
  5803  			goOp:      AZLDNF1SH,
  5804  			fixedBits: 0xa510a000,
  5805  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5806  		},
  5807  		// ZLDNF1SH [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  5808  		{
  5809  			goOp:      AZLDNF1SH,
  5810  			fixedBits: 0xa530a000,
  5811  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  5812  		},
  5813  	},
  5814  	// ZLDNF1SW
  5815  	{
  5816  		// ZLDNF1SW [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5817  		{
  5818  			goOp:      AZLDNF1SW,
  5819  			fixedBits: 0xa490a000,
  5820  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5821  		},
  5822  	},
  5823  	// ZLDNF1W
  5824  	{
  5825  		// ZLDNF1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5826  		{
  5827  			goOp:      AZLDNF1W,
  5828  			fixedBits: 0xa570a000,
  5829  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5830  		},
  5831  		// ZLDNF1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  5832  		{
  5833  			goOp:      AZLDNF1W,
  5834  			fixedBits: 0xa550a000,
  5835  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  5836  		},
  5837  	},
  5838  	// ZLDNT1B
  5839  	{
  5840  		// ZLDNT1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
  5841  		{
  5842  			goOp:      AZLDNT1B,
  5843  			fixedBits: 0xa400c000,
  5844  			args:      XnSP__Xm___PgZ___Zt_B_,
  5845  		},
  5846  		// ZLDNT1B [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
  5847  		{
  5848  			goOp:      AZLDNT1B,
  5849  			fixedBits: 0xc400c000,
  5850  			args:      Zn_D__Xm___PgZ___Zt_D_,
  5851  		},
  5852  		// ZLDNT1B [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
  5853  		{
  5854  			goOp:      AZLDNT1B,
  5855  			fixedBits: 0x8400a000,
  5856  			args:      Zn_S__Xm___PgZ___Zt_S_,
  5857  		},
  5858  		// ZLDNT1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.B }
  5859  		{
  5860  			goOp:      AZLDNT1B,
  5861  			fixedBits: 0xa400e000,
  5862  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_B_,
  5863  		},
  5864  		// ZLDNT1B [<Xn|SP>, <Xm>], <PNg>/Z, { <Zt1>.B-<Zt2>.B }
  5865  		{
  5866  			goOp:      AZLDNT1B,
  5867  			fixedBits: 0xa0000001,
  5868  			args:      XnSP__Xm___PNgZ___Zt1_B_Zt2_B_,
  5869  		},
  5870  		// ZLDNT1B [<Xn|SP>, <Xm>], <PNg>/Z, { <Zt1>.B-<Zt4>.B }
  5871  		{
  5872  			goOp:      AZLDNT1B,
  5873  			fixedBits: 0xa0008001,
  5874  			args:      XnSP__Xm___PNgZ___Zt1_B_Zt4_B_,
  5875  		},
  5876  		// ZLDNT1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.B-<Zt2>.B }
  5877  		{
  5878  			goOp:      AZLDNT1B,
  5879  			fixedBits: 0xa0400001,
  5880  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt2_B_,
  5881  		},
  5882  		// ZLDNT1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.B-<Zt4>.B }
  5883  		{
  5884  			goOp:      AZLDNT1B,
  5885  			fixedBits: 0xa0408001,
  5886  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt4_B_,
  5887  		},
  5888  	},
  5889  	// ZLDNT1D
  5890  	{
  5891  		// ZLDNT1D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.D }
  5892  		{
  5893  			goOp:      AZLDNT1D,
  5894  			fixedBits: 0xa580c000,
  5895  			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
  5896  		},
  5897  		// ZLDNT1D [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
  5898  		{
  5899  			goOp:      AZLDNT1D,
  5900  			fixedBits: 0xc580c000,
  5901  			args:      Zn_D__Xm___PgZ___Zt_D_,
  5902  		},
  5903  		// ZLDNT1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.D }
  5904  		{
  5905  			goOp:      AZLDNT1D,
  5906  			fixedBits: 0xa580e000,
  5907  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_D_,
  5908  		},
  5909  		// ZLDNT1D [<Xn|SP>, <Xm>, LSL #3], <PNg>/Z, { <Zt1>.D-<Zt2>.D }
  5910  		{
  5911  			goOp:      AZLDNT1D,
  5912  			fixedBits: 0xa0006001,
  5913  			args:      XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt2_D_,
  5914  		},
  5915  		// ZLDNT1D [<Xn|SP>, <Xm>, LSL #3], <PNg>/Z, { <Zt1>.D-<Zt4>.D }
  5916  		{
  5917  			goOp:      AZLDNT1D,
  5918  			fixedBits: 0xa000e001,
  5919  			args:      XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt4_D_,
  5920  		},
  5921  		// ZLDNT1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.D-<Zt2>.D }
  5922  		{
  5923  			goOp:      AZLDNT1D,
  5924  			fixedBits: 0xa0406001,
  5925  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt2_D_,
  5926  		},
  5927  		// ZLDNT1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.D-<Zt4>.D }
  5928  		{
  5929  			goOp:      AZLDNT1D,
  5930  			fixedBits: 0xa040e001,
  5931  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt4_D_,
  5932  		},
  5933  	},
  5934  	// ZLDNT1H
  5935  	{
  5936  		// ZLDNT1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
  5937  		{
  5938  			goOp:      AZLDNT1H,
  5939  			fixedBits: 0xa480c000,
  5940  			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
  5941  		},
  5942  		// ZLDNT1H [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
  5943  		{
  5944  			goOp:      AZLDNT1H,
  5945  			fixedBits: 0xc480c000,
  5946  			args:      Zn_D__Xm___PgZ___Zt_D_,
  5947  		},
  5948  		// ZLDNT1H [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
  5949  		{
  5950  			goOp:      AZLDNT1H,
  5951  			fixedBits: 0x8480a000,
  5952  			args:      Zn_S__Xm___PgZ___Zt_S_,
  5953  		},
  5954  		// ZLDNT1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.H }
  5955  		{
  5956  			goOp:      AZLDNT1H,
  5957  			fixedBits: 0xa480e000,
  5958  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_H_,
  5959  		},
  5960  		// ZLDNT1H [<Xn|SP>, <Xm>, LSL #1], <PNg>/Z, { <Zt1>.H-<Zt2>.H }
  5961  		{
  5962  			goOp:      AZLDNT1H,
  5963  			fixedBits: 0xa0002001,
  5964  			args:      XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt2_H_,
  5965  		},
  5966  		// ZLDNT1H [<Xn|SP>, <Xm>, LSL #1], <PNg>/Z, { <Zt1>.H-<Zt4>.H }
  5967  		{
  5968  			goOp:      AZLDNT1H,
  5969  			fixedBits: 0xa000a001,
  5970  			args:      XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt4_H_,
  5971  		},
  5972  		// ZLDNT1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.H-<Zt2>.H }
  5973  		{
  5974  			goOp:      AZLDNT1H,
  5975  			fixedBits: 0xa0402001,
  5976  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt2_H_,
  5977  		},
  5978  		// ZLDNT1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.H-<Zt4>.H }
  5979  		{
  5980  			goOp:      AZLDNT1H,
  5981  			fixedBits: 0xa040a001,
  5982  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt4_H_,
  5983  		},
  5984  	},
  5985  	// ZLDNT1SB
  5986  	{
  5987  		// ZLDNT1SB [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
  5988  		{
  5989  			goOp:      AZLDNT1SB,
  5990  			fixedBits: 0xc4008000,
  5991  			args:      Zn_D__Xm___PgZ___Zt_D_,
  5992  		},
  5993  		// ZLDNT1SB [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
  5994  		{
  5995  			goOp:      AZLDNT1SB,
  5996  			fixedBits: 0x84008000,
  5997  			args:      Zn_S__Xm___PgZ___Zt_S_,
  5998  		},
  5999  	},
  6000  	// ZLDNT1SH
  6001  	{
  6002  		// ZLDNT1SH [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
  6003  		{
  6004  			goOp:      AZLDNT1SH,
  6005  			fixedBits: 0xc4808000,
  6006  			args:      Zn_D__Xm___PgZ___Zt_D_,
  6007  		},
  6008  		// ZLDNT1SH [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
  6009  		{
  6010  			goOp:      AZLDNT1SH,
  6011  			fixedBits: 0x84808000,
  6012  			args:      Zn_S__Xm___PgZ___Zt_S_,
  6013  		},
  6014  	},
  6015  	// ZLDNT1SW
  6016  	{
  6017  		// ZLDNT1SW [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
  6018  		{
  6019  			goOp:      AZLDNT1SW,
  6020  			fixedBits: 0xc5008000,
  6021  			args:      Zn_D__Xm___PgZ___Zt_D_,
  6022  		},
  6023  	},
  6024  	// ZLDNT1W
  6025  	{
  6026  		// ZLDNT1W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.S }
  6027  		{
  6028  			goOp:      AZLDNT1W,
  6029  			fixedBits: 0xa500c000,
  6030  			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
  6031  		},
  6032  		// ZLDNT1W [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
  6033  		{
  6034  			goOp:      AZLDNT1W,
  6035  			fixedBits: 0xc500c000,
  6036  			args:      Zn_D__Xm___PgZ___Zt_D_,
  6037  		},
  6038  		// ZLDNT1W [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
  6039  		{
  6040  			goOp:      AZLDNT1W,
  6041  			fixedBits: 0x8500a000,
  6042  			args:      Zn_S__Xm___PgZ___Zt_S_,
  6043  		},
  6044  		// ZLDNT1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>/Z, { <Zt>.S }
  6045  		{
  6046  			goOp:      AZLDNT1W,
  6047  			fixedBits: 0xa500e000,
  6048  			args:      XnSP__cimm__MUL_VL___PgZ___Zt_S_,
  6049  		},
  6050  		// ZLDNT1W [<Xn|SP>, <Xm>, LSL #2], <PNg>/Z, { <Zt1>.S-<Zt2>.S }
  6051  		{
  6052  			goOp:      AZLDNT1W,
  6053  			fixedBits: 0xa0004001,
  6054  			args:      XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt2_S_,
  6055  		},
  6056  		// ZLDNT1W [<Xn|SP>, <Xm>, LSL #2], <PNg>/Z, { <Zt1>.S-<Zt4>.S }
  6057  		{
  6058  			goOp:      AZLDNT1W,
  6059  			fixedBits: 0xa000c001,
  6060  			args:      XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt4_S_,
  6061  		},
  6062  		// ZLDNT1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.S-<Zt2>.S }
  6063  		{
  6064  			goOp:      AZLDNT1W,
  6065  			fixedBits: 0xa0404001,
  6066  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt2_S_,
  6067  		},
  6068  		// ZLDNT1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>/Z, { <Zt1>.S-<Zt4>.S }
  6069  		{
  6070  			goOp:      AZLDNT1W,
  6071  			fixedBits: 0xa040c001,
  6072  			args:      XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt4_S_,
  6073  		},
  6074  	},
  6075  	// ZLDR
  6076  	{
  6077  		// ZLDR [<Xn|SP>{, #<imm>, MUL VL}], <Zt>
  6078  		{
  6079  			goOp:      AZLDR,
  6080  			fixedBits: 0x85804000,
  6081  			args:      XnSP__cimm__MUL_VL___Zt,
  6082  		},
  6083  	},
  6084  	// ZLSL
  6085  	{
  6086  		// ZLSL <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6087  		{
  6088  			goOp:      AZLSL,
  6089  			fixedBits: 0x41b8000,
  6090  			args:      Zm_D__Zdn_T__PgM__Zdn_T,
  6091  		},
  6092  		// ZLSL <Zm>.D, <Zn>.<T>, <Zd>.<T>
  6093  		{
  6094  			goOp:      AZLSL,
  6095  			fixedBits: 0x4208c00,
  6096  			args:      Zm_D__Zn_T__Zd_T,
  6097  		},
  6098  		// ZLSL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6099  		{
  6100  			goOp:      AZLSL,
  6101  			fixedBits: 0x4138000,
  6102  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  6103  		},
  6104  		// ZLSL #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6105  		{
  6106  			goOp:      AZLSL,
  6107  			fixedBits: 0x4038000,
  6108  			args:      cconst__Zdn_T__PgM__Zdn_T__2,
  6109  		},
  6110  		// ZLSL #<const>, <Zn>.<T>, <Zd>.<T>
  6111  		{
  6112  			goOp:      AZLSL,
  6113  			fixedBits: 0x4209c00,
  6114  			args:      cconst__Zn_T__Zd_T__2,
  6115  		},
  6116  	},
  6117  	// ZLSLR
  6118  	{
  6119  		// ZLSLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6120  		{
  6121  			goOp:      AZLSLR,
  6122  			fixedBits: 0x4178000,
  6123  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  6124  		},
  6125  	},
  6126  	// ZLSR
  6127  	{
  6128  		// ZLSR <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6129  		{
  6130  			goOp:      AZLSR,
  6131  			fixedBits: 0x4198000,
  6132  			args:      Zm_D__Zdn_T__PgM__Zdn_T,
  6133  		},
  6134  		// ZLSR <Zm>.D, <Zn>.<T>, <Zd>.<T>
  6135  		{
  6136  			goOp:      AZLSR,
  6137  			fixedBits: 0x4208400,
  6138  			args:      Zm_D__Zn_T__Zd_T,
  6139  		},
  6140  		// ZLSR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6141  		{
  6142  			goOp:      AZLSR,
  6143  			fixedBits: 0x4118000,
  6144  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  6145  		},
  6146  		// ZLSR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6147  		{
  6148  			goOp:      AZLSR,
  6149  			fixedBits: 0x4018000,
  6150  			args:      cconst__Zdn_T__PgM__Zdn_T__1,
  6151  		},
  6152  		// ZLSR #<const>, <Zn>.<T>, <Zd>.<T>
  6153  		{
  6154  			goOp:      AZLSR,
  6155  			fixedBits: 0x4209400,
  6156  			args:      cconst__Zn_T__Zd_T__1,
  6157  		},
  6158  	},
  6159  	// ZLSRR
  6160  	{
  6161  		// ZLSRR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6162  		{
  6163  			goOp:      AZLSRR,
  6164  			fixedBits: 0x4158000,
  6165  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  6166  		},
  6167  	},
  6168  	// ZLUTI2
  6169  	{
  6170  		// ZLUTI2 <Zm>[<index>], { <Zn>.B }, <Zd>.B
  6171  		{
  6172  			goOp:      AZLUTI2,
  6173  			fixedBits: 0x4520b000,
  6174  			args:      Zm_index____Zn_B___Zd_B__1,
  6175  		},
  6176  		// ZLUTI2 <Zm>[<index>], { <Zn>.H }, <Zd>.H
  6177  		{
  6178  			goOp:      AZLUTI2,
  6179  			fixedBits: 0x4520a800,
  6180  			args:      Zm_index____Zn_H___Zd_H__1,
  6181  		},
  6182  	},
  6183  	// ZLUTI4
  6184  	{
  6185  		// ZLUTI4 <Zm>[<index>], { <Zn1>.H, <Zn2>.H }, <Zd>.H
  6186  		{
  6187  			goOp:      AZLUTI4,
  6188  			fixedBits: 0x4520b400,
  6189  			args:      Zm_index____Zn1_H__Zn2_H___Zd_H__1,
  6190  		},
  6191  		// ZLUTI4 <Zm>[<index>], { <Zn>.B }, <Zd>.B
  6192  		{
  6193  			goOp:      AZLUTI4,
  6194  			fixedBits: 0x4560a400,
  6195  			args:      Zm_index____Zn_B___Zd_B__2,
  6196  		},
  6197  		// ZLUTI4 <Zm>[<index>], { <Zn>.H }, <Zd>.H
  6198  		{
  6199  			goOp:      AZLUTI4,
  6200  			fixedBits: 0x4520bc00,
  6201  			args:      Zm_index____Zn_H___Zd_H__2,
  6202  		},
  6203  	},
  6204  	// ZLUTI6
  6205  	{
  6206  		// ZLUTI6 <Zm>, { <Zn1>.B, <Zn2>.B }, <Zd>.B
  6207  		{
  6208  			goOp:      AZLUTI6,
  6209  			fixedBits: 0x4520ac00,
  6210  			args:      Zm___Zn1_B__Zn2_B___Zd_B,
  6211  		},
  6212  		// ZLUTI6 <Zm>[<index>], { <Zn1>.H, <Zn2>.H }, <Zd>.H
  6213  		{
  6214  			goOp:      AZLUTI6,
  6215  			fixedBits: 0x4560ac00,
  6216  			args:      Zm_index____Zn1_H__Zn2_H___Zd_H__2,
  6217  		},
  6218  	},
  6219  	// ZMAD
  6220  	{
  6221  		// ZMAD <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
  6222  		{
  6223  			goOp:      AZMAD,
  6224  			fixedBits: 0x400c000,
  6225  			args:      Za_T__Zm_T__PgM__Zdn_T__2,
  6226  		},
  6227  	},
  6228  	// ZMADPT
  6229  	{
  6230  		// ZMADPT <Za>.D, <Zm>.D, <Zdn>.D
  6231  		{
  6232  			goOp:      AZMADPT,
  6233  			fixedBits: 0x44c0d800,
  6234  			args:      Za_D__Zm_D__Zdn_D,
  6235  		},
  6236  	},
  6237  	// ZMATCH
  6238  	{
  6239  		// ZMATCH <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  6240  		{
  6241  			goOp:      AZMATCH,
  6242  			fixedBits: 0x45208000,
  6243  			args:      Zm_T__Zn_T__PgZ__Pd_T__3,
  6244  		},
  6245  	},
  6246  	// ZMLA
  6247  	{
  6248  		// ZMLA <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
  6249  		{
  6250  			goOp:      AZMLA,
  6251  			fixedBits: 0x4004000,
  6252  			args:      Zm_T__Zn_T__PgM__Zda_T__2,
  6253  		},
  6254  		// ZMLA <Zm>.D[<imm>], <Zn>.D, <Zda>.D
  6255  		{
  6256  			goOp:      AZMLA,
  6257  			fixedBits: 0x44e00800,
  6258  			args:      Zm_D_imm___Zn_D__Zda_D__1,
  6259  		},
  6260  		// ZMLA <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  6261  		{
  6262  			goOp:      AZMLA,
  6263  			fixedBits: 0x44200800,
  6264  			args:      Zm_H_imm___Zn_H__Zda_H__1,
  6265  		},
  6266  		// ZMLA <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  6267  		{
  6268  			goOp:      AZMLA,
  6269  			fixedBits: 0x44a00800,
  6270  			args:      Zm_S_imm___Zn_S__Zda_S__1,
  6271  		},
  6272  	},
  6273  	// ZMLAPT
  6274  	{
  6275  		// ZMLAPT <Zm>.D, <Zn>.D, <Zda>.D
  6276  		{
  6277  			goOp:      AZMLAPT,
  6278  			fixedBits: 0x44c0d000,
  6279  			args:      Zm_D__Zn_D__Zda_D,
  6280  		},
  6281  	},
  6282  	// ZMLS
  6283  	{
  6284  		// ZMLS <Zm>.<T>, <Zn>.<T>, <Pg>/M, <Zda>.<T>
  6285  		{
  6286  			goOp:      AZMLS,
  6287  			fixedBits: 0x4006000,
  6288  			args:      Zm_T__Zn_T__PgM__Zda_T__2,
  6289  		},
  6290  		// ZMLS <Zm>.D[<imm>], <Zn>.D, <Zda>.D
  6291  		{
  6292  			goOp:      AZMLS,
  6293  			fixedBits: 0x44e00c00,
  6294  			args:      Zm_D_imm___Zn_D__Zda_D__1,
  6295  		},
  6296  		// ZMLS <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  6297  		{
  6298  			goOp:      AZMLS,
  6299  			fixedBits: 0x44200c00,
  6300  			args:      Zm_H_imm___Zn_H__Zda_H__1,
  6301  		},
  6302  		// ZMLS <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  6303  		{
  6304  			goOp:      AZMLS,
  6305  			fixedBits: 0x44a00c00,
  6306  			args:      Zm_S_imm___Zn_S__Zda_S__1,
  6307  		},
  6308  	},
  6309  	// ZMOVPRFX
  6310  	{
  6311  		// ZMOVPRFX <Zn>.<T>, <Pg>/<ZM>, <Zd>.<T>
  6312  		{
  6313  			goOp:      AZMOVPRFX,
  6314  			fixedBits: 0x4102000,
  6315  			args:      Zn_T__PgZM__Zd_T,
  6316  		},
  6317  		// ZMOVPRFX <Zn>, <Zd>
  6318  		{
  6319  			goOp:      AZMOVPRFX,
  6320  			fixedBits: 0x420bc00,
  6321  			args:      Zn__Zd,
  6322  		},
  6323  	},
  6324  	// ZMSB
  6325  	{
  6326  		// ZMSB <Za>.<T>, <Zm>.<T>, <Pg>/M, <Zdn>.<T>
  6327  		{
  6328  			goOp:      AZMSB,
  6329  			fixedBits: 0x400e000,
  6330  			args:      Za_T__Zm_T__PgM__Zdn_T__2,
  6331  		},
  6332  	},
  6333  	// ZMUL
  6334  	{
  6335  		// ZMUL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6336  		{
  6337  			goOp:      AZMUL,
  6338  			fixedBits: 0x4100000,
  6339  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  6340  		},
  6341  		// ZMUL <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  6342  		{
  6343  			goOp:      AZMUL,
  6344  			fixedBits: 0x4206000,
  6345  			args:      Zm_T__Zn_T__Zd_T__1,
  6346  		},
  6347  		// ZMUL <Zm>.D[<imm>], <Zn>.D, <Zd>.D
  6348  		{
  6349  			goOp:      AZMUL,
  6350  			fixedBits: 0x44e0f800,
  6351  			args:      Zm_D_imm___Zn_D__Zd_D__1,
  6352  		},
  6353  		// ZMUL <Zm>.H[<imm>], <Zn>.H, <Zd>.H
  6354  		{
  6355  			goOp:      AZMUL,
  6356  			fixedBits: 0x4420f800,
  6357  			args:      Zm_H_imm___Zn_H__Zd_H__1,
  6358  		},
  6359  		// ZMUL <Zm>.S[<imm>], <Zn>.S, <Zd>.S
  6360  		{
  6361  			goOp:      AZMUL,
  6362  			fixedBits: 0x44a0f800,
  6363  			args:      Zm_S_imm___Zn_S__Zd_S__1,
  6364  		},
  6365  		// ZMUL #<imm>, <Zdn>.<T>, <Zdn>.<T>
  6366  		{
  6367  			goOp:      AZMUL,
  6368  			fixedBits: 0x2530c000,
  6369  			args:      cimm__Zdn_T__Zdn_T__1,
  6370  		},
  6371  	},
  6372  	// ZNBSL
  6373  	{
  6374  		// ZNBSL <Zk>.D, <Zm>.D, <Zdn>.D, <Zdn>.D
  6375  		{
  6376  			goOp:      AZNBSL,
  6377  			fixedBits: 0x4e03c00,
  6378  			args:      Zk_D__Zm_D__Zdn_D__Zdn_D,
  6379  		},
  6380  	},
  6381  	// ZNEG
  6382  	{
  6383  		// ZNEG <Zn>.<T>, <Pg>/M, <Zd>.<T>
  6384  		{
  6385  			goOp:      AZNEG,
  6386  			fixedBits: 0x417a000,
  6387  			args:      Zn_T__PgM__Zd_T__2,
  6388  		},
  6389  		// ZNEG <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  6390  		{
  6391  			goOp:      AZNEG,
  6392  			fixedBits: 0x407a000,
  6393  			args:      Zn_T__PgZ__Zd_T__2,
  6394  		},
  6395  	},
  6396  	// ZNMATCH
  6397  	{
  6398  		// ZNMATCH <Zm>.<T>, <Zn>.<T>, <Pg>/Z, <Pd>.<T>
  6399  		{
  6400  			goOp:      AZNMATCH,
  6401  			fixedBits: 0x45208010,
  6402  			args:      Zm_T__Zn_T__PgZ__Pd_T__3,
  6403  		},
  6404  	},
  6405  	// ZNOT
  6406  	{
  6407  		// ZNOT <Zn>.<T>, <Pg>/M, <Zd>.<T>
  6408  		{
  6409  			goOp:      AZNOT,
  6410  			fixedBits: 0x41ea000,
  6411  			args:      Zn_T__PgM__Zd_T__2,
  6412  		},
  6413  		// ZNOT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  6414  		{
  6415  			goOp:      AZNOT,
  6416  			fixedBits: 0x40ea000,
  6417  			args:      Zn_T__PgZ__Zd_T__2,
  6418  		},
  6419  	},
  6420  	// ZORQV
  6421  	{
  6422  		// ZORQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  6423  		{
  6424  			goOp:      AZORQV,
  6425  			fixedBits: 0x41c2000,
  6426  			args:      Zn_Tb__Pg__Vd_T__1,
  6427  		},
  6428  	},
  6429  	// ZORR
  6430  	{
  6431  		// ZORR <Zm>.D, <Zn>.D, <Zd>.D
  6432  		{
  6433  			goOp:      AZORR,
  6434  			fixedBits: 0x4603000,
  6435  			args:      Zm_D__Zn_D__Zd_D,
  6436  		},
  6437  		// ZORR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6438  		{
  6439  			goOp:      AZORR,
  6440  			fixedBits: 0x4180000,
  6441  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  6442  		},
  6443  		// ZORR #<const>, <Zdn>.<T>, <Zdn>.<T>
  6444  		{
  6445  			goOp:      AZORR,
  6446  			fixedBits: 0x5000000,
  6447  			args:      cconst__Zdn_T__Zdn_T,
  6448  		},
  6449  	},
  6450  	// ZORVB
  6451  	{
  6452  		// ZORVB <Zn>.<T>, <Pg>, <V><d>
  6453  		{
  6454  			goOp:      AZORVB,
  6455  			fixedBits: 0x4182000,
  6456  			args:      Zn_T__Pg__Vd__1,
  6457  		},
  6458  	},
  6459  	// ZORVD
  6460  	{
  6461  		// ZORVD <Zn>.<T>, <Pg>, <V><d>
  6462  		{
  6463  			goOp:      AZORVD,
  6464  			fixedBits: 0x4d82000,
  6465  			args:      Zn_T__Pg__Vd__1,
  6466  		},
  6467  	},
  6468  	// ZORVH
  6469  	{
  6470  		// ZORVH <Zn>.<T>, <Pg>, <V><d>
  6471  		{
  6472  			goOp:      AZORVH,
  6473  			fixedBits: 0x4582000,
  6474  			args:      Zn_T__Pg__Vd__1,
  6475  		},
  6476  	},
  6477  	// ZORVS
  6478  	{
  6479  		// ZORVS <Zn>.<T>, <Pg>, <V><d>
  6480  		{
  6481  			goOp:      AZORVS,
  6482  			fixedBits: 0x4982000,
  6483  			args:      Zn_T__Pg__Vd__1,
  6484  		},
  6485  	},
  6486  	// ZPMLAL
  6487  	{
  6488  		// ZPMLAL <Zm>.D, <Zn>.D, { <Zda1>.Q-<Zda2>.Q }
  6489  		{
  6490  			goOp:      AZPMLAL,
  6491  			fixedBits: 0x4520fc00,
  6492  			args:      Zm_D__Zn_D___Zda1_Q_Zda2_Q_,
  6493  		},
  6494  	},
  6495  	// ZPMOV
  6496  	{
  6497  		// ZPMOV <Pn>.B, <Zd>
  6498  		{
  6499  			goOp:      AZPMOV,
  6500  			fixedBits: 0x52b3800,
  6501  			args:      Pn_B__Zd,
  6502  		},
  6503  		// ZPMOV <Zn>, <Pd>.B
  6504  		{
  6505  			goOp:      AZPMOV,
  6506  			fixedBits: 0x52a3800,
  6507  			args:      Zn__Pd_B,
  6508  		},
  6509  		// ZPMOV <Pn>.D, <Zd>{[<imm>]}
  6510  		{
  6511  			goOp:      AZPMOV,
  6512  			fixedBits: 0x5a93800,
  6513  			args:      Pn_D__Zd_imm_,
  6514  		},
  6515  		// ZPMOV <Pn>.H, <Zd>{[<imm>]}
  6516  		{
  6517  			goOp:      AZPMOV,
  6518  			fixedBits: 0x52d3800,
  6519  			args:      Pn_H__Zd_imm_,
  6520  		},
  6521  		// ZPMOV <Pn>.S, <Zd>{[<imm>]}
  6522  		{
  6523  			goOp:      AZPMOV,
  6524  			fixedBits: 0x5693800,
  6525  			args:      Pn_S__Zd_imm_,
  6526  		},
  6527  		// ZPMOV <Zn>{[<imm>]}, <Pd>.D
  6528  		{
  6529  			goOp:      AZPMOV,
  6530  			fixedBits: 0x5a83800,
  6531  			args:      Zn_imm___Pd_D,
  6532  		},
  6533  		// ZPMOV <Zn>{[<imm>]}, <Pd>.H
  6534  		{
  6535  			goOp:      AZPMOV,
  6536  			fixedBits: 0x52c3800,
  6537  			args:      Zn_imm___Pd_H,
  6538  		},
  6539  		// ZPMOV <Zn>{[<imm>]}, <Pd>.S
  6540  		{
  6541  			goOp:      AZPMOV,
  6542  			fixedBits: 0x5683800,
  6543  			args:      Zn_imm___Pd_S,
  6544  		},
  6545  	},
  6546  	// ZPMUL
  6547  	{
  6548  		// ZPMUL <Zm>.B, <Zn>.B, <Zd>.B
  6549  		{
  6550  			goOp:      AZPMUL,
  6551  			fixedBits: 0x4206400,
  6552  			args:      Zm_B__Zn_B__Zd_B,
  6553  		},
  6554  	},
  6555  	// ZPMULL
  6556  	{
  6557  		// ZPMULL <Zm>.D, <Zn>.D, { <Zd1>.Q-<Zd2>.Q }
  6558  		{
  6559  			goOp:      AZPMULL,
  6560  			fixedBits: 0x4520f800,
  6561  			args:      Zm_D__Zn_D___Zd1_Q_Zd2_Q_,
  6562  		},
  6563  	},
  6564  	// ZPMULLB
  6565  	{
  6566  		// ZPMULLB <Zm>.D, <Zn>.D, <Zd>.Q
  6567  		{
  6568  			goOp:      AZPMULLB,
  6569  			fixedBits: 0x45006800,
  6570  			args:      Zm_D__Zn_D__Zd_Q,
  6571  		},
  6572  		// ZPMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6573  		{
  6574  			goOp:      AZPMULLB,
  6575  			fixedBits: 0x45006800,
  6576  			args:      Zm_Tb__Zn_Tb__Zd_T__3,
  6577  		},
  6578  	},
  6579  	// ZPMULLT
  6580  	{
  6581  		// ZPMULLT <Zm>.D, <Zn>.D, <Zd>.Q
  6582  		{
  6583  			goOp:      AZPMULLT,
  6584  			fixedBits: 0x45006c00,
  6585  			args:      Zm_D__Zn_D__Zd_Q,
  6586  		},
  6587  		// ZPMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6588  		{
  6589  			goOp:      AZPMULLT,
  6590  			fixedBits: 0x45006c00,
  6591  			args:      Zm_Tb__Zn_Tb__Zd_T__3,
  6592  		},
  6593  	},
  6594  	// ZPRFB
  6595  	{
  6596  		// ZPRFB [<Xn|SP>, <Zm>.D], <Pg>, <prfop>
  6597  		{
  6598  			goOp:      AZPRFB,
  6599  			fixedBits: 0xc4608000,
  6600  			args:      XnSP__Zm_D___Pg__prfop,
  6601  		},
  6602  		// ZPRFB [<Xn|SP>, <Zm>.D, <mod>], <Pg>, <prfop>
  6603  		{
  6604  			goOp:      AZPRFB,
  6605  			fixedBits: 0xc4200000,
  6606  			args:      XnSP__Zm_D__mod___Pg__prfop,
  6607  		},
  6608  		// ZPRFB [<Xn|SP>, <Zm>.S, <mod>], <Pg>, <prfop>
  6609  		{
  6610  			goOp:      AZPRFB,
  6611  			fixedBits: 0x84200000,
  6612  			args:      XnSP__Zm_S__mod___Pg__prfop,
  6613  		},
  6614  		// ZPRFB [<Zn>.D{, #<imm>}], <Pg>, <prfop>
  6615  		{
  6616  			goOp:      AZPRFB,
  6617  			fixedBits: 0xc400e000,
  6618  			args:      Zn_D__cimm___Pg__prfop__1,
  6619  		},
  6620  		// ZPRFB [<Zn>.S{, #<imm>}], <Pg>, <prfop>
  6621  		{
  6622  			goOp:      AZPRFB,
  6623  			fixedBits: 0x8400e000,
  6624  			args:      Zn_S__cimm___Pg__prfop__1,
  6625  		},
  6626  	},
  6627  	// ZPRFD
  6628  	{
  6629  		// ZPRFD [<Xn|SP>, <Zm>.D, LSL #3], <Pg>, <prfop>
  6630  		{
  6631  			goOp:      AZPRFD,
  6632  			fixedBits: 0xc460e000,
  6633  			args:      XnSP__Zm_D__LSL_c3___Pg__prfop,
  6634  		},
  6635  		// ZPRFD [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>, <prfop>
  6636  		{
  6637  			goOp:      AZPRFD,
  6638  			fixedBits: 0xc4206000,
  6639  			args:      XnSP__Zm_D__mod_c3___Pg__prfop,
  6640  		},
  6641  		// ZPRFD [<Xn|SP>, <Zm>.S, <mod> #3], <Pg>, <prfop>
  6642  		{
  6643  			goOp:      AZPRFD,
  6644  			fixedBits: 0x84206000,
  6645  			args:      XnSP__Zm_S__mod_c3___Pg__prfop,
  6646  		},
  6647  		// ZPRFD [<Zn>.D{, #<imm>}], <Pg>, <prfop>
  6648  		{
  6649  			goOp:      AZPRFD,
  6650  			fixedBits: 0xc580e000,
  6651  			args:      Zn_D__cimm___Pg__prfop__2,
  6652  		},
  6653  		// ZPRFD [<Zn>.S{, #<imm>}], <Pg>, <prfop>
  6654  		{
  6655  			goOp:      AZPRFD,
  6656  			fixedBits: 0x8580e000,
  6657  			args:      Zn_S__cimm___Pg__prfop__2,
  6658  		},
  6659  	},
  6660  	// ZPRFH
  6661  	{
  6662  		// ZPRFH [<Xn|SP>, <Zm>.D, LSL #1], <Pg>, <prfop>
  6663  		{
  6664  			goOp:      AZPRFH,
  6665  			fixedBits: 0xc460a000,
  6666  			args:      XnSP__Zm_D__LSL_c1___Pg__prfop,
  6667  		},
  6668  		// ZPRFH [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>, <prfop>
  6669  		{
  6670  			goOp:      AZPRFH,
  6671  			fixedBits: 0xc4202000,
  6672  			args:      XnSP__Zm_D__mod_c1___Pg__prfop,
  6673  		},
  6674  		// ZPRFH [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>, <prfop>
  6675  		{
  6676  			goOp:      AZPRFH,
  6677  			fixedBits: 0x84202000,
  6678  			args:      XnSP__Zm_S__mod_c1___Pg__prfop,
  6679  		},
  6680  		// ZPRFH [<Zn>.D{, #<imm>}], <Pg>, <prfop>
  6681  		{
  6682  			goOp:      AZPRFH,
  6683  			fixedBits: 0xc480e000,
  6684  			args:      Zn_D__cimm___Pg__prfop__3,
  6685  		},
  6686  		// ZPRFH [<Zn>.S{, #<imm>}], <Pg>, <prfop>
  6687  		{
  6688  			goOp:      AZPRFH,
  6689  			fixedBits: 0x8480e000,
  6690  			args:      Zn_S__cimm___Pg__prfop__3,
  6691  		},
  6692  	},
  6693  	// ZPRFW
  6694  	{
  6695  		// ZPRFW [<Xn|SP>, <Zm>.D, LSL #2], <Pg>, <prfop>
  6696  		{
  6697  			goOp:      AZPRFW,
  6698  			fixedBits: 0xc460c000,
  6699  			args:      XnSP__Zm_D__LSL_c2___Pg__prfop,
  6700  		},
  6701  		// ZPRFW [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>, <prfop>
  6702  		{
  6703  			goOp:      AZPRFW,
  6704  			fixedBits: 0xc4204000,
  6705  			args:      XnSP__Zm_D__mod_c2___Pg__prfop,
  6706  		},
  6707  		// ZPRFW [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>, <prfop>
  6708  		{
  6709  			goOp:      AZPRFW,
  6710  			fixedBits: 0x84204000,
  6711  			args:      XnSP__Zm_S__mod_c2___Pg__prfop,
  6712  		},
  6713  		// ZPRFW [<Zn>.D{, #<imm>}], <Pg>, <prfop>
  6714  		{
  6715  			goOp:      AZPRFW,
  6716  			fixedBits: 0xc500e000,
  6717  			args:      Zn_D__cimm___Pg__prfop__4,
  6718  		},
  6719  		// ZPRFW [<Zn>.S{, #<imm>}], <Pg>, <prfop>
  6720  		{
  6721  			goOp:      AZPRFW,
  6722  			fixedBits: 0x8500e000,
  6723  			args:      Zn_S__cimm___Pg__prfop__4,
  6724  		},
  6725  	},
  6726  	// ZRADDHNB
  6727  	{
  6728  		// ZRADDHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6729  		{
  6730  			goOp:      AZRADDHNB,
  6731  			fixedBits: 0x45206800,
  6732  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  6733  		},
  6734  	},
  6735  	// ZRADDHNT
  6736  	{
  6737  		// ZRADDHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6738  		{
  6739  			goOp:      AZRADDHNT,
  6740  			fixedBits: 0x45206c00,
  6741  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  6742  		},
  6743  	},
  6744  	// ZRAX1
  6745  	{
  6746  		// ZRAX1 <Zm>.D, <Zn>.D, <Zd>.D
  6747  		{
  6748  			goOp:      AZRAX1,
  6749  			fixedBits: 0x4520f400,
  6750  			args:      Zm_D__Zn_D__Zd_D,
  6751  		},
  6752  	},
  6753  	// ZRBIT
  6754  	{
  6755  		// ZRBIT <Zn>.<T>, <Pg>/M, <Zd>.<T>
  6756  		{
  6757  			goOp:      AZRBIT,
  6758  			fixedBits: 0x5278000,
  6759  			args:      Zn_T__PgM__Zd_T__2,
  6760  		},
  6761  		// ZRBIT <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  6762  		{
  6763  			goOp:      AZRBIT,
  6764  			fixedBits: 0x527a000,
  6765  			args:      Zn_T__PgZ__Zd_T__2,
  6766  		},
  6767  	},
  6768  	// ZREV
  6769  	{
  6770  		// ZREV <Zn>.<T>, <Zd>.<T>
  6771  		{
  6772  			goOp:      AZREV,
  6773  			fixedBits: 0x5383800,
  6774  			args:      Zn_T__Zd_T__2,
  6775  		},
  6776  	},
  6777  	// ZREVB
  6778  	{
  6779  		// ZREVB <Zn>.<T>, <Pg>/M, <Zd>.<T>
  6780  		{
  6781  			goOp:      AZREVB,
  6782  			fixedBits: 0x5248000,
  6783  			args:      Zn_T__PgM__Zd_T__4,
  6784  		},
  6785  		// ZREVB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  6786  		{
  6787  			goOp:      AZREVB,
  6788  			fixedBits: 0x524a000,
  6789  			args:      Zn_T__PgZ__Zd_T__4,
  6790  		},
  6791  	},
  6792  	// ZREVD
  6793  	{
  6794  		// ZREVD <Zn>.Q, <Pg>/M, <Zd>.Q
  6795  		{
  6796  			goOp:      AZREVD,
  6797  			fixedBits: 0x52e8000,
  6798  			args:      Zn_Q__PgM__Zd_Q,
  6799  		},
  6800  		// ZREVD <Zn>.Q, <Pg>/Z, <Zd>.Q
  6801  		{
  6802  			goOp:      AZREVD,
  6803  			fixedBits: 0x52ea000,
  6804  			args:      Zn_Q__PgZ__Zd_Q,
  6805  		},
  6806  	},
  6807  	// ZREVH
  6808  	{
  6809  		// ZREVH <Zn>.<T>, <Pg>/M, <Zd>.<T>
  6810  		{
  6811  			goOp:      AZREVH,
  6812  			fixedBits: 0x5a58000,
  6813  			args:      Zn_T__PgM__Zd_T__5,
  6814  		},
  6815  		// ZREVH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  6816  		{
  6817  			goOp:      AZREVH,
  6818  			fixedBits: 0x5a5a000,
  6819  			args:      Zn_T__PgZ__Zd_T__5,
  6820  		},
  6821  	},
  6822  	// ZREVW
  6823  	{
  6824  		// ZREVW <Zn>.D, <Pg>/M, <Zd>.D
  6825  		{
  6826  			goOp:      AZREVW,
  6827  			fixedBits: 0x5e68000,
  6828  			args:      Zn_D__PgM__Zd_D,
  6829  		},
  6830  		// ZREVW <Zn>.D, <Pg>/Z, <Zd>.D
  6831  		{
  6832  			goOp:      AZREVW,
  6833  			fixedBits: 0x5e6a000,
  6834  			args:      Zn_D__PgZ__Zd_D,
  6835  		},
  6836  	},
  6837  	// ZRSHRNB
  6838  	{
  6839  		// ZRSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T>
  6840  		{
  6841  			goOp:      AZRSHRNB,
  6842  			fixedBits: 0x45201800,
  6843  			args:      cconst__Zn_Tb__Zd_T__1,
  6844  		},
  6845  	},
  6846  	// ZRSHRNT
  6847  	{
  6848  		// ZRSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T>
  6849  		{
  6850  			goOp:      AZRSHRNT,
  6851  			fixedBits: 0x45201c00,
  6852  			args:      cconst__Zn_Tb__Zd_T__1,
  6853  		},
  6854  	},
  6855  	// ZRSUBHNB
  6856  	{
  6857  		// ZRSUBHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6858  		{
  6859  			goOp:      AZRSUBHNB,
  6860  			fixedBits: 0x45207800,
  6861  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  6862  		},
  6863  	},
  6864  	// ZRSUBHNT
  6865  	{
  6866  		// ZRSUBHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6867  		{
  6868  			goOp:      AZRSUBHNT,
  6869  			fixedBits: 0x45207c00,
  6870  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  6871  		},
  6872  	},
  6873  	// ZSABA
  6874  	{
  6875  		// ZSABA <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  6876  		{
  6877  			goOp:      AZSABA,
  6878  			fixedBits: 0x4500f800,
  6879  			args:      Zm_T__Zn_T__Zda_T__2,
  6880  		},
  6881  	},
  6882  	// ZSABAL
  6883  	{
  6884  		// ZSABAL <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  6885  		{
  6886  			goOp:      AZSABAL,
  6887  			fixedBits: 0x4400d400,
  6888  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  6889  		},
  6890  	},
  6891  	// ZSABALB
  6892  	{
  6893  		// ZSABALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  6894  		{
  6895  			goOp:      AZSABALB,
  6896  			fixedBits: 0x4500c000,
  6897  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  6898  		},
  6899  	},
  6900  	// ZSABALT
  6901  	{
  6902  		// ZSABALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  6903  		{
  6904  			goOp:      AZSABALT,
  6905  			fixedBits: 0x4500c400,
  6906  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  6907  		},
  6908  	},
  6909  	// ZSABD
  6910  	{
  6911  		// ZSABD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  6912  		{
  6913  			goOp:      AZSABD,
  6914  			fixedBits: 0x40c0000,
  6915  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  6916  		},
  6917  	},
  6918  	// ZSABDLB
  6919  	{
  6920  		// ZSABDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6921  		{
  6922  			goOp:      AZSABDLB,
  6923  			fixedBits: 0x45003000,
  6924  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  6925  		},
  6926  	},
  6927  	// ZSABDLT
  6928  	{
  6929  		// ZSABDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6930  		{
  6931  			goOp:      AZSABDLT,
  6932  			fixedBits: 0x45003400,
  6933  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  6934  		},
  6935  	},
  6936  	// ZSADALP
  6937  	{
  6938  		// ZSADALP <Zn>.<Tb>, <Pg>/M, <Zda>.<T>
  6939  		{
  6940  			goOp:      AZSADALP,
  6941  			fixedBits: 0x4404a000,
  6942  			args:      Zn_Tb__PgM__Zda_T,
  6943  		},
  6944  	},
  6945  	// ZSADDLB
  6946  	{
  6947  		// ZSADDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6948  		{
  6949  			goOp:      AZSADDLB,
  6950  			fixedBits: 0x45000000,
  6951  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  6952  		},
  6953  	},
  6954  	// ZSADDLBT
  6955  	{
  6956  		// ZSADDLBT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6957  		{
  6958  			goOp:      AZSADDLBT,
  6959  			fixedBits: 0x45008000,
  6960  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  6961  		},
  6962  	},
  6963  	// ZSADDLT
  6964  	{
  6965  		// ZSADDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  6966  		{
  6967  			goOp:      AZSADDLT,
  6968  			fixedBits: 0x45000400,
  6969  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  6970  		},
  6971  	},
  6972  	// ZSADDVD
  6973  	{
  6974  		// ZSADDVD <Zn>.<T>, <Pg>, <Dd>
  6975  		{
  6976  			goOp:      AZSADDVD,
  6977  			fixedBits: 0x4002000,
  6978  			args:      Zn_T__Pg__Dd__1,
  6979  		},
  6980  	},
  6981  	// ZSADDWB
  6982  	{
  6983  		// ZSADDWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
  6984  		{
  6985  			goOp:      AZSADDWB,
  6986  			fixedBits: 0x45004000,
  6987  			args:      Zm_Tb__Zn_T__Zd_T,
  6988  		},
  6989  	},
  6990  	// ZSADDWT
  6991  	{
  6992  		// ZSADDWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
  6993  		{
  6994  			goOp:      AZSADDWT,
  6995  			fixedBits: 0x45004400,
  6996  			args:      Zm_Tb__Zn_T__Zd_T,
  6997  		},
  6998  	},
  6999  	// ZSBCLB
  7000  	{
  7001  		// ZSBCLB <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  7002  		{
  7003  			goOp:      AZSBCLB,
  7004  			fixedBits: 0x4580d000,
  7005  			args:      Zm_T__Zn_T__Zda_T__1,
  7006  		},
  7007  	},
  7008  	// ZSBCLT
  7009  	{
  7010  		// ZSBCLT <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  7011  		{
  7012  			goOp:      AZSBCLT,
  7013  			fixedBits: 0x4580d400,
  7014  			args:      Zm_T__Zn_T__Zda_T__1,
  7015  		},
  7016  	},
  7017  	// ZSCLAMP
  7018  	{
  7019  		// ZSCLAMP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  7020  		{
  7021  			goOp:      AZSCLAMP,
  7022  			fixedBits: 0x4400c000,
  7023  			args:      Zm_T__Zn_T__Zd_T__1,
  7024  		},
  7025  	},
  7026  	// ZSCVTF
  7027  	{
  7028  		// ZSCVTF <Zn>.D, <Pg>/M, <Zd>.D
  7029  		{
  7030  			goOp:      AZSCVTF,
  7031  			fixedBits: 0x65d6a000,
  7032  			args:      Zn_D__PgM__Zd_D,
  7033  		},
  7034  		// ZSCVTF <Zn>.D, <Pg>/M, <Zd>.H
  7035  		{
  7036  			goOp:      AZSCVTF,
  7037  			fixedBits: 0x6556a000,
  7038  			args:      Zn_D__PgM__Zd_H,
  7039  		},
  7040  		// ZSCVTF <Zn>.D, <Pg>/M, <Zd>.S
  7041  		{
  7042  			goOp:      AZSCVTF,
  7043  			fixedBits: 0x65d4a000,
  7044  			args:      Zn_D__PgM__Zd_S,
  7045  		},
  7046  		// ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.D
  7047  		{
  7048  			goOp:      AZSCVTF,
  7049  			fixedBits: 0x64ddc000,
  7050  			args:      Zn_D__PgZ__Zd_D,
  7051  		},
  7052  		// ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.H
  7053  		{
  7054  			goOp:      AZSCVTF,
  7055  			fixedBits: 0x645dc000,
  7056  			args:      Zn_D__PgZ__Zd_H,
  7057  		},
  7058  		// ZSCVTF <Zn>.D, <Pg>/Z, <Zd>.S
  7059  		{
  7060  			goOp:      AZSCVTF,
  7061  			fixedBits: 0x64dd8000,
  7062  			args:      Zn_D__PgZ__Zd_S,
  7063  		},
  7064  		// ZSCVTF <Zn>.H, <Pg>/M, <Zd>.H
  7065  		{
  7066  			goOp:      AZSCVTF,
  7067  			fixedBits: 0x6552a000,
  7068  			args:      Zn_H__PgM__Zd_H,
  7069  		},
  7070  		// ZSCVTF <Zn>.H, <Pg>/Z, <Zd>.H
  7071  		{
  7072  			goOp:      AZSCVTF,
  7073  			fixedBits: 0x645cc000,
  7074  			args:      Zn_H__PgZ__Zd_H,
  7075  		},
  7076  		// ZSCVTF <Zn>.S, <Pg>/M, <Zd>.D
  7077  		{
  7078  			goOp:      AZSCVTF,
  7079  			fixedBits: 0x65d0a000,
  7080  			args:      Zn_S__PgM__Zd_D,
  7081  		},
  7082  		// ZSCVTF <Zn>.S, <Pg>/M, <Zd>.H
  7083  		{
  7084  			goOp:      AZSCVTF,
  7085  			fixedBits: 0x6554a000,
  7086  			args:      Zn_S__PgM__Zd_H,
  7087  		},
  7088  		// ZSCVTF <Zn>.S, <Pg>/M, <Zd>.S
  7089  		{
  7090  			goOp:      AZSCVTF,
  7091  			fixedBits: 0x6594a000,
  7092  			args:      Zn_S__PgM__Zd_S,
  7093  		},
  7094  		// ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.D
  7095  		{
  7096  			goOp:      AZSCVTF,
  7097  			fixedBits: 0x64dc8000,
  7098  			args:      Zn_S__PgZ__Zd_D,
  7099  		},
  7100  		// ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.H
  7101  		{
  7102  			goOp:      AZSCVTF,
  7103  			fixedBits: 0x645d8000,
  7104  			args:      Zn_S__PgZ__Zd_H,
  7105  		},
  7106  		// ZSCVTF <Zn>.S, <Pg>/Z, <Zd>.S
  7107  		{
  7108  			goOp:      AZSCVTF,
  7109  			fixedBits: 0x649d8000,
  7110  			args:      Zn_S__PgZ__Zd_S,
  7111  		},
  7112  		// ZSCVTF <Zn>.<Tb>, <Zd>.<T>
  7113  		{
  7114  			goOp:      AZSCVTF,
  7115  			fixedBits: 0x650c3000,
  7116  			args:      Zn_Tb__Zd_T__1,
  7117  		},
  7118  	},
  7119  	// ZSCVTFLT
  7120  	{
  7121  		// ZSCVTFLT <Zn>.<Tb>, <Zd>.<T>
  7122  		{
  7123  			goOp:      AZSCVTFLT,
  7124  			fixedBits: 0x650c3800,
  7125  			args:      Zn_Tb__Zd_T__1,
  7126  		},
  7127  	},
  7128  	// ZSDIV
  7129  	{
  7130  		// ZSDIV <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7131  		{
  7132  			goOp:      AZSDIV,
  7133  			fixedBits: 0x4940000,
  7134  			args:      Zm_T__Zdn_T__PgM__Zdn_T__4,
  7135  		},
  7136  	},
  7137  	// ZSDIVR
  7138  	{
  7139  		// ZSDIVR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7140  		{
  7141  			goOp:      AZSDIVR,
  7142  			fixedBits: 0x4960000,
  7143  			args:      Zm_T__Zdn_T__PgM__Zdn_T__4,
  7144  		},
  7145  	},
  7146  	// ZSDOT
  7147  	{
  7148  		// ZSDOT <Zm>.B, <Zn>.B, <Zda>.H
  7149  		{
  7150  			goOp:      AZSDOT,
  7151  			fixedBits: 0x44400000,
  7152  			args:      Zm_B__Zn_B__Zda_H,
  7153  		},
  7154  		// ZSDOT <Zm>.H, <Zn>.H, <Zda>.S
  7155  		{
  7156  			goOp:      AZSDOT,
  7157  			fixedBits: 0x4400c800,
  7158  			args:      Zm_H__Zn_H__Zda_S,
  7159  		},
  7160  		// ZSDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7161  		{
  7162  			goOp:      AZSDOT,
  7163  			fixedBits: 0x44800000,
  7164  			args:      Zm_Tb__Zn_Tb__Zda_T__2,
  7165  		},
  7166  		// ZSDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H
  7167  		{
  7168  			goOp:      AZSDOT,
  7169  			fixedBits: 0x44200000,
  7170  			args:      Zm_B_imm___Zn_B__Zda_H__2,
  7171  		},
  7172  		// ZSDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  7173  		{
  7174  			goOp:      AZSDOT,
  7175  			fixedBits: 0x44a00000,
  7176  			args:      Zm_B_imm___Zn_B__Zda_S__3,
  7177  		},
  7178  		// ZSDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.D
  7179  		{
  7180  			goOp:      AZSDOT,
  7181  			fixedBits: 0x44e00000,
  7182  			args:      Zm_H_imm___Zn_H__Zda_D,
  7183  		},
  7184  		// ZSDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7185  		{
  7186  			goOp:      AZSDOT,
  7187  			fixedBits: 0x4480c800,
  7188  			args:      Zm_H_imm___Zn_H__Zda_S__4,
  7189  		},
  7190  	},
  7191  	// ZSEL
  7192  	{
  7193  		// ZSEL <Zm>.<T>, <Zn>.<T>, <Pv>, <Zd>.<T>
  7194  		{
  7195  			goOp:      AZSEL,
  7196  			fixedBits: 0x520c000,
  7197  			args:      Zm_T__Zn_T__Pv__Zd_T,
  7198  		},
  7199  	},
  7200  	// ZSHADD
  7201  	{
  7202  		// ZSHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7203  		{
  7204  			goOp:      AZSHADD,
  7205  			fixedBits: 0x44108000,
  7206  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7207  		},
  7208  	},
  7209  	// ZSHRNB
  7210  	{
  7211  		// ZSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T>
  7212  		{
  7213  			goOp:      AZSHRNB,
  7214  			fixedBits: 0x45201000,
  7215  			args:      cconst__Zn_Tb__Zd_T__1,
  7216  		},
  7217  	},
  7218  	// ZSHRNT
  7219  	{
  7220  		// ZSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T>
  7221  		{
  7222  			goOp:      AZSHRNT,
  7223  			fixedBits: 0x45201400,
  7224  			args:      cconst__Zn_Tb__Zd_T__1,
  7225  		},
  7226  	},
  7227  	// ZSHSUB
  7228  	{
  7229  		// ZSHSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7230  		{
  7231  			goOp:      AZSHSUB,
  7232  			fixedBits: 0x44128000,
  7233  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7234  		},
  7235  	},
  7236  	// ZSHSUBR
  7237  	{
  7238  		// ZSHSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7239  		{
  7240  			goOp:      AZSHSUBR,
  7241  			fixedBits: 0x44168000,
  7242  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7243  		},
  7244  	},
  7245  	// ZSLI
  7246  	{
  7247  		// ZSLI #<const>, <Zn>.<T>, <Zd>.<T>
  7248  		{
  7249  			goOp:      AZSLI,
  7250  			fixedBits: 0x4500f400,
  7251  			args:      cconst__Zn_T__Zd_T__2,
  7252  		},
  7253  	},
  7254  	// ZSM4E
  7255  	{
  7256  		// ZSM4E <Zm>.S, <Zdn>.S, <Zdn>.S
  7257  		{
  7258  			goOp:      AZSM4E,
  7259  			fixedBits: 0x4523e000,
  7260  			args:      Zm_S__Zdn_S__Zdn_S,
  7261  		},
  7262  	},
  7263  	// ZSM4EKEY
  7264  	{
  7265  		// ZSM4EKEY <Zm>.S, <Zn>.S, <Zd>.S
  7266  		{
  7267  			goOp:      AZSM4EKEY,
  7268  			fixedBits: 0x4520f000,
  7269  			args:      Zm_S__Zn_S__Zd_S,
  7270  		},
  7271  	},
  7272  	// ZSMAX
  7273  	{
  7274  		// ZSMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7275  		{
  7276  			goOp:      AZSMAX,
  7277  			fixedBits: 0x4080000,
  7278  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7279  		},
  7280  		// ZSMAX #<imm>, <Zdn>.<T>, <Zdn>.<T>
  7281  		{
  7282  			goOp:      AZSMAX,
  7283  			fixedBits: 0x2528c000,
  7284  			args:      cimm__Zdn_T__Zdn_T__1,
  7285  		},
  7286  	},
  7287  	// ZSMAXP
  7288  	{
  7289  		// ZSMAXP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7290  		{
  7291  			goOp:      AZSMAXP,
  7292  			fixedBits: 0x4414a000,
  7293  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7294  		},
  7295  	},
  7296  	// ZSMAXQV
  7297  	{
  7298  		// ZSMAXQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  7299  		{
  7300  			goOp:      AZSMAXQV,
  7301  			fixedBits: 0x40c2000,
  7302  			args:      Zn_Tb__Pg__Vd_T__1,
  7303  		},
  7304  	},
  7305  	// ZSMAXVB
  7306  	{
  7307  		// ZSMAXVB <Zn>.<T>, <Pg>, <V><d>
  7308  		{
  7309  			goOp:      AZSMAXVB,
  7310  			fixedBits: 0x4082000,
  7311  			args:      Zn_T__Pg__Vd__1,
  7312  		},
  7313  	},
  7314  	// ZSMAXVD
  7315  	{
  7316  		// ZSMAXVD <Zn>.<T>, <Pg>, <V><d>
  7317  		{
  7318  			goOp:      AZSMAXVD,
  7319  			fixedBits: 0x4c82000,
  7320  			args:      Zn_T__Pg__Vd__1,
  7321  		},
  7322  	},
  7323  	// ZSMAXVH
  7324  	{
  7325  		// ZSMAXVH <Zn>.<T>, <Pg>, <V><d>
  7326  		{
  7327  			goOp:      AZSMAXVH,
  7328  			fixedBits: 0x4482000,
  7329  			args:      Zn_T__Pg__Vd__1,
  7330  		},
  7331  	},
  7332  	// ZSMAXVS
  7333  	{
  7334  		// ZSMAXVS <Zn>.<T>, <Pg>, <V><d>
  7335  		{
  7336  			goOp:      AZSMAXVS,
  7337  			fixedBits: 0x4882000,
  7338  			args:      Zn_T__Pg__Vd__1,
  7339  		},
  7340  	},
  7341  	// ZSMIN
  7342  	{
  7343  		// ZSMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7344  		{
  7345  			goOp:      AZSMIN,
  7346  			fixedBits: 0x40a0000,
  7347  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7348  		},
  7349  		// ZSMIN #<imm>, <Zdn>.<T>, <Zdn>.<T>
  7350  		{
  7351  			goOp:      AZSMIN,
  7352  			fixedBits: 0x252ac000,
  7353  			args:      cimm__Zdn_T__Zdn_T__1,
  7354  		},
  7355  	},
  7356  	// ZSMINP
  7357  	{
  7358  		// ZSMINP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7359  		{
  7360  			goOp:      AZSMINP,
  7361  			fixedBits: 0x4416a000,
  7362  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7363  		},
  7364  	},
  7365  	// ZSMINQV
  7366  	{
  7367  		// ZSMINQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  7368  		{
  7369  			goOp:      AZSMINQV,
  7370  			fixedBits: 0x40e2000,
  7371  			args:      Zn_Tb__Pg__Vd_T__1,
  7372  		},
  7373  	},
  7374  	// ZSMINVB
  7375  	{
  7376  		// ZSMINVB <Zn>.<T>, <Pg>, <V><d>
  7377  		{
  7378  			goOp:      AZSMINVB,
  7379  			fixedBits: 0x40a2000,
  7380  			args:      Zn_T__Pg__Vd__1,
  7381  		},
  7382  	},
  7383  	// ZSMINVD
  7384  	{
  7385  		// ZSMINVD <Zn>.<T>, <Pg>, <V><d>
  7386  		{
  7387  			goOp:      AZSMINVD,
  7388  			fixedBits: 0x4ca2000,
  7389  			args:      Zn_T__Pg__Vd__1,
  7390  		},
  7391  	},
  7392  	// ZSMINVH
  7393  	{
  7394  		// ZSMINVH <Zn>.<T>, <Pg>, <V><d>
  7395  		{
  7396  			goOp:      AZSMINVH,
  7397  			fixedBits: 0x44a2000,
  7398  			args:      Zn_T__Pg__Vd__1,
  7399  		},
  7400  	},
  7401  	// ZSMINVS
  7402  	{
  7403  		// ZSMINVS <Zn>.<T>, <Pg>, <V><d>
  7404  		{
  7405  			goOp:      AZSMINVS,
  7406  			fixedBits: 0x48a2000,
  7407  			args:      Zn_T__Pg__Vd__1,
  7408  		},
  7409  	},
  7410  	// ZSMLALB
  7411  	{
  7412  		// ZSMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7413  		{
  7414  			goOp:      AZSMLALB,
  7415  			fixedBits: 0x44004000,
  7416  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7417  		},
  7418  		// ZSMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7419  		{
  7420  			goOp:      AZSMLALB,
  7421  			fixedBits: 0x44a08000,
  7422  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7423  		},
  7424  		// ZSMLALB <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7425  		{
  7426  			goOp:      AZSMLALB,
  7427  			fixedBits: 0x44e08000,
  7428  			args:      Zm_S_imm___Zn_S__Zda_D,
  7429  		},
  7430  	},
  7431  	// ZSMLALT
  7432  	{
  7433  		// ZSMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7434  		{
  7435  			goOp:      AZSMLALT,
  7436  			fixedBits: 0x44004400,
  7437  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7438  		},
  7439  		// ZSMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7440  		{
  7441  			goOp:      AZSMLALT,
  7442  			fixedBits: 0x44a08400,
  7443  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7444  		},
  7445  		// ZSMLALT <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7446  		{
  7447  			goOp:      AZSMLALT,
  7448  			fixedBits: 0x44e08400,
  7449  			args:      Zm_S_imm___Zn_S__Zda_D,
  7450  		},
  7451  	},
  7452  	// ZSMLSLB
  7453  	{
  7454  		// ZSMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7455  		{
  7456  			goOp:      AZSMLSLB,
  7457  			fixedBits: 0x44005000,
  7458  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7459  		},
  7460  		// ZSMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7461  		{
  7462  			goOp:      AZSMLSLB,
  7463  			fixedBits: 0x44a0a000,
  7464  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7465  		},
  7466  		// ZSMLSLB <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7467  		{
  7468  			goOp:      AZSMLSLB,
  7469  			fixedBits: 0x44e0a000,
  7470  			args:      Zm_S_imm___Zn_S__Zda_D,
  7471  		},
  7472  	},
  7473  	// ZSMLSLT
  7474  	{
  7475  		// ZSMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7476  		{
  7477  			goOp:      AZSMLSLT,
  7478  			fixedBits: 0x44005400,
  7479  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7480  		},
  7481  		// ZSMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7482  		{
  7483  			goOp:      AZSMLSLT,
  7484  			fixedBits: 0x44a0a400,
  7485  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7486  		},
  7487  		// ZSMLSLT <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7488  		{
  7489  			goOp:      AZSMLSLT,
  7490  			fixedBits: 0x44e0a400,
  7491  			args:      Zm_S_imm___Zn_S__Zda_D,
  7492  		},
  7493  	},
  7494  	// ZSMMLA
  7495  	{
  7496  		// ZSMMLA <Zm>.B, <Zn>.B, <Zda>.S
  7497  		{
  7498  			goOp:      AZSMMLA,
  7499  			fixedBits: 0x45009800,
  7500  			args:      Zm_B__Zn_B__Zda_S,
  7501  		},
  7502  	},
  7503  	// ZSMULH
  7504  	{
  7505  		// ZSMULH <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7506  		{
  7507  			goOp:      AZSMULH,
  7508  			fixedBits: 0x4120000,
  7509  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7510  		},
  7511  		// ZSMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  7512  		{
  7513  			goOp:      AZSMULH,
  7514  			fixedBits: 0x4206800,
  7515  			args:      Zm_T__Zn_T__Zd_T__1,
  7516  		},
  7517  	},
  7518  	// ZSMULLB
  7519  	{
  7520  		// ZSMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  7521  		{
  7522  			goOp:      AZSMULLB,
  7523  			fixedBits: 0x45007000,
  7524  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  7525  		},
  7526  		// ZSMULLB <Zm>.H[<imm>], <Zn>.H, <Zd>.S
  7527  		{
  7528  			goOp:      AZSMULLB,
  7529  			fixedBits: 0x44a0c000,
  7530  			args:      Zm_H_imm___Zn_H__Zd_S,
  7531  		},
  7532  		// ZSMULLB <Zm>.S[<imm>], <Zn>.S, <Zd>.D
  7533  		{
  7534  			goOp:      AZSMULLB,
  7535  			fixedBits: 0x44e0c000,
  7536  			args:      Zm_S_imm___Zn_S__Zd_D,
  7537  		},
  7538  	},
  7539  	// ZSMULLT
  7540  	{
  7541  		// ZSMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  7542  		{
  7543  			goOp:      AZSMULLT,
  7544  			fixedBits: 0x45007400,
  7545  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  7546  		},
  7547  		// ZSMULLT <Zm>.H[<imm>], <Zn>.H, <Zd>.S
  7548  		{
  7549  			goOp:      AZSMULLT,
  7550  			fixedBits: 0x44a0c400,
  7551  			args:      Zm_H_imm___Zn_H__Zd_S,
  7552  		},
  7553  		// ZSMULLT <Zm>.S[<imm>], <Zn>.S, <Zd>.D
  7554  		{
  7555  			goOp:      AZSMULLT,
  7556  			fixedBits: 0x44e0c400,
  7557  			args:      Zm_S_imm___Zn_S__Zd_D,
  7558  		},
  7559  	},
  7560  	// ZSPLICE
  7561  	{
  7562  		// ZSPLICE <Zm>.<T>, <Zdn>.<T>, <Pv>, <Zdn>.<T>
  7563  		{
  7564  			goOp:      AZSPLICE,
  7565  			fixedBits: 0x52c8000,
  7566  			args:      Zm_T__Zdn_T__Pv__Zdn_T,
  7567  		},
  7568  		// ZSPLICE { <Zn1>.<T>, <Zn2>.<T> }, <Pv>, <Zd>.<T>
  7569  		{
  7570  			goOp:      AZSPLICE,
  7571  			fixedBits: 0x52d8000,
  7572  			args:      Zn1_T__Zn2_T___Pv__Zd_T,
  7573  		},
  7574  	},
  7575  	// ZSQABS
  7576  	{
  7577  		// ZSQABS <Zn>.<T>, <Pg>/M, <Zd>.<T>
  7578  		{
  7579  			goOp:      AZSQABS,
  7580  			fixedBits: 0x4408a000,
  7581  			args:      Zn_T__PgM__Zd_T__2,
  7582  		},
  7583  		// ZSQABS <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  7584  		{
  7585  			goOp:      AZSQABS,
  7586  			fixedBits: 0x440aa000,
  7587  			args:      Zn_T__PgZ__Zd_T__2,
  7588  		},
  7589  	},
  7590  	// ZSQADD
  7591  	{
  7592  		// ZSQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7593  		{
  7594  			goOp:      AZSQADD,
  7595  			fixedBits: 0x44188000,
  7596  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7597  		},
  7598  		// ZSQADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  7599  		{
  7600  			goOp:      AZSQADD,
  7601  			fixedBits: 0x4201000,
  7602  			args:      Zm_T__Zn_T__Zd_T__1,
  7603  		},
  7604  		// ZSQADD #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T>
  7605  		{
  7606  			goOp:      AZSQADD,
  7607  			fixedBits: 0x2524c000,
  7608  			args:      cimm__shift__Zdn_T__Zdn_T,
  7609  		},
  7610  	},
  7611  	// ZSQCADD
  7612  	{
  7613  		// ZSQCADD <const>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T>
  7614  		{
  7615  			goOp:      AZSQCADD,
  7616  			fixedBits: 0x4501d800,
  7617  			args:      const__Zm_T__Zdn_T__Zdn_T,
  7618  		},
  7619  	},
  7620  	// ZSQCVTN
  7621  	{
  7622  		// ZSQCVTN { <Zn1>.S-<Zn2>.S }, <Zd>.H
  7623  		{
  7624  			goOp:      AZSQCVTN,
  7625  			fixedBits: 0x45314000,
  7626  			args:      Zn1_S_Zn2_S___Zd_H,
  7627  		},
  7628  	},
  7629  	// ZSQCVTUN
  7630  	{
  7631  		// ZSQCVTUN { <Zn1>.S-<Zn2>.S }, <Zd>.H
  7632  		{
  7633  			goOp:      AZSQCVTUN,
  7634  			fixedBits: 0x45315000,
  7635  			args:      Zn1_S_Zn2_S___Zd_H,
  7636  		},
  7637  	},
  7638  	// ZSQDECP
  7639  	{
  7640  		// ZSQDECP <Pm>.<T>, <Zdn>.<T>
  7641  		{
  7642  			goOp:      AZSQDECP,
  7643  			fixedBits: 0x252a8000,
  7644  			args:      Pm_T__Zdn_T,
  7645  		},
  7646  	},
  7647  	// ZSQDMLALB
  7648  	{
  7649  		// ZSQDMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7650  		{
  7651  			goOp:      AZSQDMLALB,
  7652  			fixedBits: 0x44006000,
  7653  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7654  		},
  7655  		// ZSQDMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7656  		{
  7657  			goOp:      AZSQDMLALB,
  7658  			fixedBits: 0x44a02000,
  7659  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7660  		},
  7661  		// ZSQDMLALB <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7662  		{
  7663  			goOp:      AZSQDMLALB,
  7664  			fixedBits: 0x44e02000,
  7665  			args:      Zm_S_imm___Zn_S__Zda_D,
  7666  		},
  7667  	},
  7668  	// ZSQDMLALBT
  7669  	{
  7670  		// ZSQDMLALBT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7671  		{
  7672  			goOp:      AZSQDMLALBT,
  7673  			fixedBits: 0x44000800,
  7674  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7675  		},
  7676  	},
  7677  	// ZSQDMLALT
  7678  	{
  7679  		// ZSQDMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7680  		{
  7681  			goOp:      AZSQDMLALT,
  7682  			fixedBits: 0x44006400,
  7683  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7684  		},
  7685  		// ZSQDMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7686  		{
  7687  			goOp:      AZSQDMLALT,
  7688  			fixedBits: 0x44a02400,
  7689  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7690  		},
  7691  		// ZSQDMLALT <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7692  		{
  7693  			goOp:      AZSQDMLALT,
  7694  			fixedBits: 0x44e02400,
  7695  			args:      Zm_S_imm___Zn_S__Zda_D,
  7696  		},
  7697  	},
  7698  	// ZSQDMLSLB
  7699  	{
  7700  		// ZSQDMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7701  		{
  7702  			goOp:      AZSQDMLSLB,
  7703  			fixedBits: 0x44006800,
  7704  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7705  		},
  7706  		// ZSQDMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7707  		{
  7708  			goOp:      AZSQDMLSLB,
  7709  			fixedBits: 0x44a03000,
  7710  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7711  		},
  7712  		// ZSQDMLSLB <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7713  		{
  7714  			goOp:      AZSQDMLSLB,
  7715  			fixedBits: 0x44e03000,
  7716  			args:      Zm_S_imm___Zn_S__Zda_D,
  7717  		},
  7718  	},
  7719  	// ZSQDMLSLBT
  7720  	{
  7721  		// ZSQDMLSLBT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7722  		{
  7723  			goOp:      AZSQDMLSLBT,
  7724  			fixedBits: 0x44000c00,
  7725  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7726  		},
  7727  	},
  7728  	// ZSQDMLSLT
  7729  	{
  7730  		// ZSQDMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  7731  		{
  7732  			goOp:      AZSQDMLSLT,
  7733  			fixedBits: 0x44006c00,
  7734  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  7735  		},
  7736  		// ZSQDMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  7737  		{
  7738  			goOp:      AZSQDMLSLT,
  7739  			fixedBits: 0x44a03400,
  7740  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  7741  		},
  7742  		// ZSQDMLSLT <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  7743  		{
  7744  			goOp:      AZSQDMLSLT,
  7745  			fixedBits: 0x44e03400,
  7746  			args:      Zm_S_imm___Zn_S__Zda_D,
  7747  		},
  7748  	},
  7749  	// ZSQDMULH
  7750  	{
  7751  		// ZSQDMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  7752  		{
  7753  			goOp:      AZSQDMULH,
  7754  			fixedBits: 0x4207000,
  7755  			args:      Zm_T__Zn_T__Zd_T__1,
  7756  		},
  7757  		// ZSQDMULH <Zm>.D[<imm>], <Zn>.D, <Zd>.D
  7758  		{
  7759  			goOp:      AZSQDMULH,
  7760  			fixedBits: 0x44e0f000,
  7761  			args:      Zm_D_imm___Zn_D__Zd_D__1,
  7762  		},
  7763  		// ZSQDMULH <Zm>.H[<imm>], <Zn>.H, <Zd>.H
  7764  		{
  7765  			goOp:      AZSQDMULH,
  7766  			fixedBits: 0x4420f000,
  7767  			args:      Zm_H_imm___Zn_H__Zd_H__1,
  7768  		},
  7769  		// ZSQDMULH <Zm>.S[<imm>], <Zn>.S, <Zd>.S
  7770  		{
  7771  			goOp:      AZSQDMULH,
  7772  			fixedBits: 0x44a0f000,
  7773  			args:      Zm_S_imm___Zn_S__Zd_S__1,
  7774  		},
  7775  	},
  7776  	// ZSQDMULLB
  7777  	{
  7778  		// ZSQDMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  7779  		{
  7780  			goOp:      AZSQDMULLB,
  7781  			fixedBits: 0x45006000,
  7782  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  7783  		},
  7784  		// ZSQDMULLB <Zm>.H[<imm>], <Zn>.H, <Zd>.S
  7785  		{
  7786  			goOp:      AZSQDMULLB,
  7787  			fixedBits: 0x44a0e000,
  7788  			args:      Zm_H_imm___Zn_H__Zd_S,
  7789  		},
  7790  		// ZSQDMULLB <Zm>.S[<imm>], <Zn>.S, <Zd>.D
  7791  		{
  7792  			goOp:      AZSQDMULLB,
  7793  			fixedBits: 0x44e0e000,
  7794  			args:      Zm_S_imm___Zn_S__Zd_D,
  7795  		},
  7796  	},
  7797  	// ZSQDMULLT
  7798  	{
  7799  		// ZSQDMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  7800  		{
  7801  			goOp:      AZSQDMULLT,
  7802  			fixedBits: 0x45006400,
  7803  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  7804  		},
  7805  		// ZSQDMULLT <Zm>.H[<imm>], <Zn>.H, <Zd>.S
  7806  		{
  7807  			goOp:      AZSQDMULLT,
  7808  			fixedBits: 0x44a0e400,
  7809  			args:      Zm_H_imm___Zn_H__Zd_S,
  7810  		},
  7811  		// ZSQDMULLT <Zm>.S[<imm>], <Zn>.S, <Zd>.D
  7812  		{
  7813  			goOp:      AZSQDMULLT,
  7814  			fixedBits: 0x44e0e400,
  7815  			args:      Zm_S_imm___Zn_S__Zd_D,
  7816  		},
  7817  	},
  7818  	// ZSQINCP
  7819  	{
  7820  		// ZSQINCP <Pm>.<T>, <Zdn>.<T>
  7821  		{
  7822  			goOp:      AZSQINCP,
  7823  			fixedBits: 0x25288000,
  7824  			args:      Pm_T__Zdn_T,
  7825  		},
  7826  	},
  7827  	// ZSQNEG
  7828  	{
  7829  		// ZSQNEG <Zn>.<T>, <Pg>/M, <Zd>.<T>
  7830  		{
  7831  			goOp:      AZSQNEG,
  7832  			fixedBits: 0x4409a000,
  7833  			args:      Zn_T__PgM__Zd_T__2,
  7834  		},
  7835  		// ZSQNEG <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  7836  		{
  7837  			goOp:      AZSQNEG,
  7838  			fixedBits: 0x440ba000,
  7839  			args:      Zn_T__PgZ__Zd_T__2,
  7840  		},
  7841  	},
  7842  	// ZSQRDCMLAH
  7843  	{
  7844  		// ZSQRDCMLAH <const>, <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  7845  		{
  7846  			goOp:      AZSQRDCMLAH,
  7847  			fixedBits: 0x44a07000,
  7848  			args:      const__Zm_H_imm___Zn_H__Zda_H__1,
  7849  		},
  7850  		// ZSQRDCMLAH <const>, <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  7851  		{
  7852  			goOp:      AZSQRDCMLAH,
  7853  			fixedBits: 0x44e07000,
  7854  			args:      const__Zm_S_imm___Zn_S__Zda_S__1,
  7855  		},
  7856  		// ZSQRDCMLAH <const>, <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  7857  		{
  7858  			goOp:      AZSQRDCMLAH,
  7859  			fixedBits: 0x44003000,
  7860  			args:      const__Zm_T__Zn_T__Zda_T,
  7861  		},
  7862  	},
  7863  	// ZSQRDMLAH
  7864  	{
  7865  		// ZSQRDMLAH <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  7866  		{
  7867  			goOp:      AZSQRDMLAH,
  7868  			fixedBits: 0x44007000,
  7869  			args:      Zm_T__Zn_T__Zda_T__2,
  7870  		},
  7871  		// ZSQRDMLAH <Zm>.D[<imm>], <Zn>.D, <Zda>.D
  7872  		{
  7873  			goOp:      AZSQRDMLAH,
  7874  			fixedBits: 0x44e01000,
  7875  			args:      Zm_D_imm___Zn_D__Zda_D__1,
  7876  		},
  7877  		// ZSQRDMLAH <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  7878  		{
  7879  			goOp:      AZSQRDMLAH,
  7880  			fixedBits: 0x44201000,
  7881  			args:      Zm_H_imm___Zn_H__Zda_H__1,
  7882  		},
  7883  		// ZSQRDMLAH <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  7884  		{
  7885  			goOp:      AZSQRDMLAH,
  7886  			fixedBits: 0x44a01000,
  7887  			args:      Zm_S_imm___Zn_S__Zda_S__1,
  7888  		},
  7889  	},
  7890  	// ZSQRDMLSH
  7891  	{
  7892  		// ZSQRDMLSH <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  7893  		{
  7894  			goOp:      AZSQRDMLSH,
  7895  			fixedBits: 0x44007400,
  7896  			args:      Zm_T__Zn_T__Zda_T__2,
  7897  		},
  7898  		// ZSQRDMLSH <Zm>.D[<imm>], <Zn>.D, <Zda>.D
  7899  		{
  7900  			goOp:      AZSQRDMLSH,
  7901  			fixedBits: 0x44e01400,
  7902  			args:      Zm_D_imm___Zn_D__Zda_D__1,
  7903  		},
  7904  		// ZSQRDMLSH <Zm>.H[<imm>], <Zn>.H, <Zda>.H
  7905  		{
  7906  			goOp:      AZSQRDMLSH,
  7907  			fixedBits: 0x44201400,
  7908  			args:      Zm_H_imm___Zn_H__Zda_H__1,
  7909  		},
  7910  		// ZSQRDMLSH <Zm>.S[<imm>], <Zn>.S, <Zda>.S
  7911  		{
  7912  			goOp:      AZSQRDMLSH,
  7913  			fixedBits: 0x44a01400,
  7914  			args:      Zm_S_imm___Zn_S__Zda_S__1,
  7915  		},
  7916  	},
  7917  	// ZSQRDMULH
  7918  	{
  7919  		// ZSQRDMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  7920  		{
  7921  			goOp:      AZSQRDMULH,
  7922  			fixedBits: 0x4207400,
  7923  			args:      Zm_T__Zn_T__Zd_T__1,
  7924  		},
  7925  		// ZSQRDMULH <Zm>.D[<imm>], <Zn>.D, <Zd>.D
  7926  		{
  7927  			goOp:      AZSQRDMULH,
  7928  			fixedBits: 0x44e0f400,
  7929  			args:      Zm_D_imm___Zn_D__Zd_D__1,
  7930  		},
  7931  		// ZSQRDMULH <Zm>.H[<imm>], <Zn>.H, <Zd>.H
  7932  		{
  7933  			goOp:      AZSQRDMULH,
  7934  			fixedBits: 0x4420f400,
  7935  			args:      Zm_H_imm___Zn_H__Zd_H__1,
  7936  		},
  7937  		// ZSQRDMULH <Zm>.S[<imm>], <Zn>.S, <Zd>.S
  7938  		{
  7939  			goOp:      AZSQRDMULH,
  7940  			fixedBits: 0x44a0f400,
  7941  			args:      Zm_S_imm___Zn_S__Zd_S__1,
  7942  		},
  7943  	},
  7944  	// ZSQRSHL
  7945  	{
  7946  		// ZSQRSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7947  		{
  7948  			goOp:      AZSQRSHL,
  7949  			fixedBits: 0x440a8000,
  7950  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7951  		},
  7952  	},
  7953  	// ZSQRSHLR
  7954  	{
  7955  		// ZSQRSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  7956  		{
  7957  			goOp:      AZSQRSHLR,
  7958  			fixedBits: 0x440e8000,
  7959  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  7960  		},
  7961  	},
  7962  	// ZSQRSHRN
  7963  	{
  7964  		// ZSQRSHRN #<const>, { <Zn1>.H-<Zn2>.H }, <Zd>.B
  7965  		{
  7966  			goOp:      AZSQRSHRN,
  7967  			fixedBits: 0x45a82800,
  7968  			args:      cconst___Zn1_H_Zn2_H___Zd_B,
  7969  		},
  7970  		// ZSQRSHRN #<const>, { <Zn1>.S-<Zn2>.S }, <Zd>.H
  7971  		{
  7972  			goOp:      AZSQRSHRN,
  7973  			fixedBits: 0x45b02800,
  7974  			args:      cconst___Zn1_S_Zn2_S___Zd_H,
  7975  		},
  7976  	},
  7977  	// ZSQRSHRNB
  7978  	{
  7979  		// ZSQRSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T>
  7980  		{
  7981  			goOp:      AZSQRSHRNB,
  7982  			fixedBits: 0x45202800,
  7983  			args:      cconst__Zn_Tb__Zd_T__1,
  7984  		},
  7985  	},
  7986  	// ZSQRSHRNT
  7987  	{
  7988  		// ZSQRSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T>
  7989  		{
  7990  			goOp:      AZSQRSHRNT,
  7991  			fixedBits: 0x45202c00,
  7992  			args:      cconst__Zn_Tb__Zd_T__1,
  7993  		},
  7994  	},
  7995  	// ZSQRSHRUN
  7996  	{
  7997  		// ZSQRSHRUN #<const>, { <Zn1>.H-<Zn2>.H }, <Zd>.B
  7998  		{
  7999  			goOp:      AZSQRSHRUN,
  8000  			fixedBits: 0x45a80800,
  8001  			args:      cconst___Zn1_H_Zn2_H___Zd_B,
  8002  		},
  8003  		// ZSQRSHRUN #<const>, { <Zn1>.S-<Zn2>.S }, <Zd>.H
  8004  		{
  8005  			goOp:      AZSQRSHRUN,
  8006  			fixedBits: 0x45b00800,
  8007  			args:      cconst___Zn1_S_Zn2_S___Zd_H,
  8008  		},
  8009  	},
  8010  	// ZSQRSHRUNB
  8011  	{
  8012  		// ZSQRSHRUNB #<const>, <Zn>.<Tb>, <Zd>.<T>
  8013  		{
  8014  			goOp:      AZSQRSHRUNB,
  8015  			fixedBits: 0x45200800,
  8016  			args:      cconst__Zn_Tb__Zd_T__1,
  8017  		},
  8018  	},
  8019  	// ZSQRSHRUNT
  8020  	{
  8021  		// ZSQRSHRUNT #<const>, <Zn>.<Tb>, <Zd>.<T>
  8022  		{
  8023  			goOp:      AZSQRSHRUNT,
  8024  			fixedBits: 0x45200c00,
  8025  			args:      cconst__Zn_Tb__Zd_T__1,
  8026  		},
  8027  	},
  8028  	// ZSQSHL
  8029  	{
  8030  		// ZSQSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8031  		{
  8032  			goOp:      AZSQSHL,
  8033  			fixedBits: 0x44088000,
  8034  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  8035  		},
  8036  		// ZSQSHL #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8037  		{
  8038  			goOp:      AZSQSHL,
  8039  			fixedBits: 0x4068000,
  8040  			args:      cconst__Zdn_T__PgM__Zdn_T__2,
  8041  		},
  8042  	},
  8043  	// ZSQSHLR
  8044  	{
  8045  		// ZSQSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8046  		{
  8047  			goOp:      AZSQSHLR,
  8048  			fixedBits: 0x440c8000,
  8049  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  8050  		},
  8051  	},
  8052  	// ZSQSHLU
  8053  	{
  8054  		// ZSQSHLU #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8055  		{
  8056  			goOp:      AZSQSHLU,
  8057  			fixedBits: 0x40f8000,
  8058  			args:      cconst__Zdn_T__PgM__Zdn_T__2,
  8059  		},
  8060  	},
  8061  	// ZSQSHRN
  8062  	{
  8063  		// ZSQSHRN #<const>, { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zd>.<T>
  8064  		{
  8065  			goOp:      AZSQSHRN,
  8066  			fixedBits: 0x45a00000,
  8067  			args:      cconst___Zn1_Tb_Zn2_Tb___Zd_T,
  8068  		},
  8069  	},
  8070  	// ZSQSHRNB
  8071  	{
  8072  		// ZSQSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T>
  8073  		{
  8074  			goOp:      AZSQSHRNB,
  8075  			fixedBits: 0x45202000,
  8076  			args:      cconst__Zn_Tb__Zd_T__1,
  8077  		},
  8078  	},
  8079  	// ZSQSHRNT
  8080  	{
  8081  		// ZSQSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T>
  8082  		{
  8083  			goOp:      AZSQSHRNT,
  8084  			fixedBits: 0x45202400,
  8085  			args:      cconst__Zn_Tb__Zd_T__1,
  8086  		},
  8087  	},
  8088  	// ZSQSHRUN
  8089  	{
  8090  		// ZSQSHRUN #<const>, { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zd>.<T>
  8091  		{
  8092  			goOp:      AZSQSHRUN,
  8093  			fixedBits: 0x45a02000,
  8094  			args:      cconst___Zn1_Tb_Zn2_Tb___Zd_T,
  8095  		},
  8096  	},
  8097  	// ZSQSHRUNB
  8098  	{
  8099  		// ZSQSHRUNB #<const>, <Zn>.<Tb>, <Zd>.<T>
  8100  		{
  8101  			goOp:      AZSQSHRUNB,
  8102  			fixedBits: 0x45200000,
  8103  			args:      cconst__Zn_Tb__Zd_T__1,
  8104  		},
  8105  	},
  8106  	// ZSQSHRUNT
  8107  	{
  8108  		// ZSQSHRUNT #<const>, <Zn>.<Tb>, <Zd>.<T>
  8109  		{
  8110  			goOp:      AZSQSHRUNT,
  8111  			fixedBits: 0x45200400,
  8112  			args:      cconst__Zn_Tb__Zd_T__1,
  8113  		},
  8114  	},
  8115  	// ZSQSUB
  8116  	{
  8117  		// ZSQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8118  		{
  8119  			goOp:      AZSQSUB,
  8120  			fixedBits: 0x441a8000,
  8121  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  8122  		},
  8123  		// ZSQSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  8124  		{
  8125  			goOp:      AZSQSUB,
  8126  			fixedBits: 0x4201800,
  8127  			args:      Zm_T__Zn_T__Zd_T__1,
  8128  		},
  8129  		// ZSQSUB #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T>
  8130  		{
  8131  			goOp:      AZSQSUB,
  8132  			fixedBits: 0x2526c000,
  8133  			args:      cimm__shift__Zdn_T__Zdn_T,
  8134  		},
  8135  	},
  8136  	// ZSQSUBR
  8137  	{
  8138  		// ZSQSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8139  		{
  8140  			goOp:      AZSQSUBR,
  8141  			fixedBits: 0x441e8000,
  8142  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  8143  		},
  8144  	},
  8145  	// ZSQXTNB
  8146  	{
  8147  		// ZSQXTNB <Zn>.<Tb>, <Zd>.<T>
  8148  		{
  8149  			goOp:      AZSQXTNB,
  8150  			fixedBits: 0x45204000,
  8151  			args:      Zn_Tb__Zd_T__2,
  8152  		},
  8153  	},
  8154  	// ZSQXTNT
  8155  	{
  8156  		// ZSQXTNT <Zn>.<Tb>, <Zd>.<T>
  8157  		{
  8158  			goOp:      AZSQXTNT,
  8159  			fixedBits: 0x45204400,
  8160  			args:      Zn_Tb__Zd_T__2,
  8161  		},
  8162  	},
  8163  	// ZSQXTUNB
  8164  	{
  8165  		// ZSQXTUNB <Zn>.<Tb>, <Zd>.<T>
  8166  		{
  8167  			goOp:      AZSQXTUNB,
  8168  			fixedBits: 0x45205000,
  8169  			args:      Zn_Tb__Zd_T__2,
  8170  		},
  8171  	},
  8172  	// ZSQXTUNT
  8173  	{
  8174  		// ZSQXTUNT <Zn>.<Tb>, <Zd>.<T>
  8175  		{
  8176  			goOp:      AZSQXTUNT,
  8177  			fixedBits: 0x45205400,
  8178  			args:      Zn_Tb__Zd_T__2,
  8179  		},
  8180  	},
  8181  	// ZSRHADD
  8182  	{
  8183  		// ZSRHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8184  		{
  8185  			goOp:      AZSRHADD,
  8186  			fixedBits: 0x44148000,
  8187  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  8188  		},
  8189  	},
  8190  	// ZSRI
  8191  	{
  8192  		// ZSRI #<const>, <Zn>.<T>, <Zd>.<T>
  8193  		{
  8194  			goOp:      AZSRI,
  8195  			fixedBits: 0x4500f000,
  8196  			args:      cconst__Zn_T__Zd_T__1,
  8197  		},
  8198  	},
  8199  	// ZSRSHL
  8200  	{
  8201  		// ZSRSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8202  		{
  8203  			goOp:      AZSRSHL,
  8204  			fixedBits: 0x44028000,
  8205  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  8206  		},
  8207  	},
  8208  	// ZSRSHLR
  8209  	{
  8210  		// ZSRSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8211  		{
  8212  			goOp:      AZSRSHLR,
  8213  			fixedBits: 0x44068000,
  8214  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  8215  		},
  8216  	},
  8217  	// ZSRSHR
  8218  	{
  8219  		// ZSRSHR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  8220  		{
  8221  			goOp:      AZSRSHR,
  8222  			fixedBits: 0x40c8000,
  8223  			args:      cconst__Zdn_T__PgM__Zdn_T__1,
  8224  		},
  8225  	},
  8226  	// ZSRSRA
  8227  	{
  8228  		// ZSRSRA #<const>, <Zn>.<T>, <Zda>.<T>
  8229  		{
  8230  			goOp:      AZSRSRA,
  8231  			fixedBits: 0x4500e800,
  8232  			args:      cconst__Zn_T__Zda_T,
  8233  		},
  8234  	},
  8235  	// ZSSHLLB
  8236  	{
  8237  		// ZSSHLLB #<const>, <Zn>.<Tb>, <Zd>.<T>
  8238  		{
  8239  			goOp:      AZSSHLLB,
  8240  			fixedBits: 0x4500a000,
  8241  			args:      cconst__Zn_Tb__Zd_T__2,
  8242  		},
  8243  	},
  8244  	// ZSSHLLT
  8245  	{
  8246  		// ZSSHLLT #<const>, <Zn>.<Tb>, <Zd>.<T>
  8247  		{
  8248  			goOp:      AZSSHLLT,
  8249  			fixedBits: 0x4500a400,
  8250  			args:      cconst__Zn_Tb__Zd_T__2,
  8251  		},
  8252  	},
  8253  	// ZSSRA
  8254  	{
  8255  		// ZSSRA #<const>, <Zn>.<T>, <Zda>.<T>
  8256  		{
  8257  			goOp:      AZSSRA,
  8258  			fixedBits: 0x4500e000,
  8259  			args:      cconst__Zn_T__Zda_T,
  8260  		},
  8261  	},
  8262  	// ZSSUBLB
  8263  	{
  8264  		// ZSSUBLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  8265  		{
  8266  			goOp:      AZSSUBLB,
  8267  			fixedBits: 0x45001000,
  8268  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  8269  		},
  8270  	},
  8271  	// ZSSUBLBT
  8272  	{
  8273  		// ZSSUBLBT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  8274  		{
  8275  			goOp:      AZSSUBLBT,
  8276  			fixedBits: 0x45008800,
  8277  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  8278  		},
  8279  	},
  8280  	// ZSSUBLT
  8281  	{
  8282  		// ZSSUBLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  8283  		{
  8284  			goOp:      AZSSUBLT,
  8285  			fixedBits: 0x45001400,
  8286  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  8287  		},
  8288  	},
  8289  	// ZSSUBLTB
  8290  	{
  8291  		// ZSSUBLTB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  8292  		{
  8293  			goOp:      AZSSUBLTB,
  8294  			fixedBits: 0x45008c00,
  8295  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  8296  		},
  8297  	},
  8298  	// ZSSUBWB
  8299  	{
  8300  		// ZSSUBWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
  8301  		{
  8302  			goOp:      AZSSUBWB,
  8303  			fixedBits: 0x45005000,
  8304  			args:      Zm_Tb__Zn_T__Zd_T,
  8305  		},
  8306  	},
  8307  	// ZSSUBWT
  8308  	{
  8309  		// ZSSUBWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
  8310  		{
  8311  			goOp:      AZSSUBWT,
  8312  			fixedBits: 0x45005400,
  8313  			args:      Zm_Tb__Zn_T__Zd_T,
  8314  		},
  8315  	},
  8316  	// ZST1B
  8317  	{
  8318  		// ZST1B [<Xn|SP>, <Xm>], <Pg>, { <Zt>.<T> }
  8319  		{
  8320  			goOp:      AZST1B,
  8321  			fixedBits: 0xe4004000,
  8322  			args:      XnSP__Xm___Pg___Zt_T_,
  8323  		},
  8324  		// ZST1B [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
  8325  		{
  8326  			goOp:      AZST1B,
  8327  			fixedBits: 0xe400a000,
  8328  			args:      XnSP__Zm_D___Pg___Zt_D_,
  8329  		},
  8330  		// ZST1B [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
  8331  		{
  8332  			goOp:      AZST1B,
  8333  			fixedBits: 0xe4008000,
  8334  			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
  8335  		},
  8336  		// ZST1B [<Xn|SP>, <Zm>.S, <mod>], <Pg>, { <Zt>.S }
  8337  		{
  8338  			goOp:      AZST1B,
  8339  			fixedBits: 0xe4408000,
  8340  			args:      XnSP__Zm_S__mod___Pg___Zt_S_,
  8341  		},
  8342  		// ZST1B [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
  8343  		{
  8344  			goOp:      AZST1B,
  8345  			fixedBits: 0xe440a000,
  8346  			args:      Zn_D__cimm___Pg___Zt_D___1,
  8347  		},
  8348  		// ZST1B [<Zn>.S{, #<imm>}], <Pg>, { <Zt>.S }
  8349  		{
  8350  			goOp:      AZST1B,
  8351  			fixedBits: 0xe460a000,
  8352  			args:      Zn_S__cimm___Pg___Zt_S___1,
  8353  		},
  8354  		// ZST1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.<T> }
  8355  		{
  8356  			goOp:      AZST1B,
  8357  			fixedBits: 0xe400e000,
  8358  			args:      XnSP__cimm__MUL_VL___Pg___Zt_T___1,
  8359  		},
  8360  		// ZST1B [<Xn|SP>, <Xm>], <PNg>, { <Zt1>.B-<Zt2>.B }
  8361  		{
  8362  			goOp:      AZST1B,
  8363  			fixedBits: 0xa0200000,
  8364  			args:      XnSP__Xm___PNg___Zt1_B_Zt2_B_,
  8365  		},
  8366  		// ZST1B [<Xn|SP>, <Xm>], <PNg>, { <Zt1>.B-<Zt4>.B }
  8367  		{
  8368  			goOp:      AZST1B,
  8369  			fixedBits: 0xa0208000,
  8370  			args:      XnSP__Xm___PNg___Zt1_B_Zt4_B_,
  8371  		},
  8372  		// ZST1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.B-<Zt2>.B }
  8373  		{
  8374  			goOp:      AZST1B,
  8375  			fixedBits: 0xa0600000,
  8376  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_B_Zt2_B_,
  8377  		},
  8378  		// ZST1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.B-<Zt4>.B }
  8379  		{
  8380  			goOp:      AZST1B,
  8381  			fixedBits: 0xa0608000,
  8382  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_B_Zt4_B_,
  8383  		},
  8384  	},
  8385  	// ZST1D
  8386  	{
  8387  		// ZST1D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt>.D }
  8388  		{
  8389  			goOp:      AZST1D,
  8390  			fixedBits: 0xe5e04000,
  8391  			args:      XnSP__Xm__LSL_c3___Pg___Zt_D_,
  8392  		},
  8393  		// ZST1D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt>.Q }
  8394  		{
  8395  			goOp:      AZST1D,
  8396  			fixedBits: 0xe5c04000,
  8397  			args:      XnSP__Xm__LSL_c3___Pg___Zt_Q_,
  8398  		},
  8399  		// ZST1D [<Xn|SP>, <Zm>.D, LSL #3], <Pg>, { <Zt>.D }
  8400  		{
  8401  			goOp:      AZST1D,
  8402  			fixedBits: 0xe5a0a000,
  8403  			args:      XnSP__Zm_D__LSL_c3___Pg___Zt_D_,
  8404  		},
  8405  		// ZST1D [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
  8406  		{
  8407  			goOp:      AZST1D,
  8408  			fixedBits: 0xe580a000,
  8409  			args:      XnSP__Zm_D___Pg___Zt_D_,
  8410  		},
  8411  		// ZST1D [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
  8412  		{
  8413  			goOp:      AZST1D,
  8414  			fixedBits: 0xe5808000,
  8415  			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
  8416  		},
  8417  		// ZST1D [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>, { <Zt>.D }
  8418  		{
  8419  			goOp:      AZST1D,
  8420  			fixedBits: 0xe5a08000,
  8421  			args:      XnSP__Zm_D__mod_c3___Pg___Zt_D_,
  8422  		},
  8423  		// ZST1D [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
  8424  		{
  8425  			goOp:      AZST1D,
  8426  			fixedBits: 0xe5c0a000,
  8427  			args:      Zn_D__cimm___Pg___Zt_D___2,
  8428  		},
  8429  		// ZST1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.D }
  8430  		{
  8431  			goOp:      AZST1D,
  8432  			fixedBits: 0xe5e0e000,
  8433  			args:      XnSP__cimm__MUL_VL___Pg___Zt_D_,
  8434  		},
  8435  		// ZST1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.Q }
  8436  		{
  8437  			goOp:      AZST1D,
  8438  			fixedBits: 0xe5c0e000,
  8439  			args:      XnSP__cimm__MUL_VL___Pg___Zt_Q_,
  8440  		},
  8441  		// ZST1D [<Xn|SP>, <Xm>, LSL #3], <PNg>, { <Zt1>.D-<Zt2>.D }
  8442  		{
  8443  			goOp:      AZST1D,
  8444  			fixedBits: 0xa0206000,
  8445  			args:      XnSP__Xm__LSL_c3___PNg___Zt1_D_Zt2_D_,
  8446  		},
  8447  		// ZST1D [<Xn|SP>, <Xm>, LSL #3], <PNg>, { <Zt1>.D-<Zt4>.D }
  8448  		{
  8449  			goOp:      AZST1D,
  8450  			fixedBits: 0xa020e000,
  8451  			args:      XnSP__Xm__LSL_c3___PNg___Zt1_D_Zt4_D_,
  8452  		},
  8453  		// ZST1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.D-<Zt2>.D }
  8454  		{
  8455  			goOp:      AZST1D,
  8456  			fixedBits: 0xa0606000,
  8457  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_D_Zt2_D_,
  8458  		},
  8459  		// ZST1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.D-<Zt4>.D }
  8460  		{
  8461  			goOp:      AZST1D,
  8462  			fixedBits: 0xa060e000,
  8463  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_D_Zt4_D_,
  8464  		},
  8465  	},
  8466  	// ZST1H
  8467  	{
  8468  		// ZST1H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt>.<T> }
  8469  		{
  8470  			goOp:      AZST1H,
  8471  			fixedBits: 0xe4804000,
  8472  			args:      XnSP__Xm__LSL_c1___Pg___Zt_T_,
  8473  		},
  8474  		// ZST1H [<Xn|SP>, <Zm>.D, LSL #1], <Pg>, { <Zt>.D }
  8475  		{
  8476  			goOp:      AZST1H,
  8477  			fixedBits: 0xe4a0a000,
  8478  			args:      XnSP__Zm_D__LSL_c1___Pg___Zt_D_,
  8479  		},
  8480  		// ZST1H [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
  8481  		{
  8482  			goOp:      AZST1H,
  8483  			fixedBits: 0xe480a000,
  8484  			args:      XnSP__Zm_D___Pg___Zt_D_,
  8485  		},
  8486  		// ZST1H [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
  8487  		{
  8488  			goOp:      AZST1H,
  8489  			fixedBits: 0xe4808000,
  8490  			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
  8491  		},
  8492  		// ZST1H [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>, { <Zt>.D }
  8493  		{
  8494  			goOp:      AZST1H,
  8495  			fixedBits: 0xe4a08000,
  8496  			args:      XnSP__Zm_D__mod_c1___Pg___Zt_D_,
  8497  		},
  8498  		// ZST1H [<Xn|SP>, <Zm>.S, <mod>], <Pg>, { <Zt>.S }
  8499  		{
  8500  			goOp:      AZST1H,
  8501  			fixedBits: 0xe4c08000,
  8502  			args:      XnSP__Zm_S__mod___Pg___Zt_S_,
  8503  		},
  8504  		// ZST1H [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>, { <Zt>.S }
  8505  		{
  8506  			goOp:      AZST1H,
  8507  			fixedBits: 0xe4e08000,
  8508  			args:      XnSP__Zm_S__mod_c1___Pg___Zt_S_,
  8509  		},
  8510  		// ZST1H [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
  8511  		{
  8512  			goOp:      AZST1H,
  8513  			fixedBits: 0xe4c0a000,
  8514  			args:      Zn_D__cimm___Pg___Zt_D___3,
  8515  		},
  8516  		// ZST1H [<Zn>.S{, #<imm>}], <Pg>, { <Zt>.S }
  8517  		{
  8518  			goOp:      AZST1H,
  8519  			fixedBits: 0xe4e0a000,
  8520  			args:      Zn_S__cimm___Pg___Zt_S___2,
  8521  		},
  8522  		// ZST1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.<T> }
  8523  		{
  8524  			goOp:      AZST1H,
  8525  			fixedBits: 0xe480e000,
  8526  			args:      XnSP__cimm__MUL_VL___Pg___Zt_T___2,
  8527  		},
  8528  		// ZST1H [<Xn|SP>, <Xm>, LSL #1], <PNg>, { <Zt1>.H-<Zt2>.H }
  8529  		{
  8530  			goOp:      AZST1H,
  8531  			fixedBits: 0xa0202000,
  8532  			args:      XnSP__Xm__LSL_c1___PNg___Zt1_H_Zt2_H_,
  8533  		},
  8534  		// ZST1H [<Xn|SP>, <Xm>, LSL #1], <PNg>, { <Zt1>.H-<Zt4>.H }
  8535  		{
  8536  			goOp:      AZST1H,
  8537  			fixedBits: 0xa020a000,
  8538  			args:      XnSP__Xm__LSL_c1___PNg___Zt1_H_Zt4_H_,
  8539  		},
  8540  		// ZST1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.H-<Zt2>.H }
  8541  		{
  8542  			goOp:      AZST1H,
  8543  			fixedBits: 0xa0602000,
  8544  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_H_Zt2_H_,
  8545  		},
  8546  		// ZST1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.H-<Zt4>.H }
  8547  		{
  8548  			goOp:      AZST1H,
  8549  			fixedBits: 0xa060a000,
  8550  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_H_Zt4_H_,
  8551  		},
  8552  	},
  8553  	// ZST1Q
  8554  	{
  8555  		// ZST1Q [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.Q }
  8556  		{
  8557  			goOp:      AZST1Q,
  8558  			fixedBits: 0xe4202000,
  8559  			args:      Zn_D__Xm___Pg___Zt_Q_,
  8560  		},
  8561  	},
  8562  	// ZST1W
  8563  	{
  8564  		// ZST1W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt>.Q }
  8565  		{
  8566  			goOp:      AZST1W,
  8567  			fixedBits: 0xe5004000,
  8568  			args:      XnSP__Xm__LSL_c2___Pg___Zt_Q_,
  8569  		},
  8570  		// ZST1W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt>.<T> }
  8571  		{
  8572  			goOp:      AZST1W,
  8573  			fixedBits: 0xe5404000,
  8574  			args:      XnSP__Xm__LSL_c2___Pg___Zt_T_,
  8575  		},
  8576  		// ZST1W [<Xn|SP>, <Zm>.D, LSL #2], <Pg>, { <Zt>.D }
  8577  		{
  8578  			goOp:      AZST1W,
  8579  			fixedBits: 0xe520a000,
  8580  			args:      XnSP__Zm_D__LSL_c2___Pg___Zt_D_,
  8581  		},
  8582  		// ZST1W [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
  8583  		{
  8584  			goOp:      AZST1W,
  8585  			fixedBits: 0xe500a000,
  8586  			args:      XnSP__Zm_D___Pg___Zt_D_,
  8587  		},
  8588  		// ZST1W [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
  8589  		{
  8590  			goOp:      AZST1W,
  8591  			fixedBits: 0xe5008000,
  8592  			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
  8593  		},
  8594  		// ZST1W [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>, { <Zt>.D }
  8595  		{
  8596  			goOp:      AZST1W,
  8597  			fixedBits: 0xe5208000,
  8598  			args:      XnSP__Zm_D__mod_c2___Pg___Zt_D_,
  8599  		},
  8600  		// ZST1W [<Xn|SP>, <Zm>.S, <mod>], <Pg>, { <Zt>.S }
  8601  		{
  8602  			goOp:      AZST1W,
  8603  			fixedBits: 0xe5408000,
  8604  			args:      XnSP__Zm_S__mod___Pg___Zt_S_,
  8605  		},
  8606  		// ZST1W [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>, { <Zt>.S }
  8607  		{
  8608  			goOp:      AZST1W,
  8609  			fixedBits: 0xe5608000,
  8610  			args:      XnSP__Zm_S__mod_c2___Pg___Zt_S_,
  8611  		},
  8612  		// ZST1W [<Zn>.D{, #<imm>}], <Pg>, { <Zt>.D }
  8613  		{
  8614  			goOp:      AZST1W,
  8615  			fixedBits: 0xe540a000,
  8616  			args:      Zn_D__cimm___Pg___Zt_D___4,
  8617  		},
  8618  		// ZST1W [<Zn>.S{, #<imm>}], <Pg>, { <Zt>.S }
  8619  		{
  8620  			goOp:      AZST1W,
  8621  			fixedBits: 0xe560a000,
  8622  			args:      Zn_S__cimm___Pg___Zt_S___3,
  8623  		},
  8624  		// ZST1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.Q }
  8625  		{
  8626  			goOp:      AZST1W,
  8627  			fixedBits: 0xe500e000,
  8628  			args:      XnSP__cimm__MUL_VL___Pg___Zt_Q_,
  8629  		},
  8630  		// ZST1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.<T> }
  8631  		{
  8632  			goOp:      AZST1W,
  8633  			fixedBits: 0xe540e000,
  8634  			args:      XnSP__cimm__MUL_VL___Pg___Zt_T___3,
  8635  		},
  8636  		// ZST1W [<Xn|SP>, <Xm>, LSL #2], <PNg>, { <Zt1>.S-<Zt2>.S }
  8637  		{
  8638  			goOp:      AZST1W,
  8639  			fixedBits: 0xa0204000,
  8640  			args:      XnSP__Xm__LSL_c2___PNg___Zt1_S_Zt2_S_,
  8641  		},
  8642  		// ZST1W [<Xn|SP>, <Xm>, LSL #2], <PNg>, { <Zt1>.S-<Zt4>.S }
  8643  		{
  8644  			goOp:      AZST1W,
  8645  			fixedBits: 0xa020c000,
  8646  			args:      XnSP__Xm__LSL_c2___PNg___Zt1_S_Zt4_S_,
  8647  		},
  8648  		// ZST1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.S-<Zt2>.S }
  8649  		{
  8650  			goOp:      AZST1W,
  8651  			fixedBits: 0xa0604000,
  8652  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_S_Zt2_S_,
  8653  		},
  8654  		// ZST1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.S-<Zt4>.S }
  8655  		{
  8656  			goOp:      AZST1W,
  8657  			fixedBits: 0xa060c000,
  8658  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_S_Zt4_S_,
  8659  		},
  8660  	},
  8661  	// ZST2B
  8662  	{
  8663  		// ZST2B [<Xn|SP>, <Xm>], <Pg>, { <Zt1>.B, <Zt2>.B }
  8664  		{
  8665  			goOp:      AZST2B,
  8666  			fixedBits: 0xe4206000,
  8667  			args:      XnSP__Xm___Pg___Zt1_B__Zt2_B_,
  8668  		},
  8669  		// ZST2B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.B, <Zt2>.B }
  8670  		{
  8671  			goOp:      AZST2B,
  8672  			fixedBits: 0xe430e000,
  8673  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B_,
  8674  		},
  8675  	},
  8676  	// ZST2D
  8677  	{
  8678  		// ZST2D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt1>.D, <Zt2>.D }
  8679  		{
  8680  			goOp:      AZST2D,
  8681  			fixedBits: 0xe5a06000,
  8682  			args:      XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D_,
  8683  		},
  8684  		// ZST2D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.D, <Zt2>.D }
  8685  		{
  8686  			goOp:      AZST2D,
  8687  			fixedBits: 0xe5b0e000,
  8688  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D_,
  8689  		},
  8690  	},
  8691  	// ZST2H
  8692  	{
  8693  		// ZST2H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt1>.H, <Zt2>.H }
  8694  		{
  8695  			goOp:      AZST2H,
  8696  			fixedBits: 0xe4a06000,
  8697  			args:      XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H_,
  8698  		},
  8699  		// ZST2H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.H, <Zt2>.H }
  8700  		{
  8701  			goOp:      AZST2H,
  8702  			fixedBits: 0xe4b0e000,
  8703  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H_,
  8704  		},
  8705  	},
  8706  	// ZST2Q
  8707  	{
  8708  		// ZST2Q [<Xn|SP>, <Xm>, LSL #4], <Pg>, { <Zt1>.Q, <Zt2>.Q }
  8709  		{
  8710  			goOp:      AZST2Q,
  8711  			fixedBits: 0xe4600000,
  8712  			args:      XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q_,
  8713  		},
  8714  		// ZST2Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.Q, <Zt2>.Q }
  8715  		{
  8716  			goOp:      AZST2Q,
  8717  			fixedBits: 0xe4400000,
  8718  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q_,
  8719  		},
  8720  	},
  8721  	// ZST2W
  8722  	{
  8723  		// ZST2W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt1>.S, <Zt2>.S }
  8724  		{
  8725  			goOp:      AZST2W,
  8726  			fixedBits: 0xe5206000,
  8727  			args:      XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S_,
  8728  		},
  8729  		// ZST2W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.S, <Zt2>.S }
  8730  		{
  8731  			goOp:      AZST2W,
  8732  			fixedBits: 0xe530e000,
  8733  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S_,
  8734  		},
  8735  	},
  8736  	// ZST3B
  8737  	{
  8738  		// ZST3B [<Xn|SP>, <Xm>], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
  8739  		{
  8740  			goOp:      AZST3B,
  8741  			fixedBits: 0xe4406000,
  8742  			args:      XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B_,
  8743  		},
  8744  		// ZST3B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
  8745  		{
  8746  			goOp:      AZST3B,
  8747  			fixedBits: 0xe450e000,
  8748  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B_,
  8749  		},
  8750  	},
  8751  	// ZST3D
  8752  	{
  8753  		// ZST3D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
  8754  		{
  8755  			goOp:      AZST3D,
  8756  			fixedBits: 0xe5c06000,
  8757  			args:      XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D_,
  8758  		},
  8759  		// ZST3D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
  8760  		{
  8761  			goOp:      AZST3D,
  8762  			fixedBits: 0xe5d0e000,
  8763  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D_,
  8764  		},
  8765  	},
  8766  	// ZST3H
  8767  	{
  8768  		// ZST3H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
  8769  		{
  8770  			goOp:      AZST3H,
  8771  			fixedBits: 0xe4c06000,
  8772  			args:      XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H_,
  8773  		},
  8774  		// ZST3H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
  8775  		{
  8776  			goOp:      AZST3H,
  8777  			fixedBits: 0xe4d0e000,
  8778  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H_,
  8779  		},
  8780  	},
  8781  	// ZST3Q
  8782  	{
  8783  		// ZST3Q [<Xn|SP>, <Xm>, LSL #4], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
  8784  		{
  8785  			goOp:      AZST3Q,
  8786  			fixedBits: 0xe4a00000,
  8787  			args:      XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q_,
  8788  		},
  8789  		// ZST3Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
  8790  		{
  8791  			goOp:      AZST3Q,
  8792  			fixedBits: 0xe4800000,
  8793  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q_,
  8794  		},
  8795  	},
  8796  	// ZST3W
  8797  	{
  8798  		// ZST3W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
  8799  		{
  8800  			goOp:      AZST3W,
  8801  			fixedBits: 0xe5406000,
  8802  			args:      XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S_,
  8803  		},
  8804  		// ZST3W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
  8805  		{
  8806  			goOp:      AZST3W,
  8807  			fixedBits: 0xe550e000,
  8808  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S_,
  8809  		},
  8810  	},
  8811  	// ZST4B
  8812  	{
  8813  		// ZST4B [<Xn|SP>, <Xm>], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
  8814  		{
  8815  			goOp:      AZST4B,
  8816  			fixedBits: 0xe4606000,
  8817  			args:      XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
  8818  		},
  8819  		// ZST4B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
  8820  		{
  8821  			goOp:      AZST4B,
  8822  			fixedBits: 0xe470e000,
  8823  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
  8824  		},
  8825  	},
  8826  	// ZST4D
  8827  	{
  8828  		// ZST4D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
  8829  		{
  8830  			goOp:      AZST4D,
  8831  			fixedBits: 0xe5e06000,
  8832  			args:      XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
  8833  		},
  8834  		// ZST4D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
  8835  		{
  8836  			goOp:      AZST4D,
  8837  			fixedBits: 0xe5f0e000,
  8838  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
  8839  		},
  8840  	},
  8841  	// ZST4H
  8842  	{
  8843  		// ZST4H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
  8844  		{
  8845  			goOp:      AZST4H,
  8846  			fixedBits: 0xe4e06000,
  8847  			args:      XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
  8848  		},
  8849  		// ZST4H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
  8850  		{
  8851  			goOp:      AZST4H,
  8852  			fixedBits: 0xe4f0e000,
  8853  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
  8854  		},
  8855  	},
  8856  	// ZST4Q
  8857  	{
  8858  		// ZST4Q [<Xn|SP>, <Xm>, LSL #4], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
  8859  		{
  8860  			goOp:      AZST4Q,
  8861  			fixedBits: 0xe4e00000,
  8862  			args:      XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
  8863  		},
  8864  		// ZST4Q [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
  8865  		{
  8866  			goOp:      AZST4Q,
  8867  			fixedBits: 0xe4c00000,
  8868  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
  8869  		},
  8870  	},
  8871  	// ZST4W
  8872  	{
  8873  		// ZST4W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
  8874  		{
  8875  			goOp:      AZST4W,
  8876  			fixedBits: 0xe5606000,
  8877  			args:      XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
  8878  		},
  8879  		// ZST4W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
  8880  		{
  8881  			goOp:      AZST4W,
  8882  			fixedBits: 0xe570e000,
  8883  			args:      XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
  8884  		},
  8885  	},
  8886  	// ZSTNT1B
  8887  	{
  8888  		// ZSTNT1B [<Xn|SP>, <Xm>], <Pg>, { <Zt>.B }
  8889  		{
  8890  			goOp:      AZSTNT1B,
  8891  			fixedBits: 0xe4006000,
  8892  			args:      XnSP__Xm___Pg___Zt_B_,
  8893  		},
  8894  		// ZSTNT1B [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
  8895  		{
  8896  			goOp:      AZSTNT1B,
  8897  			fixedBits: 0xe4002000,
  8898  			args:      Zn_D__Xm___Pg___Zt_D_,
  8899  		},
  8900  		// ZSTNT1B [<Zn>.S{, <Xm>}], <Pg>, { <Zt>.S }
  8901  		{
  8902  			goOp:      AZSTNT1B,
  8903  			fixedBits: 0xe4402000,
  8904  			args:      Zn_S__Xm___Pg___Zt_S_,
  8905  		},
  8906  		// ZSTNT1B [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.B }
  8907  		{
  8908  			goOp:      AZSTNT1B,
  8909  			fixedBits: 0xe410e000,
  8910  			args:      XnSP__cimm__MUL_VL___Pg___Zt_B_,
  8911  		},
  8912  		// ZSTNT1B [<Xn|SP>, <Xm>], <PNg>, { <Zt1>.B-<Zt2>.B }
  8913  		{
  8914  			goOp:      AZSTNT1B,
  8915  			fixedBits: 0xa0200001,
  8916  			args:      XnSP__Xm___PNg___Zt1_B_Zt2_B_,
  8917  		},
  8918  		// ZSTNT1B [<Xn|SP>, <Xm>], <PNg>, { <Zt1>.B-<Zt4>.B }
  8919  		{
  8920  			goOp:      AZSTNT1B,
  8921  			fixedBits: 0xa0208001,
  8922  			args:      XnSP__Xm___PNg___Zt1_B_Zt4_B_,
  8923  		},
  8924  		// ZSTNT1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.B-<Zt2>.B }
  8925  		{
  8926  			goOp:      AZSTNT1B,
  8927  			fixedBits: 0xa0600001,
  8928  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_B_Zt2_B_,
  8929  		},
  8930  		// ZSTNT1B [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.B-<Zt4>.B }
  8931  		{
  8932  			goOp:      AZSTNT1B,
  8933  			fixedBits: 0xa0608001,
  8934  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_B_Zt4_B_,
  8935  		},
  8936  	},
  8937  	// ZSTNT1D
  8938  	{
  8939  		// ZSTNT1D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt>.D }
  8940  		{
  8941  			goOp:      AZSTNT1D,
  8942  			fixedBits: 0xe5806000,
  8943  			args:      XnSP__Xm__LSL_c3___Pg___Zt_D_,
  8944  		},
  8945  		// ZSTNT1D [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
  8946  		{
  8947  			goOp:      AZSTNT1D,
  8948  			fixedBits: 0xe5802000,
  8949  			args:      Zn_D__Xm___Pg___Zt_D_,
  8950  		},
  8951  		// ZSTNT1D [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.D }
  8952  		{
  8953  			goOp:      AZSTNT1D,
  8954  			fixedBits: 0xe590e000,
  8955  			args:      XnSP__cimm__MUL_VL___Pg___Zt_D_,
  8956  		},
  8957  		// ZSTNT1D [<Xn|SP>, <Xm>, LSL #3], <PNg>, { <Zt1>.D-<Zt2>.D }
  8958  		{
  8959  			goOp:      AZSTNT1D,
  8960  			fixedBits: 0xa0206001,
  8961  			args:      XnSP__Xm__LSL_c3___PNg___Zt1_D_Zt2_D_,
  8962  		},
  8963  		// ZSTNT1D [<Xn|SP>, <Xm>, LSL #3], <PNg>, { <Zt1>.D-<Zt4>.D }
  8964  		{
  8965  			goOp:      AZSTNT1D,
  8966  			fixedBits: 0xa020e001,
  8967  			args:      XnSP__Xm__LSL_c3___PNg___Zt1_D_Zt4_D_,
  8968  		},
  8969  		// ZSTNT1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.D-<Zt2>.D }
  8970  		{
  8971  			goOp:      AZSTNT1D,
  8972  			fixedBits: 0xa0606001,
  8973  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_D_Zt2_D_,
  8974  		},
  8975  		// ZSTNT1D [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.D-<Zt4>.D }
  8976  		{
  8977  			goOp:      AZSTNT1D,
  8978  			fixedBits: 0xa060e001,
  8979  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_D_Zt4_D_,
  8980  		},
  8981  	},
  8982  	// ZSTNT1H
  8983  	{
  8984  		// ZSTNT1H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt>.H }
  8985  		{
  8986  			goOp:      AZSTNT1H,
  8987  			fixedBits: 0xe4806000,
  8988  			args:      XnSP__Xm__LSL_c1___Pg___Zt_H_,
  8989  		},
  8990  		// ZSTNT1H [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
  8991  		{
  8992  			goOp:      AZSTNT1H,
  8993  			fixedBits: 0xe4802000,
  8994  			args:      Zn_D__Xm___Pg___Zt_D_,
  8995  		},
  8996  		// ZSTNT1H [<Zn>.S{, <Xm>}], <Pg>, { <Zt>.S }
  8997  		{
  8998  			goOp:      AZSTNT1H,
  8999  			fixedBits: 0xe4c02000,
  9000  			args:      Zn_S__Xm___Pg___Zt_S_,
  9001  		},
  9002  		// ZSTNT1H [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.H }
  9003  		{
  9004  			goOp:      AZSTNT1H,
  9005  			fixedBits: 0xe490e000,
  9006  			args:      XnSP__cimm__MUL_VL___Pg___Zt_H_,
  9007  		},
  9008  		// ZSTNT1H [<Xn|SP>, <Xm>, LSL #1], <PNg>, { <Zt1>.H-<Zt2>.H }
  9009  		{
  9010  			goOp:      AZSTNT1H,
  9011  			fixedBits: 0xa0202001,
  9012  			args:      XnSP__Xm__LSL_c1___PNg___Zt1_H_Zt2_H_,
  9013  		},
  9014  		// ZSTNT1H [<Xn|SP>, <Xm>, LSL #1], <PNg>, { <Zt1>.H-<Zt4>.H }
  9015  		{
  9016  			goOp:      AZSTNT1H,
  9017  			fixedBits: 0xa020a001,
  9018  			args:      XnSP__Xm__LSL_c1___PNg___Zt1_H_Zt4_H_,
  9019  		},
  9020  		// ZSTNT1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.H-<Zt2>.H }
  9021  		{
  9022  			goOp:      AZSTNT1H,
  9023  			fixedBits: 0xa0602001,
  9024  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_H_Zt2_H_,
  9025  		},
  9026  		// ZSTNT1H [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.H-<Zt4>.H }
  9027  		{
  9028  			goOp:      AZSTNT1H,
  9029  			fixedBits: 0xa060a001,
  9030  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_H_Zt4_H_,
  9031  		},
  9032  	},
  9033  	// ZSTNT1W
  9034  	{
  9035  		// ZSTNT1W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt>.S }
  9036  		{
  9037  			goOp:      AZSTNT1W,
  9038  			fixedBits: 0xe5006000,
  9039  			args:      XnSP__Xm__LSL_c2___Pg___Zt_S_,
  9040  		},
  9041  		// ZSTNT1W [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
  9042  		{
  9043  			goOp:      AZSTNT1W,
  9044  			fixedBits: 0xe5002000,
  9045  			args:      Zn_D__Xm___Pg___Zt_D_,
  9046  		},
  9047  		// ZSTNT1W [<Zn>.S{, <Xm>}], <Pg>, { <Zt>.S }
  9048  		{
  9049  			goOp:      AZSTNT1W,
  9050  			fixedBits: 0xe5402000,
  9051  			args:      Zn_S__Xm___Pg___Zt_S_,
  9052  		},
  9053  		// ZSTNT1W [<Xn|SP>{, #<imm>, MUL VL}], <Pg>, { <Zt>.S }
  9054  		{
  9055  			goOp:      AZSTNT1W,
  9056  			fixedBits: 0xe510e000,
  9057  			args:      XnSP__cimm__MUL_VL___Pg___Zt_S_,
  9058  		},
  9059  		// ZSTNT1W [<Xn|SP>, <Xm>, LSL #2], <PNg>, { <Zt1>.S-<Zt2>.S }
  9060  		{
  9061  			goOp:      AZSTNT1W,
  9062  			fixedBits: 0xa0204001,
  9063  			args:      XnSP__Xm__LSL_c2___PNg___Zt1_S_Zt2_S_,
  9064  		},
  9065  		// ZSTNT1W [<Xn|SP>, <Xm>, LSL #2], <PNg>, { <Zt1>.S-<Zt4>.S }
  9066  		{
  9067  			goOp:      AZSTNT1W,
  9068  			fixedBits: 0xa020c001,
  9069  			args:      XnSP__Xm__LSL_c2___PNg___Zt1_S_Zt4_S_,
  9070  		},
  9071  		// ZSTNT1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.S-<Zt2>.S }
  9072  		{
  9073  			goOp:      AZSTNT1W,
  9074  			fixedBits: 0xa0604001,
  9075  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_S_Zt2_S_,
  9076  		},
  9077  		// ZSTNT1W [<Xn|SP>{, #<imm>, MUL VL}], <PNg>, { <Zt1>.S-<Zt4>.S }
  9078  		{
  9079  			goOp:      AZSTNT1W,
  9080  			fixedBits: 0xa060c001,
  9081  			args:      XnSP__cimm__MUL_VL___PNg___Zt1_S_Zt4_S_,
  9082  		},
  9083  	},
  9084  	// ZSTR
  9085  	{
  9086  		// ZSTR [<Xn|SP>{, #<imm>, MUL VL}], <Zt>
  9087  		{
  9088  			goOp:      AZSTR,
  9089  			fixedBits: 0xe5804000,
  9090  			args:      XnSP__cimm__MUL_VL___Zt,
  9091  		},
  9092  	},
  9093  	// ZSUB
  9094  	{
  9095  		// ZSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9096  		{
  9097  			goOp:      AZSUB,
  9098  			fixedBits: 0x4010000,
  9099  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9100  		},
  9101  		// ZSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9102  		{
  9103  			goOp:      AZSUB,
  9104  			fixedBits: 0x4200400,
  9105  			args:      Zm_T__Zn_T__Zd_T__1,
  9106  		},
  9107  		// ZSUB #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T>
  9108  		{
  9109  			goOp:      AZSUB,
  9110  			fixedBits: 0x2521c000,
  9111  			args:      cimm__shift__Zdn_T__Zdn_T,
  9112  		},
  9113  	},
  9114  	// ZSUBHNB
  9115  	{
  9116  		// ZSUBHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9117  		{
  9118  			goOp:      AZSUBHNB,
  9119  			fixedBits: 0x45207000,
  9120  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  9121  		},
  9122  	},
  9123  	// ZSUBHNT
  9124  	{
  9125  		// ZSUBHNT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9126  		{
  9127  			goOp:      AZSUBHNT,
  9128  			fixedBits: 0x45207400,
  9129  			args:      Zm_Tb__Zn_Tb__Zd_T__2,
  9130  		},
  9131  	},
  9132  	// ZSUBP
  9133  	{
  9134  		// ZSUBP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9135  		{
  9136  			goOp:      AZSUBP,
  9137  			fixedBits: 0x4410a000,
  9138  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9139  		},
  9140  	},
  9141  	// ZSUBPT
  9142  	{
  9143  		// ZSUBPT <Zm>.D, <Zdn>.D, <Pg>/M, <Zdn>.D
  9144  		{
  9145  			goOp:      AZSUBPT,
  9146  			fixedBits: 0x4c50000,
  9147  			args:      Zm_D__Zdn_D__PgM__Zdn_D,
  9148  		},
  9149  		// ZSUBPT <Zm>.D, <Zn>.D, <Zd>.D
  9150  		{
  9151  			goOp:      AZSUBPT,
  9152  			fixedBits: 0x4e00c00,
  9153  			args:      Zm_D__Zn_D__Zd_D,
  9154  		},
  9155  	},
  9156  	// ZSUBR
  9157  	{
  9158  		// ZSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9159  		{
  9160  			goOp:      AZSUBR,
  9161  			fixedBits: 0x4030000,
  9162  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9163  		},
  9164  		// ZSUBR #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T>
  9165  		{
  9166  			goOp:      AZSUBR,
  9167  			fixedBits: 0x2523c000,
  9168  			args:      cimm__shift__Zdn_T__Zdn_T,
  9169  		},
  9170  	},
  9171  	// ZSUDOT
  9172  	{
  9173  		// ZSUDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  9174  		{
  9175  			goOp:      AZSUDOT,
  9176  			fixedBits: 0x44a01c00,
  9177  			args:      Zm_B_imm___Zn_B__Zda_S__2,
  9178  		},
  9179  	},
  9180  	// ZSUNPKHI
  9181  	{
  9182  		// ZSUNPKHI <Zn>.<Tb>, <Zd>.<T>
  9183  		{
  9184  			goOp:      AZSUNPKHI,
  9185  			fixedBits: 0x5313800,
  9186  			args:      Zn_Tb__Zd_T__1,
  9187  		},
  9188  	},
  9189  	// ZSUNPKLO
  9190  	{
  9191  		// ZSUNPKLO <Zn>.<Tb>, <Zd>.<T>
  9192  		{
  9193  			goOp:      AZSUNPKLO,
  9194  			fixedBits: 0x5303800,
  9195  			args:      Zn_Tb__Zd_T__1,
  9196  		},
  9197  	},
  9198  	// ZSUQADD
  9199  	{
  9200  		// ZSUQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9201  		{
  9202  			goOp:      AZSUQADD,
  9203  			fixedBits: 0x441c8000,
  9204  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9205  		},
  9206  	},
  9207  	// ZSXTB
  9208  	{
  9209  		// ZSXTB <Zn>.<T>, <Pg>/M, <Zd>.<T>
  9210  		{
  9211  			goOp:      AZSXTB,
  9212  			fixedBits: 0x410a000,
  9213  			args:      Zn_T__PgM__Zd_T__4,
  9214  		},
  9215  		// ZSXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  9216  		{
  9217  			goOp:      AZSXTB,
  9218  			fixedBits: 0x400a000,
  9219  			args:      Zn_T__PgZ__Zd_T__4,
  9220  		},
  9221  	},
  9222  	// ZSXTH
  9223  	{
  9224  		// ZSXTH <Zn>.<T>, <Pg>/M, <Zd>.<T>
  9225  		{
  9226  			goOp:      AZSXTH,
  9227  			fixedBits: 0x492a000,
  9228  			args:      Zn_T__PgM__Zd_T__5,
  9229  		},
  9230  		// ZSXTH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
  9231  		{
  9232  			goOp:      AZSXTH,
  9233  			fixedBits: 0x482a000,
  9234  			args:      Zn_T__PgZ__Zd_T__5,
  9235  		},
  9236  	},
  9237  	// ZSXTW
  9238  	{
  9239  		// ZSXTW <Zn>.D, <Pg>/M, <Zd>.D
  9240  		{
  9241  			goOp:      AZSXTW,
  9242  			fixedBits: 0x4d4a000,
  9243  			args:      Zn_D__PgM__Zd_D,
  9244  		},
  9245  		// ZSXTW <Zn>.D, <Pg>/Z, <Zd>.D
  9246  		{
  9247  			goOp:      AZSXTW,
  9248  			fixedBits: 0x4c4a000,
  9249  			args:      Zn_D__PgZ__Zd_D,
  9250  		},
  9251  	},
  9252  	// ZTBL
  9253  	{
  9254  		// ZTBL <Zm>.<T>, { <Zn1>.<T>, <Zn2>.<T> }, <Zd>.<T>
  9255  		{
  9256  			goOp:      AZTBL,
  9257  			fixedBits: 0x5202800,
  9258  			args:      Zm_T___Zn1_T__Zn2_T___Zd_T,
  9259  		},
  9260  		// ZTBL <Zm>.<T>, { <Zn>.<T> }, <Zd>.<T>
  9261  		{
  9262  			goOp:      AZTBL,
  9263  			fixedBits: 0x5203000,
  9264  			args:      Zm_T___Zn_T___Zd_T,
  9265  		},
  9266  	},
  9267  	// ZTBLQ
  9268  	{
  9269  		// ZTBLQ <Zm>.<T>, { <Zn>.<T> }, <Zd>.<T>
  9270  		{
  9271  			goOp:      AZTBLQ,
  9272  			fixedBits: 0x4400f800,
  9273  			args:      Zm_T___Zn_T___Zd_T,
  9274  		},
  9275  	},
  9276  	// ZTBX
  9277  	{
  9278  		// ZTBX <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9279  		{
  9280  			goOp:      AZTBX,
  9281  			fixedBits: 0x5202c00,
  9282  			args:      Zm_T__Zn_T__Zd_T__1,
  9283  		},
  9284  	},
  9285  	// ZTBXQ
  9286  	{
  9287  		// ZTBXQ <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9288  		{
  9289  			goOp:      AZTBXQ,
  9290  			fixedBits: 0x5203400,
  9291  			args:      Zm_T__Zn_T__Zd_T__1,
  9292  		},
  9293  	},
  9294  	// ZTRN1
  9295  	{
  9296  		// ZTRN1 <Zm>.Q, <Zn>.Q, <Zd>.Q
  9297  		{
  9298  			goOp:      AZTRN1,
  9299  			fixedBits: 0x5a01800,
  9300  			args:      Zm_Q__Zn_Q__Zd_Q,
  9301  		},
  9302  		// ZTRN1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9303  		{
  9304  			goOp:      AZTRN1,
  9305  			fixedBits: 0x5207000,
  9306  			args:      Zm_T__Zn_T__Zd_T__1,
  9307  		},
  9308  	},
  9309  	// ZTRN2
  9310  	{
  9311  		// ZTRN2 <Zm>.Q, <Zn>.Q, <Zd>.Q
  9312  		{
  9313  			goOp:      AZTRN2,
  9314  			fixedBits: 0x5a01c00,
  9315  			args:      Zm_Q__Zn_Q__Zd_Q,
  9316  		},
  9317  		// ZTRN2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9318  		{
  9319  			goOp:      AZTRN2,
  9320  			fixedBits: 0x5207400,
  9321  			args:      Zm_T__Zn_T__Zd_T__1,
  9322  		},
  9323  	},
  9324  	// ZUABA
  9325  	{
  9326  		// ZUABA <Zm>.<T>, <Zn>.<T>, <Zda>.<T>
  9327  		{
  9328  			goOp:      AZUABA,
  9329  			fixedBits: 0x4500fc00,
  9330  			args:      Zm_T__Zn_T__Zda_T__2,
  9331  		},
  9332  	},
  9333  	// ZUABAL
  9334  	{
  9335  		// ZUABAL <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9336  		{
  9337  			goOp:      AZUABAL,
  9338  			fixedBits: 0x4400dc00,
  9339  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  9340  		},
  9341  	},
  9342  	// ZUABALB
  9343  	{
  9344  		// ZUABALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9345  		{
  9346  			goOp:      AZUABALB,
  9347  			fixedBits: 0x4500c800,
  9348  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  9349  		},
  9350  	},
  9351  	// ZUABALT
  9352  	{
  9353  		// ZUABALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9354  		{
  9355  			goOp:      AZUABALT,
  9356  			fixedBits: 0x4500cc00,
  9357  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  9358  		},
  9359  	},
  9360  	// ZUABD
  9361  	{
  9362  		// ZUABD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9363  		{
  9364  			goOp:      AZUABD,
  9365  			fixedBits: 0x40d0000,
  9366  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9367  		},
  9368  	},
  9369  	// ZUABDLB
  9370  	{
  9371  		// ZUABDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9372  		{
  9373  			goOp:      AZUABDLB,
  9374  			fixedBits: 0x45003800,
  9375  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  9376  		},
  9377  	},
  9378  	// ZUABDLT
  9379  	{
  9380  		// ZUABDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9381  		{
  9382  			goOp:      AZUABDLT,
  9383  			fixedBits: 0x45003c00,
  9384  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  9385  		},
  9386  	},
  9387  	// ZUADALP
  9388  	{
  9389  		// ZUADALP <Zn>.<Tb>, <Pg>/M, <Zda>.<T>
  9390  		{
  9391  			goOp:      AZUADALP,
  9392  			fixedBits: 0x4405a000,
  9393  			args:      Zn_Tb__PgM__Zda_T,
  9394  		},
  9395  	},
  9396  	// ZUADDLB
  9397  	{
  9398  		// ZUADDLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9399  		{
  9400  			goOp:      AZUADDLB,
  9401  			fixedBits: 0x45000800,
  9402  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  9403  		},
  9404  	},
  9405  	// ZUADDLT
  9406  	{
  9407  		// ZUADDLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9408  		{
  9409  			goOp:      AZUADDLT,
  9410  			fixedBits: 0x45000c00,
  9411  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  9412  		},
  9413  	},
  9414  	// ZUADDVD
  9415  	{
  9416  		// ZUADDVD <Zn>.<T>, <Pg>, <Dd>
  9417  		{
  9418  			goOp:      AZUADDVD,
  9419  			fixedBits: 0x4012000,
  9420  			args:      Zn_T__Pg__Dd__2,
  9421  		},
  9422  	},
  9423  	// ZUADDWB
  9424  	{
  9425  		// ZUADDWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
  9426  		{
  9427  			goOp:      AZUADDWB,
  9428  			fixedBits: 0x45004800,
  9429  			args:      Zm_Tb__Zn_T__Zd_T,
  9430  		},
  9431  	},
  9432  	// ZUADDWT
  9433  	{
  9434  		// ZUADDWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
  9435  		{
  9436  			goOp:      AZUADDWT,
  9437  			fixedBits: 0x45004c00,
  9438  			args:      Zm_Tb__Zn_T__Zd_T,
  9439  		},
  9440  	},
  9441  	// ZUCLAMP
  9442  	{
  9443  		// ZUCLAMP <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9444  		{
  9445  			goOp:      AZUCLAMP,
  9446  			fixedBits: 0x4400c400,
  9447  			args:      Zm_T__Zn_T__Zd_T__1,
  9448  		},
  9449  	},
  9450  	// ZUCVTF
  9451  	{
  9452  		// ZUCVTF <Zn>.D, <Pg>/M, <Zd>.D
  9453  		{
  9454  			goOp:      AZUCVTF,
  9455  			fixedBits: 0x65d7a000,
  9456  			args:      Zn_D__PgM__Zd_D,
  9457  		},
  9458  		// ZUCVTF <Zn>.D, <Pg>/M, <Zd>.H
  9459  		{
  9460  			goOp:      AZUCVTF,
  9461  			fixedBits: 0x6557a000,
  9462  			args:      Zn_D__PgM__Zd_H,
  9463  		},
  9464  		// ZUCVTF <Zn>.D, <Pg>/M, <Zd>.S
  9465  		{
  9466  			goOp:      AZUCVTF,
  9467  			fixedBits: 0x65d5a000,
  9468  			args:      Zn_D__PgM__Zd_S,
  9469  		},
  9470  		// ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.D
  9471  		{
  9472  			goOp:      AZUCVTF,
  9473  			fixedBits: 0x64dde000,
  9474  			args:      Zn_D__PgZ__Zd_D,
  9475  		},
  9476  		// ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.H
  9477  		{
  9478  			goOp:      AZUCVTF,
  9479  			fixedBits: 0x645de000,
  9480  			args:      Zn_D__PgZ__Zd_H,
  9481  		},
  9482  		// ZUCVTF <Zn>.D, <Pg>/Z, <Zd>.S
  9483  		{
  9484  			goOp:      AZUCVTF,
  9485  			fixedBits: 0x64dda000,
  9486  			args:      Zn_D__PgZ__Zd_S,
  9487  		},
  9488  		// ZUCVTF <Zn>.H, <Pg>/M, <Zd>.H
  9489  		{
  9490  			goOp:      AZUCVTF,
  9491  			fixedBits: 0x6553a000,
  9492  			args:      Zn_H__PgM__Zd_H,
  9493  		},
  9494  		// ZUCVTF <Zn>.H, <Pg>/Z, <Zd>.H
  9495  		{
  9496  			goOp:      AZUCVTF,
  9497  			fixedBits: 0x645ce000,
  9498  			args:      Zn_H__PgZ__Zd_H,
  9499  		},
  9500  		// ZUCVTF <Zn>.S, <Pg>/M, <Zd>.D
  9501  		{
  9502  			goOp:      AZUCVTF,
  9503  			fixedBits: 0x65d1a000,
  9504  			args:      Zn_S__PgM__Zd_D,
  9505  		},
  9506  		// ZUCVTF <Zn>.S, <Pg>/M, <Zd>.H
  9507  		{
  9508  			goOp:      AZUCVTF,
  9509  			fixedBits: 0x6555a000,
  9510  			args:      Zn_S__PgM__Zd_H,
  9511  		},
  9512  		// ZUCVTF <Zn>.S, <Pg>/M, <Zd>.S
  9513  		{
  9514  			goOp:      AZUCVTF,
  9515  			fixedBits: 0x6595a000,
  9516  			args:      Zn_S__PgM__Zd_S,
  9517  		},
  9518  		// ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.D
  9519  		{
  9520  			goOp:      AZUCVTF,
  9521  			fixedBits: 0x64dca000,
  9522  			args:      Zn_S__PgZ__Zd_D,
  9523  		},
  9524  		// ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.H
  9525  		{
  9526  			goOp:      AZUCVTF,
  9527  			fixedBits: 0x645da000,
  9528  			args:      Zn_S__PgZ__Zd_H,
  9529  		},
  9530  		// ZUCVTF <Zn>.S, <Pg>/Z, <Zd>.S
  9531  		{
  9532  			goOp:      AZUCVTF,
  9533  			fixedBits: 0x649da000,
  9534  			args:      Zn_S__PgZ__Zd_S,
  9535  		},
  9536  		// ZUCVTF <Zn>.<Tb>, <Zd>.<T>
  9537  		{
  9538  			goOp:      AZUCVTF,
  9539  			fixedBits: 0x650c3400,
  9540  			args:      Zn_Tb__Zd_T__1,
  9541  		},
  9542  	},
  9543  	// ZUCVTFLT
  9544  	{
  9545  		// ZUCVTFLT <Zn>.<Tb>, <Zd>.<T>
  9546  		{
  9547  			goOp:      AZUCVTFLT,
  9548  			fixedBits: 0x650c3c00,
  9549  			args:      Zn_Tb__Zd_T__1,
  9550  		},
  9551  	},
  9552  	// ZUDIV
  9553  	{
  9554  		// ZUDIV <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9555  		{
  9556  			goOp:      AZUDIV,
  9557  			fixedBits: 0x4950000,
  9558  			args:      Zm_T__Zdn_T__PgM__Zdn_T__4,
  9559  		},
  9560  	},
  9561  	// ZUDIVR
  9562  	{
  9563  		// ZUDIVR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9564  		{
  9565  			goOp:      AZUDIVR,
  9566  			fixedBits: 0x4970000,
  9567  			args:      Zm_T__Zdn_T__PgM__Zdn_T__4,
  9568  		},
  9569  	},
  9570  	// ZUDOT
  9571  	{
  9572  		// ZUDOT <Zm>.B, <Zn>.B, <Zda>.H
  9573  		{
  9574  			goOp:      AZUDOT,
  9575  			fixedBits: 0x44400400,
  9576  			args:      Zm_B__Zn_B__Zda_H,
  9577  		},
  9578  		// ZUDOT <Zm>.H, <Zn>.H, <Zda>.S
  9579  		{
  9580  			goOp:      AZUDOT,
  9581  			fixedBits: 0x4400cc00,
  9582  			args:      Zm_H__Zn_H__Zda_S,
  9583  		},
  9584  		// ZUDOT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9585  		{
  9586  			goOp:      AZUDOT,
  9587  			fixedBits: 0x44800400,
  9588  			args:      Zm_Tb__Zn_Tb__Zda_T__2,
  9589  		},
  9590  		// ZUDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.H
  9591  		{
  9592  			goOp:      AZUDOT,
  9593  			fixedBits: 0x44200400,
  9594  			args:      Zm_B_imm___Zn_B__Zda_H__2,
  9595  		},
  9596  		// ZUDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S
  9597  		{
  9598  			goOp:      AZUDOT,
  9599  			fixedBits: 0x44a00400,
  9600  			args:      Zm_B_imm___Zn_B__Zda_S__3,
  9601  		},
  9602  		// ZUDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.D
  9603  		{
  9604  			goOp:      AZUDOT,
  9605  			fixedBits: 0x44e00400,
  9606  			args:      Zm_H_imm___Zn_H__Zda_D,
  9607  		},
  9608  		// ZUDOT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  9609  		{
  9610  			goOp:      AZUDOT,
  9611  			fixedBits: 0x4480cc00,
  9612  			args:      Zm_H_imm___Zn_H__Zda_S__4,
  9613  		},
  9614  	},
  9615  	// ZUHADD
  9616  	{
  9617  		// ZUHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9618  		{
  9619  			goOp:      AZUHADD,
  9620  			fixedBits: 0x44118000,
  9621  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9622  		},
  9623  	},
  9624  	// ZUHSUB
  9625  	{
  9626  		// ZUHSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9627  		{
  9628  			goOp:      AZUHSUB,
  9629  			fixedBits: 0x44138000,
  9630  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9631  		},
  9632  	},
  9633  	// ZUHSUBR
  9634  	{
  9635  		// ZUHSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9636  		{
  9637  			goOp:      AZUHSUBR,
  9638  			fixedBits: 0x44178000,
  9639  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9640  		},
  9641  	},
  9642  	// ZUMAX
  9643  	{
  9644  		// ZUMAX <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9645  		{
  9646  			goOp:      AZUMAX,
  9647  			fixedBits: 0x4090000,
  9648  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9649  		},
  9650  		// ZUMAX #<imm>, <Zdn>.<T>, <Zdn>.<T>
  9651  		{
  9652  			goOp:      AZUMAX,
  9653  			fixedBits: 0x2529c000,
  9654  			args:      cimm__Zdn_T__Zdn_T__2,
  9655  		},
  9656  	},
  9657  	// ZUMAXP
  9658  	{
  9659  		// ZUMAXP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9660  		{
  9661  			goOp:      AZUMAXP,
  9662  			fixedBits: 0x4415a000,
  9663  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9664  		},
  9665  	},
  9666  	// ZUMAXQV
  9667  	{
  9668  		// ZUMAXQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  9669  		{
  9670  			goOp:      AZUMAXQV,
  9671  			fixedBits: 0x40d2000,
  9672  			args:      Zn_Tb__Pg__Vd_T__1,
  9673  		},
  9674  	},
  9675  	// ZUMAXVB
  9676  	{
  9677  		// ZUMAXVB <Zn>.<T>, <Pg>, <V><d>
  9678  		{
  9679  			goOp:      AZUMAXVB,
  9680  			fixedBits: 0x4092000,
  9681  			args:      Zn_T__Pg__Vd__1,
  9682  		},
  9683  	},
  9684  	// ZUMAXVD
  9685  	{
  9686  		// ZUMAXVD <Zn>.<T>, <Pg>, <V><d>
  9687  		{
  9688  			goOp:      AZUMAXVD,
  9689  			fixedBits: 0x4c92000,
  9690  			args:      Zn_T__Pg__Vd__1,
  9691  		},
  9692  	},
  9693  	// ZUMAXVH
  9694  	{
  9695  		// ZUMAXVH <Zn>.<T>, <Pg>, <V><d>
  9696  		{
  9697  			goOp:      AZUMAXVH,
  9698  			fixedBits: 0x4492000,
  9699  			args:      Zn_T__Pg__Vd__1,
  9700  		},
  9701  	},
  9702  	// ZUMAXVS
  9703  	{
  9704  		// ZUMAXVS <Zn>.<T>, <Pg>, <V><d>
  9705  		{
  9706  			goOp:      AZUMAXVS,
  9707  			fixedBits: 0x4892000,
  9708  			args:      Zn_T__Pg__Vd__1,
  9709  		},
  9710  	},
  9711  	// ZUMIN
  9712  	{
  9713  		// ZUMIN <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9714  		{
  9715  			goOp:      AZUMIN,
  9716  			fixedBits: 0x40b0000,
  9717  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9718  		},
  9719  		// ZUMIN #<imm>, <Zdn>.<T>, <Zdn>.<T>
  9720  		{
  9721  			goOp:      AZUMIN,
  9722  			fixedBits: 0x252bc000,
  9723  			args:      cimm__Zdn_T__Zdn_T__2,
  9724  		},
  9725  	},
  9726  	// ZUMINP
  9727  	{
  9728  		// ZUMINP <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9729  		{
  9730  			goOp:      AZUMINP,
  9731  			fixedBits: 0x4417a000,
  9732  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9733  		},
  9734  	},
  9735  	// ZUMINQV
  9736  	{
  9737  		// ZUMINQV <Zn>.<Tb>, <Pg>, <Vd>.<T>
  9738  		{
  9739  			goOp:      AZUMINQV,
  9740  			fixedBits: 0x40f2000,
  9741  			args:      Zn_Tb__Pg__Vd_T__1,
  9742  		},
  9743  	},
  9744  	// ZUMINVB
  9745  	{
  9746  		// ZUMINVB <Zn>.<T>, <Pg>, <V><d>
  9747  		{
  9748  			goOp:      AZUMINVB,
  9749  			fixedBits: 0x40b2000,
  9750  			args:      Zn_T__Pg__Vd__1,
  9751  		},
  9752  	},
  9753  	// ZUMINVD
  9754  	{
  9755  		// ZUMINVD <Zn>.<T>, <Pg>, <V><d>
  9756  		{
  9757  			goOp:      AZUMINVD,
  9758  			fixedBits: 0x4cb2000,
  9759  			args:      Zn_T__Pg__Vd__1,
  9760  		},
  9761  	},
  9762  	// ZUMINVH
  9763  	{
  9764  		// ZUMINVH <Zn>.<T>, <Pg>, <V><d>
  9765  		{
  9766  			goOp:      AZUMINVH,
  9767  			fixedBits: 0x44b2000,
  9768  			args:      Zn_T__Pg__Vd__1,
  9769  		},
  9770  	},
  9771  	// ZUMINVS
  9772  	{
  9773  		// ZUMINVS <Zn>.<T>, <Pg>, <V><d>
  9774  		{
  9775  			goOp:      AZUMINVS,
  9776  			fixedBits: 0x48b2000,
  9777  			args:      Zn_T__Pg__Vd__1,
  9778  		},
  9779  	},
  9780  	// ZUMLALB
  9781  	{
  9782  		// ZUMLALB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9783  		{
  9784  			goOp:      AZUMLALB,
  9785  			fixedBits: 0x44004800,
  9786  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  9787  		},
  9788  		// ZUMLALB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  9789  		{
  9790  			goOp:      AZUMLALB,
  9791  			fixedBits: 0x44a09000,
  9792  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  9793  		},
  9794  		// ZUMLALB <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  9795  		{
  9796  			goOp:      AZUMLALB,
  9797  			fixedBits: 0x44e09000,
  9798  			args:      Zm_S_imm___Zn_S__Zda_D,
  9799  		},
  9800  	},
  9801  	// ZUMLALT
  9802  	{
  9803  		// ZUMLALT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9804  		{
  9805  			goOp:      AZUMLALT,
  9806  			fixedBits: 0x44004c00,
  9807  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  9808  		},
  9809  		// ZUMLALT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  9810  		{
  9811  			goOp:      AZUMLALT,
  9812  			fixedBits: 0x44a09400,
  9813  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  9814  		},
  9815  		// ZUMLALT <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  9816  		{
  9817  			goOp:      AZUMLALT,
  9818  			fixedBits: 0x44e09400,
  9819  			args:      Zm_S_imm___Zn_S__Zda_D,
  9820  		},
  9821  	},
  9822  	// ZUMLSLB
  9823  	{
  9824  		// ZUMLSLB <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9825  		{
  9826  			goOp:      AZUMLSLB,
  9827  			fixedBits: 0x44005800,
  9828  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  9829  		},
  9830  		// ZUMLSLB <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  9831  		{
  9832  			goOp:      AZUMLSLB,
  9833  			fixedBits: 0x44a0b000,
  9834  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  9835  		},
  9836  		// ZUMLSLB <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  9837  		{
  9838  			goOp:      AZUMLSLB,
  9839  			fixedBits: 0x44e0b000,
  9840  			args:      Zm_S_imm___Zn_S__Zda_D,
  9841  		},
  9842  	},
  9843  	// ZUMLSLT
  9844  	{
  9845  		// ZUMLSLT <Zm>.<Tb>, <Zn>.<Tb>, <Zda>.<T>
  9846  		{
  9847  			goOp:      AZUMLSLT,
  9848  			fixedBits: 0x44005c00,
  9849  			args:      Zm_Tb__Zn_Tb__Zda_T__1,
  9850  		},
  9851  		// ZUMLSLT <Zm>.H[<imm>], <Zn>.H, <Zda>.S
  9852  		{
  9853  			goOp:      AZUMLSLT,
  9854  			fixedBits: 0x44a0b400,
  9855  			args:      Zm_H_imm___Zn_H__Zda_S__1,
  9856  		},
  9857  		// ZUMLSLT <Zm>.S[<imm>], <Zn>.S, <Zda>.D
  9858  		{
  9859  			goOp:      AZUMLSLT,
  9860  			fixedBits: 0x44e0b400,
  9861  			args:      Zm_S_imm___Zn_S__Zda_D,
  9862  		},
  9863  	},
  9864  	// ZUMMLA
  9865  	{
  9866  		// ZUMMLA <Zm>.B, <Zn>.B, <Zda>.S
  9867  		{
  9868  			goOp:      AZUMMLA,
  9869  			fixedBits: 0x45c09800,
  9870  			args:      Zm_B__Zn_B__Zda_S,
  9871  		},
  9872  	},
  9873  	// ZUMULH
  9874  	{
  9875  		// ZUMULH <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9876  		{
  9877  			goOp:      AZUMULH,
  9878  			fixedBits: 0x4130000,
  9879  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9880  		},
  9881  		// ZUMULH <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9882  		{
  9883  			goOp:      AZUMULH,
  9884  			fixedBits: 0x4206c00,
  9885  			args:      Zm_T__Zn_T__Zd_T__1,
  9886  		},
  9887  	},
  9888  	// ZUMULLB
  9889  	{
  9890  		// ZUMULLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9891  		{
  9892  			goOp:      AZUMULLB,
  9893  			fixedBits: 0x45007800,
  9894  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  9895  		},
  9896  		// ZUMULLB <Zm>.H[<imm>], <Zn>.H, <Zd>.S
  9897  		{
  9898  			goOp:      AZUMULLB,
  9899  			fixedBits: 0x44a0d000,
  9900  			args:      Zm_H_imm___Zn_H__Zd_S,
  9901  		},
  9902  		// ZUMULLB <Zm>.S[<imm>], <Zn>.S, <Zd>.D
  9903  		{
  9904  			goOp:      AZUMULLB,
  9905  			fixedBits: 0x44e0d000,
  9906  			args:      Zm_S_imm___Zn_S__Zd_D,
  9907  		},
  9908  	},
  9909  	// ZUMULLT
  9910  	{
  9911  		// ZUMULLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
  9912  		{
  9913  			goOp:      AZUMULLT,
  9914  			fixedBits: 0x45007c00,
  9915  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
  9916  		},
  9917  		// ZUMULLT <Zm>.H[<imm>], <Zn>.H, <Zd>.S
  9918  		{
  9919  			goOp:      AZUMULLT,
  9920  			fixedBits: 0x44a0d400,
  9921  			args:      Zm_H_imm___Zn_H__Zd_S,
  9922  		},
  9923  		// ZUMULLT <Zm>.S[<imm>], <Zn>.S, <Zd>.D
  9924  		{
  9925  			goOp:      AZUMULLT,
  9926  			fixedBits: 0x44e0d400,
  9927  			args:      Zm_S_imm___Zn_S__Zd_D,
  9928  		},
  9929  	},
  9930  	// ZUQADD
  9931  	{
  9932  		// ZUQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9933  		{
  9934  			goOp:      AZUQADD,
  9935  			fixedBits: 0x44198000,
  9936  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9937  		},
  9938  		// ZUQADD <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
  9939  		{
  9940  			goOp:      AZUQADD,
  9941  			fixedBits: 0x4201400,
  9942  			args:      Zm_T__Zn_T__Zd_T__1,
  9943  		},
  9944  		// ZUQADD #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T>
  9945  		{
  9946  			goOp:      AZUQADD,
  9947  			fixedBits: 0x2525c000,
  9948  			args:      cimm__shift__Zdn_T__Zdn_T,
  9949  		},
  9950  	},
  9951  	// ZUQCVTN
  9952  	{
  9953  		// ZUQCVTN { <Zn1>.S-<Zn2>.S }, <Zd>.H
  9954  		{
  9955  			goOp:      AZUQCVTN,
  9956  			fixedBits: 0x45314800,
  9957  			args:      Zn1_S_Zn2_S___Zd_H,
  9958  		},
  9959  	},
  9960  	// ZUQDECP
  9961  	{
  9962  		// ZUQDECP <Pm>.<T>, <Zdn>.<T>
  9963  		{
  9964  			goOp:      AZUQDECP,
  9965  			fixedBits: 0x252b8000,
  9966  			args:      Pm_T__Zdn_T,
  9967  		},
  9968  	},
  9969  	// ZUQINCP
  9970  	{
  9971  		// ZUQINCP <Pm>.<T>, <Zdn>.<T>
  9972  		{
  9973  			goOp:      AZUQINCP,
  9974  			fixedBits: 0x25298000,
  9975  			args:      Pm_T__Zdn_T,
  9976  		},
  9977  	},
  9978  	// ZUQRSHL
  9979  	{
  9980  		// ZUQRSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9981  		{
  9982  			goOp:      AZUQRSHL,
  9983  			fixedBits: 0x440b8000,
  9984  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9985  		},
  9986  	},
  9987  	// ZUQRSHLR
  9988  	{
  9989  		// ZUQRSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
  9990  		{
  9991  			goOp:      AZUQRSHLR,
  9992  			fixedBits: 0x440f8000,
  9993  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
  9994  		},
  9995  	},
  9996  	// ZUQRSHRN
  9997  	{
  9998  		// ZUQRSHRN #<const>, { <Zn1>.H-<Zn2>.H }, <Zd>.B
  9999  		{
 10000  			goOp:      AZUQRSHRN,
 10001  			fixedBits: 0x45a83800,
 10002  			args:      cconst___Zn1_H_Zn2_H___Zd_B,
 10003  		},
 10004  		// ZUQRSHRN #<const>, { <Zn1>.S-<Zn2>.S }, <Zd>.H
 10005  		{
 10006  			goOp:      AZUQRSHRN,
 10007  			fixedBits: 0x45b03800,
 10008  			args:      cconst___Zn1_S_Zn2_S___Zd_H,
 10009  		},
 10010  	},
 10011  	// ZUQRSHRNB
 10012  	{
 10013  		// ZUQRSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T>
 10014  		{
 10015  			goOp:      AZUQRSHRNB,
 10016  			fixedBits: 0x45203800,
 10017  			args:      cconst__Zn_Tb__Zd_T__1,
 10018  		},
 10019  	},
 10020  	// ZUQRSHRNT
 10021  	{
 10022  		// ZUQRSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T>
 10023  		{
 10024  			goOp:      AZUQRSHRNT,
 10025  			fixedBits: 0x45203c00,
 10026  			args:      cconst__Zn_Tb__Zd_T__1,
 10027  		},
 10028  	},
 10029  	// ZUQSHL
 10030  	{
 10031  		// ZUQSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10032  		{
 10033  			goOp:      AZUQSHL,
 10034  			fixedBits: 0x44098000,
 10035  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10036  		},
 10037  		// ZUQSHL #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10038  		{
 10039  			goOp:      AZUQSHL,
 10040  			fixedBits: 0x4078000,
 10041  			args:      cconst__Zdn_T__PgM__Zdn_T__2,
 10042  		},
 10043  	},
 10044  	// ZUQSHLR
 10045  	{
 10046  		// ZUQSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10047  		{
 10048  			goOp:      AZUQSHLR,
 10049  			fixedBits: 0x440d8000,
 10050  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10051  		},
 10052  	},
 10053  	// ZUQSHRN
 10054  	{
 10055  		// ZUQSHRN #<const>, { <Zn1>.<Tb>-<Zn2>.<Tb> }, <Zd>.<T>
 10056  		{
 10057  			goOp:      AZUQSHRN,
 10058  			fixedBits: 0x45a01000,
 10059  			args:      cconst___Zn1_Tb_Zn2_Tb___Zd_T,
 10060  		},
 10061  	},
 10062  	// ZUQSHRNB
 10063  	{
 10064  		// ZUQSHRNB #<const>, <Zn>.<Tb>, <Zd>.<T>
 10065  		{
 10066  			goOp:      AZUQSHRNB,
 10067  			fixedBits: 0x45203000,
 10068  			args:      cconst__Zn_Tb__Zd_T__1,
 10069  		},
 10070  	},
 10071  	// ZUQSHRNT
 10072  	{
 10073  		// ZUQSHRNT #<const>, <Zn>.<Tb>, <Zd>.<T>
 10074  		{
 10075  			goOp:      AZUQSHRNT,
 10076  			fixedBits: 0x45203400,
 10077  			args:      cconst__Zn_Tb__Zd_T__1,
 10078  		},
 10079  	},
 10080  	// ZUQSUB
 10081  	{
 10082  		// ZUQSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10083  		{
 10084  			goOp:      AZUQSUB,
 10085  			fixedBits: 0x441b8000,
 10086  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10087  		},
 10088  		// ZUQSUB <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10089  		{
 10090  			goOp:      AZUQSUB,
 10091  			fixedBits: 0x4201c00,
 10092  			args:      Zm_T__Zn_T__Zd_T__1,
 10093  		},
 10094  		// ZUQSUB #<imm>{, <shift>}, <Zdn>.<T>, <Zdn>.<T>
 10095  		{
 10096  			goOp:      AZUQSUB,
 10097  			fixedBits: 0x2527c000,
 10098  			args:      cimm__shift__Zdn_T__Zdn_T,
 10099  		},
 10100  	},
 10101  	// ZUQSUBR
 10102  	{
 10103  		// ZUQSUBR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10104  		{
 10105  			goOp:      AZUQSUBR,
 10106  			fixedBits: 0x441f8000,
 10107  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10108  		},
 10109  	},
 10110  	// ZUQXTNB
 10111  	{
 10112  		// ZUQXTNB <Zn>.<Tb>, <Zd>.<T>
 10113  		{
 10114  			goOp:      AZUQXTNB,
 10115  			fixedBits: 0x45204800,
 10116  			args:      Zn_Tb__Zd_T__2,
 10117  		},
 10118  	},
 10119  	// ZUQXTNT
 10120  	{
 10121  		// ZUQXTNT <Zn>.<Tb>, <Zd>.<T>
 10122  		{
 10123  			goOp:      AZUQXTNT,
 10124  			fixedBits: 0x45204c00,
 10125  			args:      Zn_Tb__Zd_T__2,
 10126  		},
 10127  	},
 10128  	// ZURECPE
 10129  	{
 10130  		// ZURECPE <Zn>.S, <Pg>/M, <Zd>.S
 10131  		{
 10132  			goOp:      AZURECPE,
 10133  			fixedBits: 0x4480a000,
 10134  			args:      Zn_S__PgM__Zd_S,
 10135  		},
 10136  		// ZURECPE <Zn>.S, <Pg>/Z, <Zd>.S
 10137  		{
 10138  			goOp:      AZURECPE,
 10139  			fixedBits: 0x4482a000,
 10140  			args:      Zn_S__PgZ__Zd_S,
 10141  		},
 10142  	},
 10143  	// ZURHADD
 10144  	{
 10145  		// ZURHADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10146  		{
 10147  			goOp:      AZURHADD,
 10148  			fixedBits: 0x44158000,
 10149  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10150  		},
 10151  	},
 10152  	// ZURSHL
 10153  	{
 10154  		// ZURSHL <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10155  		{
 10156  			goOp:      AZURSHL,
 10157  			fixedBits: 0x44038000,
 10158  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10159  		},
 10160  	},
 10161  	// ZURSHLR
 10162  	{
 10163  		// ZURSHLR <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10164  		{
 10165  			goOp:      AZURSHLR,
 10166  			fixedBits: 0x44078000,
 10167  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10168  		},
 10169  	},
 10170  	// ZURSHR
 10171  	{
 10172  		// ZURSHR #<const>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10173  		{
 10174  			goOp:      AZURSHR,
 10175  			fixedBits: 0x40d8000,
 10176  			args:      cconst__Zdn_T__PgM__Zdn_T__1,
 10177  		},
 10178  	},
 10179  	// ZURSQRTE
 10180  	{
 10181  		// ZURSQRTE <Zn>.S, <Pg>/M, <Zd>.S
 10182  		{
 10183  			goOp:      AZURSQRTE,
 10184  			fixedBits: 0x4481a000,
 10185  			args:      Zn_S__PgM__Zd_S,
 10186  		},
 10187  		// ZURSQRTE <Zn>.S, <Pg>/Z, <Zd>.S
 10188  		{
 10189  			goOp:      AZURSQRTE,
 10190  			fixedBits: 0x4483a000,
 10191  			args:      Zn_S__PgZ__Zd_S,
 10192  		},
 10193  	},
 10194  	// ZURSRA
 10195  	{
 10196  		// ZURSRA #<const>, <Zn>.<T>, <Zda>.<T>
 10197  		{
 10198  			goOp:      AZURSRA,
 10199  			fixedBits: 0x4500ec00,
 10200  			args:      cconst__Zn_T__Zda_T,
 10201  		},
 10202  	},
 10203  	// ZUSDOT
 10204  	{
 10205  		// ZUSDOT <Zm>.B, <Zn>.B, <Zda>.S
 10206  		{
 10207  			goOp:      AZUSDOT,
 10208  			fixedBits: 0x44807800,
 10209  			args:      Zm_B__Zn_B__Zda_S,
 10210  		},
 10211  		// ZUSDOT <Zm>.B[<imm>], <Zn>.B, <Zda>.S
 10212  		{
 10213  			goOp:      AZUSDOT,
 10214  			fixedBits: 0x44a01800,
 10215  			args:      Zm_B_imm___Zn_B__Zda_S__2,
 10216  		},
 10217  	},
 10218  	// ZUSHLLB
 10219  	{
 10220  		// ZUSHLLB #<const>, <Zn>.<Tb>, <Zd>.<T>
 10221  		{
 10222  			goOp:      AZUSHLLB,
 10223  			fixedBits: 0x4500a800,
 10224  			args:      cconst__Zn_Tb__Zd_T__2,
 10225  		},
 10226  	},
 10227  	// ZUSHLLT
 10228  	{
 10229  		// ZUSHLLT #<const>, <Zn>.<Tb>, <Zd>.<T>
 10230  		{
 10231  			goOp:      AZUSHLLT,
 10232  			fixedBits: 0x4500ac00,
 10233  			args:      cconst__Zn_Tb__Zd_T__2,
 10234  		},
 10235  	},
 10236  	// ZUSMMLA
 10237  	{
 10238  		// ZUSMMLA <Zm>.B, <Zn>.B, <Zda>.S
 10239  		{
 10240  			goOp:      AZUSMMLA,
 10241  			fixedBits: 0x45809800,
 10242  			args:      Zm_B__Zn_B__Zda_S,
 10243  		},
 10244  	},
 10245  	// ZUSQADD
 10246  	{
 10247  		// ZUSQADD <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
 10248  		{
 10249  			goOp:      AZUSQADD,
 10250  			fixedBits: 0x441d8000,
 10251  			args:      Zm_T__Zdn_T__PgM__Zdn_T__1,
 10252  		},
 10253  	},
 10254  	// ZUSRA
 10255  	{
 10256  		// ZUSRA #<const>, <Zn>.<T>, <Zda>.<T>
 10257  		{
 10258  			goOp:      AZUSRA,
 10259  			fixedBits: 0x4500e400,
 10260  			args:      cconst__Zn_T__Zda_T,
 10261  		},
 10262  	},
 10263  	// ZUSUBLB
 10264  	{
 10265  		// ZUSUBLB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
 10266  		{
 10267  			goOp:      AZUSUBLB,
 10268  			fixedBits: 0x45001800,
 10269  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
 10270  		},
 10271  	},
 10272  	// ZUSUBLT
 10273  	{
 10274  		// ZUSUBLT <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
 10275  		{
 10276  			goOp:      AZUSUBLT,
 10277  			fixedBits: 0x45001c00,
 10278  			args:      Zm_Tb__Zn_Tb__Zd_T__1,
 10279  		},
 10280  	},
 10281  	// ZUSUBWB
 10282  	{
 10283  		// ZUSUBWB <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
 10284  		{
 10285  			goOp:      AZUSUBWB,
 10286  			fixedBits: 0x45005800,
 10287  			args:      Zm_Tb__Zn_T__Zd_T,
 10288  		},
 10289  	},
 10290  	// ZUSUBWT
 10291  	{
 10292  		// ZUSUBWT <Zm>.<Tb>, <Zn>.<T>, <Zd>.<T>
 10293  		{
 10294  			goOp:      AZUSUBWT,
 10295  			fixedBits: 0x45005c00,
 10296  			args:      Zm_Tb__Zn_T__Zd_T,
 10297  		},
 10298  	},
 10299  	// ZUUNPKHI
 10300  	{
 10301  		// ZUUNPKHI <Zn>.<Tb>, <Zd>.<T>
 10302  		{
 10303  			goOp:      AZUUNPKHI,
 10304  			fixedBits: 0x5333800,
 10305  			args:      Zn_Tb__Zd_T__1,
 10306  		},
 10307  	},
 10308  	// ZUUNPKLO
 10309  	{
 10310  		// ZUUNPKLO <Zn>.<Tb>, <Zd>.<T>
 10311  		{
 10312  			goOp:      AZUUNPKLO,
 10313  			fixedBits: 0x5323800,
 10314  			args:      Zn_Tb__Zd_T__1,
 10315  		},
 10316  	},
 10317  	// ZUXTB
 10318  	{
 10319  		// ZUXTB <Zn>.<T>, <Pg>/M, <Zd>.<T>
 10320  		{
 10321  			goOp:      AZUXTB,
 10322  			fixedBits: 0x411a000,
 10323  			args:      Zn_T__PgM__Zd_T__4,
 10324  		},
 10325  		// ZUXTB <Zn>.<T>, <Pg>/Z, <Zd>.<T>
 10326  		{
 10327  			goOp:      AZUXTB,
 10328  			fixedBits: 0x401a000,
 10329  			args:      Zn_T__PgZ__Zd_T__4,
 10330  		},
 10331  	},
 10332  	// ZUXTH
 10333  	{
 10334  		// ZUXTH <Zn>.<T>, <Pg>/M, <Zd>.<T>
 10335  		{
 10336  			goOp:      AZUXTH,
 10337  			fixedBits: 0x493a000,
 10338  			args:      Zn_T__PgM__Zd_T__5,
 10339  		},
 10340  		// ZUXTH <Zn>.<T>, <Pg>/Z, <Zd>.<T>
 10341  		{
 10342  			goOp:      AZUXTH,
 10343  			fixedBits: 0x483a000,
 10344  			args:      Zn_T__PgZ__Zd_T__5,
 10345  		},
 10346  	},
 10347  	// ZUXTW
 10348  	{
 10349  		// ZUXTW <Zn>.D, <Pg>/M, <Zd>.D
 10350  		{
 10351  			goOp:      AZUXTW,
 10352  			fixedBits: 0x4d5a000,
 10353  			args:      Zn_D__PgM__Zd_D,
 10354  		},
 10355  		// ZUXTW <Zn>.D, <Pg>/Z, <Zd>.D
 10356  		{
 10357  			goOp:      AZUXTW,
 10358  			fixedBits: 0x4c5a000,
 10359  			args:      Zn_D__PgZ__Zd_D,
 10360  		},
 10361  	},
 10362  	// ZUZP1
 10363  	{
 10364  		// ZUZP1 <Zm>.Q, <Zn>.Q, <Zd>.Q
 10365  		{
 10366  			goOp:      AZUZP1,
 10367  			fixedBits: 0x5a00800,
 10368  			args:      Zm_Q__Zn_Q__Zd_Q,
 10369  		},
 10370  		// ZUZP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10371  		{
 10372  			goOp:      AZUZP1,
 10373  			fixedBits: 0x5206800,
 10374  			args:      Zm_T__Zn_T__Zd_T__1,
 10375  		},
 10376  	},
 10377  	// ZUZP2
 10378  	{
 10379  		// ZUZP2 <Zm>.Q, <Zn>.Q, <Zd>.Q
 10380  		{
 10381  			goOp:      AZUZP2,
 10382  			fixedBits: 0x5a00c00,
 10383  			args:      Zm_Q__Zn_Q__Zd_Q,
 10384  		},
 10385  		// ZUZP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10386  		{
 10387  			goOp:      AZUZP2,
 10388  			fixedBits: 0x5206c00,
 10389  			args:      Zm_T__Zn_T__Zd_T__1,
 10390  		},
 10391  	},
 10392  	// ZUZPQ1
 10393  	{
 10394  		// ZUZPQ1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10395  		{
 10396  			goOp:      AZUZPQ1,
 10397  			fixedBits: 0x4400e800,
 10398  			args:      Zm_T__Zn_T__Zd_T__1,
 10399  		},
 10400  	},
 10401  	// ZUZPQ2
 10402  	{
 10403  		// ZUZPQ2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10404  		{
 10405  			goOp:      AZUZPQ2,
 10406  			fixedBits: 0x4400ec00,
 10407  			args:      Zm_T__Zn_T__Zd_T__1,
 10408  		},
 10409  	},
 10410  	// ZXAR
 10411  	{
 10412  		// ZXAR #<const>, <Zm>.<T>, <Zdn>.<T>, <Zdn>.<T>
 10413  		{
 10414  			goOp:      AZXAR,
 10415  			fixedBits: 0x4203400,
 10416  			args:      cconst__Zm_T__Zdn_T__Zdn_T,
 10417  		},
 10418  	},
 10419  	// ZZIP1
 10420  	{
 10421  		// ZZIP1 <Zm>.Q, <Zn>.Q, <Zd>.Q
 10422  		{
 10423  			goOp:      AZZIP1,
 10424  			fixedBits: 0x5a00000,
 10425  			args:      Zm_Q__Zn_Q__Zd_Q,
 10426  		},
 10427  		// ZZIP1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10428  		{
 10429  			goOp:      AZZIP1,
 10430  			fixedBits: 0x5206000,
 10431  			args:      Zm_T__Zn_T__Zd_T__1,
 10432  		},
 10433  	},
 10434  	// ZZIP2
 10435  	{
 10436  		// ZZIP2 <Zm>.Q, <Zn>.Q, <Zd>.Q
 10437  		{
 10438  			goOp:      AZZIP2,
 10439  			fixedBits: 0x5a00400,
 10440  			args:      Zm_Q__Zn_Q__Zd_Q,
 10441  		},
 10442  		// ZZIP2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10443  		{
 10444  			goOp:      AZZIP2,
 10445  			fixedBits: 0x5206400,
 10446  			args:      Zm_T__Zn_T__Zd_T__1,
 10447  		},
 10448  	},
 10449  	// ZZIPQ1
 10450  	{
 10451  		// ZZIPQ1 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10452  		{
 10453  			goOp:      AZZIPQ1,
 10454  			fixedBits: 0x4400e000,
 10455  			args:      Zm_T__Zn_T__Zd_T__1,
 10456  		},
 10457  	},
 10458  	// ZZIPQ2
 10459  	{
 10460  		// ZZIPQ2 <Zm>.<T>, <Zn>.<T>, <Zd>.<T>
 10461  		{
 10462  			goOp:      AZZIPQ2,
 10463  			fixedBits: 0x4400e400,
 10464  			args:      Zm_T__Zn_T__Zd_T__1,
 10465  		},
 10466  	},
 10467  }
 10468  
 10469  var a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit = operand{
 10470  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10471  		{encodeZm1619_16Bit32Bit, enc_Zm},
 10472  		{encodeArngHCheck, enc_NIL},
 10473  		{encodeI3hI3l_1923_16Bit, enc_i3h_i3l},
 10474  	},
 10475  }
 10476  
 10477  var a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit = operand{
 10478  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10479  		{encodeZm1619_16Bit32Bit, enc_Zm},
 10480  		{encodeArngSCheck, enc_NIL},
 10481  		{encodeI2_1921_32Bit, enc_i2},
 10482  	},
 10483  }
 10484  
 10485  var a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit = operand{
 10486  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10487  		{encodeZm1619_32Bit, enc_Zm},
 10488  		{encodeArngHCheck, enc_NIL},
 10489  		{encodeI3hI3l_1119_32Bit, enc_i3h_i3l},
 10490  	},
 10491  }
 10492  
 10493  var a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit = operand{
 10494  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10495  		{encodeZm1619_8To32Bit, enc_Zm},
 10496  		{encodeArngBCheck, enc_NIL},
 10497  		{encodeI2_1921_8To32Bit, enc_i2},
 10498  	},
 10499  }
 10500  
 10501  var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision = operand{
 10502  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10503  		{encodeZm1619_HalfSinglePrecision, enc_Zm},
 10504  		{encodeArngHCheck, enc_NIL},
 10505  		{encodeI3hI3l_1923_HalfPrecision, enc_i3h_i3l},
 10506  	},
 10507  }
 10508  
 10509  var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision = operand{
 10510  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10511  		{encodeZm1619_HalfSinglePrecision, enc_Zm},
 10512  		{encodeArngSCheck, enc_NIL},
 10513  		{encodeI2_1921_SinglePrecision, enc_i2},
 10514  	},
 10515  }
 10516  
 10517  var a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit = operand{
 10518  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10519  		{encodeZm1620_16To64Bit, enc_Zm},
 10520  		{encodeArngHCheck, enc_NIL},
 10521  		{encodeI1_2021_16To64Bit, enc_i1},
 10522  	},
 10523  }
 10524  
 10525  var a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit = operand{
 10526  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10527  		{encodeZm1620_64Bit, enc_Zm},
 10528  		{encodeArngDCheck, enc_NIL},
 10529  		{encodeI1_2021_64Bit, enc_i1},
 10530  	},
 10531  }
 10532  
 10533  var a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit = operand{
 10534  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10535  		{encodeZm1620_64Bit, enc_Zm},
 10536  		{encodeArngSCheck, enc_NIL},
 10537  		{encodeI2hI2l_1120_64Bit, enc_i2h_i2l},
 10538  	},
 10539  }
 10540  
 10541  var a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision = operand{
 10542  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10543  		{encodeZm1620_DoublePrecision, enc_Zm},
 10544  		{encodeArngDCheck, enc_NIL},
 10545  		{encodeI1_2021_DoublePrecision, enc_i1},
 10546  	},
 10547  }
 10548  
 10549  var a_ARNGIDX_Zm510V1_ArngQCheck_I21921 = operand{
 10550  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10551  		{encodeZm510V1, enc_Zm},
 10552  		{encodeArngQCheck, enc_NIL},
 10553  		{encodeI21921, enc_i2},
 10554  	},
 10555  }
 10556  
 10557  var a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half = operand{
 10558  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10559  		{encodeZm_1619_Half, enc_Zm},
 10560  		{encodeArngHCheck, enc_NIL},
 10561  		{encodeI2_1921_Half, enc_i2},
 10562  	},
 10563  }
 10564  
 10565  var a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit = operand{
 10566  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10567  		{encodeZm_1619_Range0_7V1, enc_Zm},
 10568  		{encodeArngHCheck, enc_NIL},
 10569  		{encodeI2_1921_16bit, enc_i2},
 10570  	},
 10571  }
 10572  
 10573  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup = operand{
 10574  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10575  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10576  		{encodeArngBCheck, enc_NIL},
 10577  		{encodeI2_1921_8BitGroup, enc_i2},
 10578  	},
 10579  }
 10580  
 10581  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit = operand{
 10582  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10583  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10584  		{encodeArngBCheck, enc_NIL},
 10585  		{encodeI3hI3l_1119_Pair8Bit, enc_i3h_i3l},
 10586  	},
 10587  }
 10588  
 10589  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit = operand{
 10590  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10591  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10592  		{encodeArngBCheck, enc_NIL},
 10593  		{encodeI3hI3l_1923_8To16Bit, enc_i3h_i3l},
 10594  	},
 10595  }
 10596  
 10597  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019 = operand{
 10598  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10599  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10600  		{encodeArngBCheck, enc_NIL},
 10601  		{encodeI4hI4l_1019, enc_i4h_i4l},
 10602  	},
 10603  }
 10604  
 10605  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit = operand{
 10606  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10607  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10608  		{encodeArngHCheck, enc_NIL},
 10609  		{encodeI2_1921_16To32Bit, enc_i2},
 10610  	},
 10611  }
 10612  
 10613  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit = operand{
 10614  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10615  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10616  		{encodeArngHCheck, enc_NIL},
 10617  		{encodeI2_1921_Pair16Bit, enc_i2},
 10618  	},
 10619  }
 10620  
 10621  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119 = operand{
 10622  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10623  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10624  		{encodeArngHCheck, enc_NIL},
 10625  		{encodeI3hI3l_1119, enc_i3h_i3l},
 10626  	},
 10627  }
 10628  
 10629  var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922 = operand{
 10630  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10631  		{encodeZm_1619_Range0_7V2, enc_Zm},
 10632  		{encodeArngHCheck, enc_NIL},
 10633  		{encodeI3hI3l_1922, enc_i3h_i3l},
 10634  	},
 10635  }
 10636  
 10637  var a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit = operand{
 10638  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10639  		{encodeZm_1620_Range0_15, enc_Zm},
 10640  		{encodeArngSCheck, enc_NIL},
 10641  		{encodeI1_2021_32bit, enc_i1},
 10642  	},
 10643  }
 10644  
 10645  var a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single = operand{
 10646  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10647  		{encodeZm_1620_Single, enc_Zm},
 10648  		{encodeArngSCheck, enc_NIL},
 10649  		{encodeI1_2021_Single, enc_i1},
 10650  	},
 10651  }
 10652  
 10653  var a_ARNGIDX_Zn510Src_Tsz_1620_SizeSpecifier4_I1Tsz_Delegate = operand{
 10654  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10655  		{encodeZn510Src, enc_Zn},
 10656  		{encodeTsz_1620_SizeSpecifier4, enc_tsz},
 10657  		{encodeI1Tsz_Delegate, enc_i1_tsz},
 10658  	},
 10659  }
 10660  
 10661  var a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate = operand{
 10662  	class: AC_ARNGIDX, elemEncoders: []elemEncoder{
 10663  		{encodeZn510Src, enc_Zn},
 10664  		{encodeTsz_1621_SizeSpecifier5, enc_tsz},
 10665  		{encodeImm2Tsz_Delegate, enc_imm2_tsz},
 10666  	},
 10667  }
 10668  
 10669  var a_ARNG_PNd_SizeBHSD2224 = operand{
 10670  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10671  		{encodePNd, enc_PNd},
 10672  		{encodeSizeBHSD2224, enc_size},
 10673  	},
 10674  }
 10675  
 10676  var a_ARNG_PNn59_SizeBHSD2224 = operand{
 10677  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10678  		{encodePNn59, enc_PNn},
 10679  		{encodeSizeBHSD2224, enc_size},
 10680  	},
 10681  }
 10682  
 10683  var a_ARNG_Pd_ArngBCheck = operand{
 10684  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10685  		{encodePd, enc_Pd},
 10686  		{encodeArngBCheck, enc_NIL},
 10687  	},
 10688  }
 10689  
 10690  var a_ARNG_Pd_ArngDCheck = operand{
 10691  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10692  		{encodePd, enc_Pd},
 10693  		{encodeArngDCheck, enc_NIL},
 10694  	},
 10695  }
 10696  
 10697  var a_ARNG_Pd_ArngHCheck = operand{
 10698  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10699  		{encodePd, enc_Pd},
 10700  		{encodeArngHCheck, enc_NIL},
 10701  	},
 10702  }
 10703  
 10704  var a_ARNG_Pd_ArngSCheck = operand{
 10705  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10706  		{encodePd, enc_Pd},
 10707  		{encodeArngSCheck, enc_NIL},
 10708  	},
 10709  }
 10710  
 10711  var a_ARNG_Pd_Size0BH2223 = operand{
 10712  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10713  		{encodePd, enc_Pd},
 10714  		{encodeSize0BH2223, enc_size0},
 10715  	},
 10716  }
 10717  
 10718  var a_ARNG_Pd_SizeBHS2224 = operand{
 10719  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10720  		{encodePd, enc_Pd},
 10721  		{encodeSizeBHS2224, enc_size},
 10722  	},
 10723  }
 10724  
 10725  var a_ARNG_Pd_SizeBHSD2224 = operand{
 10726  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10727  		{encodePd, enc_Pd},
 10728  		{encodeSizeBHSD2224, enc_size},
 10729  	},
 10730  }
 10731  
 10732  var a_ARNG_Pd_SizeHSD2224 = operand{
 10733  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10734  		{encodePd, enc_Pd},
 10735  		{encodeSizeHSD2224, enc_size},
 10736  	},
 10737  }
 10738  
 10739  var a_ARNG_PdmDest_ArngBCheck = operand{
 10740  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10741  		{encodePdmDest, enc_Pdm},
 10742  		{encodeArngBCheck, enc_NIL},
 10743  	},
 10744  }
 10745  
 10746  var a_ARNG_PdnDest_SizeBHSD2224 = operand{
 10747  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10748  		{encodePdnDest, enc_Pdn},
 10749  		{encodeSizeBHSD2224, enc_size},
 10750  	},
 10751  }
 10752  
 10753  var a_ARNG_PdnSrcDst_ArngBCheck = operand{
 10754  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10755  		{encodePdnSrcDst, enc_Pdn},
 10756  		{encodeArngBCheck, enc_NIL},
 10757  	},
 10758  }
 10759  
 10760  var a_ARNG_Pm1620_ArngBCheck = operand{
 10761  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10762  		{encodePm1620, enc_Pm},
 10763  		{encodeArngBCheck, enc_NIL},
 10764  	},
 10765  }
 10766  
 10767  var a_ARNG_Pm1620_SizeBHSD2224 = operand{
 10768  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10769  		{encodePm1620, enc_Pm},
 10770  		{encodeSizeBHSD2224, enc_size},
 10771  	},
 10772  }
 10773  
 10774  var a_ARNG_Pm59V1_SizeBHSD2224 = operand{
 10775  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10776  		{encodePm59V1, enc_Pm},
 10777  		{encodeSizeBHSD2224, enc_size},
 10778  	},
 10779  }
 10780  
 10781  var a_ARNG_Pm59V1_SizeHSD2224 = operand{
 10782  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10783  		{encodePm59V1, enc_Pm},
 10784  		{encodeSizeHSD2224, enc_size},
 10785  	},
 10786  }
 10787  
 10788  var a_ARNG_Pn59V2_ArngBCheck = operand{
 10789  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10790  		{encodePn59V2, enc_Pn},
 10791  		{encodeArngBCheck, enc_NIL},
 10792  	},
 10793  }
 10794  
 10795  var a_ARNG_Pn59V2_ArngDCheck = operand{
 10796  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10797  		{encodePn59V2, enc_Pn},
 10798  		{encodeArngDCheck, enc_NIL},
 10799  	},
 10800  }
 10801  
 10802  var a_ARNG_Pn59V2_ArngHCheck = operand{
 10803  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10804  		{encodePn59V2, enc_Pn},
 10805  		{encodeArngHCheck, enc_NIL},
 10806  	},
 10807  }
 10808  
 10809  var a_ARNG_Pn59V2_ArngSCheck = operand{
 10810  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10811  		{encodePn59V2, enc_Pn},
 10812  		{encodeArngSCheck, enc_NIL},
 10813  	},
 10814  }
 10815  
 10816  var a_ARNG_Pn59V2_SizeBHSD2224 = operand{
 10817  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10818  		{encodePn59V2, enc_Pn},
 10819  		{encodeSizeBHSD2224, enc_size},
 10820  	},
 10821  }
 10822  
 10823  var a_ARNG_Pn59_ArngBCheck = operand{
 10824  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10825  		{encodePn59, enc_Pn},
 10826  		{encodeArngBCheck, enc_NIL},
 10827  	},
 10828  }
 10829  
 10830  var a_ARNG_Pn59_SizeBHSD2224 = operand{
 10831  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10832  		{encodePn59, enc_Pn},
 10833  		{encodeSizeBHSD2224, enc_size},
 10834  	},
 10835  }
 10836  
 10837  var a_ARNG_Vd_Size16B8H4S2D = operand{
 10838  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10839  		{encodeVd, enc_Vd},
 10840  		{encodeSize16B8H4S2D, enc_size},
 10841  	},
 10842  }
 10843  
 10844  var a_ARNG_Vd_Size8H4S2D = operand{
 10845  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10846  		{encodeVd, enc_Vd},
 10847  		{encodeSize8H4S2D, enc_size},
 10848  	},
 10849  }
 10850  
 10851  var a_ARNG_Za16213Rd_SizeHSD2224 = operand{
 10852  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10853  		{encodeZa16213Rd, enc_Za},
 10854  		{encodeSizeHSD2224, enc_size},
 10855  	},
 10856  }
 10857  
 10858  var a_ARNG_Za5103Rd_ArngDCheck = operand{
 10859  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10860  		{encodeZa5103Rd, enc_Za},
 10861  		{encodeArngDCheck, enc_NIL},
 10862  	},
 10863  }
 10864  
 10865  var a_ARNG_Za5103Rd_SizeBHSD2224 = operand{
 10866  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10867  		{encodeZa5103Rd, enc_Za},
 10868  		{encodeSizeBHSD2224, enc_size},
 10869  	},
 10870  }
 10871  
 10872  var a_ARNG_Zd_ArngBCheck = operand{
 10873  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10874  		{encodeZd, enc_Zd},
 10875  		{encodeArngBCheck, enc_NIL},
 10876  	},
 10877  }
 10878  
 10879  var a_ARNG_Zd_ArngDCheck = operand{
 10880  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10881  		{encodeZd, enc_Zd},
 10882  		{encodeArngDCheck, enc_NIL},
 10883  	},
 10884  }
 10885  
 10886  var a_ARNG_Zd_ArngHCheck = operand{
 10887  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10888  		{encodeZd, enc_Zd},
 10889  		{encodeArngHCheck, enc_NIL},
 10890  	},
 10891  }
 10892  
 10893  var a_ARNG_Zd_ArngQCheck = operand{
 10894  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10895  		{encodeZd, enc_Zd},
 10896  		{encodeArngQCheck, enc_NIL},
 10897  	},
 10898  }
 10899  
 10900  var a_ARNG_Zd_ArngSCheck = operand{
 10901  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10902  		{encodeZd, enc_Zd},
 10903  		{encodeArngSCheck, enc_NIL},
 10904  	},
 10905  }
 10906  
 10907  var a_ARNG_Zd_Size0HalfwordMergeZero = operand{
 10908  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10909  		{encodeZd, enc_Zd},
 10910  		{encodeSize0HalfwordMergeZero, enc_size0},
 10911  	},
 10912  }
 10913  
 10914  var a_ARNG_Zd_Size0SD2223 = operand{
 10915  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10916  		{encodeZd, enc_Zd},
 10917  		{encodeSize0SD2223, enc_size0},
 10918  	},
 10919  }
 10920  
 10921  var a_ARNG_Zd_SizeBHS2224 = operand{
 10922  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10923  		{encodeZd, enc_Zd},
 10924  		{encodeSizeBHS2224, enc_size},
 10925  	},
 10926  }
 10927  
 10928  var a_ARNG_Zd_SizeBHS2224Offset1 = operand{
 10929  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10930  		{encodeZd, enc_Zd},
 10931  		{encodeSizeBHS2224Offset1, enc_size},
 10932  	},
 10933  }
 10934  
 10935  var a_ARNG_Zd_SizeBHSD2224 = operand{
 10936  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10937  		{encodeZd, enc_Zd},
 10938  		{encodeSizeBHSD2224, enc_size},
 10939  	},
 10940  }
 10941  
 10942  var a_ARNG_Zd_SizeBhsTsz1921 = operand{
 10943  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10944  		{encodeZd, enc_Zd},
 10945  		{encodeSizeBhsTsz1921, enc_tszh_tszl},
 10946  	},
 10947  }
 10948  
 10949  var a_ARNG_Zd_SizeBhsdTsz1921 = operand{
 10950  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10951  		{encodeZd, enc_Zd},
 10952  		{encodeSizeBhsdTsz1921, enc_tszh_tszl},
 10953  	},
 10954  }
 10955  
 10956  var a_ARNG_Zd_SizeByteMergeZero = operand{
 10957  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10958  		{encodeZd, enc_Zd},
 10959  		{encodeSizeByteMergeZero, enc_size},
 10960  	},
 10961  }
 10962  
 10963  var a_ARNG_Zd_SizeHD2224 = operand{
 10964  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10965  		{encodeZd, enc_Zd},
 10966  		{encodeSizeHD2224, enc_size},
 10967  	},
 10968  }
 10969  
 10970  var a_ARNG_Zd_SizeHSD1315 = operand{
 10971  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10972  		{encodeZd, enc_Zd},
 10973  		{encodeSizeHSD1315, enc_size},
 10974  	},
 10975  }
 10976  
 10977  var a_ARNG_Zd_SizeHSD1719 = operand{
 10978  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10979  		{encodeZd, enc_Zd},
 10980  		{encodeSizeHSD1719, enc_size},
 10981  	},
 10982  }
 10983  
 10984  var a_ARNG_Zd_SizeHSD2224 = operand{
 10985  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10986  		{encodeZd, enc_Zd},
 10987  		{encodeSizeHSD2224, enc_size},
 10988  	},
 10989  }
 10990  
 10991  var a_ARNG_Zd_SizeHSD2224No00 = operand{
 10992  	class: AC_ARNG, elemEncoders: []elemEncoder{
 10993  		{encodeZd, enc_Zd},
 10994  		{encodeSizeHSD2224No00, enc_size},
 10995  	},
 10996  }
 10997  
 10998  var a_ARNG_Zd_SizeHsdTsz1921 = operand{
 10999  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11000  		{encodeZd, enc_Zd},
 11001  		{encodeSizeHsdTsz1921, enc_tszh_tszl},
 11002  	},
 11003  }
 11004  
 11005  var a_ARNG_Zd_SizeImm13NoOp = operand{
 11006  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11007  		{encodeZd, enc_Zd},
 11008  		{encodeSizeImm13NoOp, enc_imm13},
 11009  	},
 11010  }
 11011  
 11012  var a_ARNG_Zd_SzByteHalfword = operand{
 11013  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11014  		{encodeZd, enc_Zd},
 11015  		{encodeSzByteHalfword, enc_sz},
 11016  	},
 11017  }
 11018  
 11019  var a_ARNG_Zd_SzSD1415 = operand{
 11020  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11021  		{encodeZd, enc_Zd},
 11022  		{encodeSzSD1415, enc_sz},
 11023  	},
 11024  }
 11025  
 11026  var a_ARNG_Zd_SzSD1718 = operand{
 11027  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11028  		{encodeZd, enc_Zd},
 11029  		{encodeSzSD1718, enc_sz},
 11030  	},
 11031  }
 11032  
 11033  var a_ARNG_Zd_SzSD2223 = operand{
 11034  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11035  		{encodeZd, enc_Zd},
 11036  		{encodeSzSD2223, enc_sz},
 11037  	},
 11038  }
 11039  
 11040  var a_ARNG_Zd_SzWordDoubleword = operand{
 11041  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11042  		{encodeZd, enc_Zd},
 11043  		{encodeSzWordDoubleword, enc_sz},
 11044  	},
 11045  }
 11046  
 11047  var a_ARNG_Zd_Tsize1921V1 = operand{
 11048  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11049  		{encodeZd, enc_Zd},
 11050  		{encodeTsize1921V1, enc_tsize},
 11051  	},
 11052  }
 11053  
 11054  var a_ARNG_Zd_Tsz_1620_SizeSpecifier4 = operand{
 11055  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11056  		{encodeZd, enc_Zd},
 11057  		{encodeTsz_1620_SizeSpecifier4, enc_tsz},
 11058  	},
 11059  }
 11060  
 11061  var a_ARNG_Zd_Tsz_1621_SizeSpecifier5 = operand{
 11062  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11063  		{encodeZd, enc_Zd},
 11064  		{encodeTsz_1621_SizeSpecifier5, enc_tsz},
 11065  	},
 11066  }
 11067  
 11068  var a_ARNG_Zd_TszhTszlBHS = operand{
 11069  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11070  		{encodeZd, enc_Zd},
 11071  		{encodeTszhTszlBHS, enc_tszh_tszl},
 11072  	},
 11073  }
 11074  
 11075  var a_ARNG_Zda3RdSrcDst_ArngDCheck = operand{
 11076  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11077  		{encodeZda3RdSrcDst, enc_Zda},
 11078  		{encodeArngDCheck, enc_NIL},
 11079  	},
 11080  }
 11081  
 11082  var a_ARNG_Zda3RdSrcDst_ArngHCheck = operand{
 11083  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11084  		{encodeZda3RdSrcDst, enc_Zda},
 11085  		{encodeArngHCheck, enc_NIL},
 11086  	},
 11087  }
 11088  
 11089  var a_ARNG_Zda3RdSrcDst_ArngSCheck = operand{
 11090  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11091  		{encodeZda3RdSrcDst, enc_Zda},
 11092  		{encodeArngSCheck, enc_NIL},
 11093  	},
 11094  }
 11095  
 11096  var a_ARNG_Zda3RdSrcDst_Size0SD2223 = operand{
 11097  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11098  		{encodeZda3RdSrcDst, enc_Zda},
 11099  		{encodeSize0SD2223, enc_size0},
 11100  	},
 11101  }
 11102  
 11103  var a_ARNG_Zda3RdSrcDst_SizeBHSD2224 = operand{
 11104  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11105  		{encodeZda3RdSrcDst, enc_Zda},
 11106  		{encodeSizeBHSD2224, enc_size},
 11107  	},
 11108  }
 11109  
 11110  var a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921 = operand{
 11111  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11112  		{encodeZda3RdSrcDst, enc_Zda},
 11113  		{encodeSizeBhsdTsz1921, enc_tszh_tszl},
 11114  	},
 11115  }
 11116  
 11117  var a_ARNG_Zda3RdSrcDst_SizeHSD2224 = operand{
 11118  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11119  		{encodeZda3RdSrcDst, enc_Zda},
 11120  		{encodeSizeHSD2224, enc_size},
 11121  	},
 11122  }
 11123  
 11124  var a_ARNG_Zda3RdSrcDst_SizeHSD2224No00 = operand{
 11125  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11126  		{encodeZda3RdSrcDst, enc_Zda},
 11127  		{encodeSizeHSD2224No00, enc_size},
 11128  	},
 11129  }
 11130  
 11131  var a_ARNG_Zda3RdSrcDst_SzSD2223 = operand{
 11132  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11133  		{encodeZda3RdSrcDst, enc_Zda},
 11134  		{encodeSzSD2223, enc_sz},
 11135  	},
 11136  }
 11137  
 11138  var a_ARNG_ZdaDest_SizeHSD2224 = operand{
 11139  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11140  		{encodeZdaDest, enc_Zda},
 11141  		{encodeSizeHSD2224, enc_size},
 11142  	},
 11143  }
 11144  
 11145  var a_ARNG_ZdnDest_ArngBCheck = operand{
 11146  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11147  		{encodeZdnDest, enc_Zdn},
 11148  		{encodeArngBCheck, enc_NIL},
 11149  	},
 11150  }
 11151  
 11152  var a_ARNG_ZdnDest_ArngDCheck = operand{
 11153  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11154  		{encodeZdnDest, enc_Zdn},
 11155  		{encodeArngDCheck, enc_NIL},
 11156  	},
 11157  }
 11158  
 11159  var a_ARNG_ZdnDest_ArngHCheck = operand{
 11160  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11161  		{encodeZdnDest, enc_Zdn},
 11162  		{encodeArngHCheck, enc_NIL},
 11163  	},
 11164  }
 11165  
 11166  var a_ARNG_ZdnDest_ArngSCheck = operand{
 11167  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11168  		{encodeZdnDest, enc_Zdn},
 11169  		{encodeArngSCheck, enc_NIL},
 11170  	},
 11171  }
 11172  
 11173  var a_ARNG_ZdnDest_Size0SD2223 = operand{
 11174  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11175  		{encodeZdnDest, enc_Zdn},
 11176  		{encodeSize0SD2223, enc_size0},
 11177  	},
 11178  }
 11179  
 11180  var a_ARNG_ZdnDest_SizeBHS2224 = operand{
 11181  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11182  		{encodeZdnDest, enc_Zdn},
 11183  		{encodeSizeBHS2224, enc_size},
 11184  	},
 11185  }
 11186  
 11187  var a_ARNG_ZdnDest_SizeBHSD2224 = operand{
 11188  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11189  		{encodeZdnDest, enc_Zdn},
 11190  		{encodeSizeBHSD2224, enc_size},
 11191  	},
 11192  }
 11193  
 11194  var a_ARNG_ZdnDest_SizeBhsdTsz1921 = operand{
 11195  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11196  		{encodeZdnDest, enc_Zdn},
 11197  		{encodeSizeBhsdTsz1921, enc_tszh_tszl},
 11198  	},
 11199  }
 11200  
 11201  var a_ARNG_ZdnDest_SizeHSD2224 = operand{
 11202  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11203  		{encodeZdnDest, enc_Zdn},
 11204  		{encodeSizeHSD2224, enc_size},
 11205  	},
 11206  }
 11207  
 11208  var a_ARNG_ZdnDest_SizeHSD2224No00 = operand{
 11209  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11210  		{encodeZdnDest, enc_Zdn},
 11211  		{encodeSizeHSD2224No00, enc_size},
 11212  	},
 11213  }
 11214  
 11215  var a_ARNG_ZdnSrcDst_ArngBCheck = operand{
 11216  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11217  		{encodeZdnSrcDst, enc_Zdn},
 11218  		{encodeArngBCheck, enc_NIL},
 11219  	},
 11220  }
 11221  
 11222  var a_ARNG_ZdnSrcDst_SizeBHSD2224 = operand{
 11223  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11224  		{encodeZdnSrcDst, enc_Zdn},
 11225  		{encodeSizeBHSD2224, enc_size},
 11226  	},
 11227  }
 11228  
 11229  var a_ARNG_ZdnSrcDst_SizeBhsdTsz810 = operand{
 11230  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11231  		{encodeZdnSrcDst, enc_Zdn},
 11232  		{encodeSizeBhsdTsz810, enc_tszh_tszl},
 11233  	},
 11234  }
 11235  
 11236  var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{
 11237  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11238  		{encodeZdnSrcDst, enc_Zdn},
 11239  		{encodeSizeHSD2224, enc_size},
 11240  	},
 11241  }
 11242  
 11243  var a_ARNG_ZdnSrcDst_SizeImm13NoOp = operand{
 11244  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11245  		{encodeZdnSrcDst, enc_Zdn},
 11246  		{encodeSizeImm13NoOp, enc_imm13},
 11247  	},
 11248  }
 11249  
 11250  var a_ARNG_Zk5103Rd_ArngDCheck = operand{
 11251  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11252  		{encodeZk5103Rd, enc_Zk},
 11253  		{encodeArngDCheck, enc_NIL},
 11254  	},
 11255  }
 11256  
 11257  var a_ARNG_Zm1621V2_ArngBCheck = operand{
 11258  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11259  		{encodeZm1621V2, enc_Zm},
 11260  		{encodeArngBCheck, enc_NIL},
 11261  	},
 11262  }
 11263  
 11264  var a_ARNG_Zm1621V2_ArngDCheck = operand{
 11265  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11266  		{encodeZm1621V2, enc_Zm},
 11267  		{encodeArngDCheck, enc_NIL},
 11268  	},
 11269  }
 11270  
 11271  var a_ARNG_Zm1621V2_ArngHCheck = operand{
 11272  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11273  		{encodeZm1621V2, enc_Zm},
 11274  		{encodeArngHCheck, enc_NIL},
 11275  	},
 11276  }
 11277  
 11278  var a_ARNG_Zm1621V2_ArngQCheck = operand{
 11279  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11280  		{encodeZm1621V2, enc_Zm},
 11281  		{encodeArngQCheck, enc_NIL},
 11282  	},
 11283  }
 11284  
 11285  var a_ARNG_Zm1621V2_ArngSCheck = operand{
 11286  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11287  		{encodeZm1621V2, enc_Zm},
 11288  		{encodeArngSCheck, enc_NIL},
 11289  	},
 11290  }
 11291  
 11292  var a_ARNG_Zm1621V2_Size0BH2223 = operand{
 11293  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11294  		{encodeZm1621V2, enc_Zm},
 11295  		{encodeSize0BH2223, enc_size0},
 11296  	},
 11297  }
 11298  
 11299  var a_ARNG_Zm1621V2_Size0SD2223 = operand{
 11300  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11301  		{encodeZm1621V2, enc_Zm},
 11302  		{encodeSize0SD2223, enc_size0},
 11303  	},
 11304  }
 11305  
 11306  var a_ARNG_Zm1621V2_Size0TbBH2223 = operand{
 11307  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11308  		{encodeZm1621V2, enc_Zm},
 11309  		{encodeSize0TbBH2223, enc_size0},
 11310  	},
 11311  }
 11312  
 11313  var a_ARNG_Zm1621V2_SizeBHSD2224 = operand{
 11314  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11315  		{encodeZm1621V2, enc_Zm},
 11316  		{encodeSizeBHSD2224, enc_size},
 11317  	},
 11318  }
 11319  
 11320  var a_ARNG_Zm1621V2_SizeHSD2224 = operand{
 11321  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11322  		{encodeZm1621V2, enc_Zm},
 11323  		{encodeSizeHSD2224, enc_size},
 11324  	},
 11325  }
 11326  
 11327  var a_ARNG_Zm1621V2_SizeHSD2224No00 = operand{
 11328  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11329  		{encodeZm1621V2, enc_Zm},
 11330  		{encodeSizeHSD2224No00, enc_size},
 11331  	},
 11332  }
 11333  
 11334  var a_ARNG_Zm1621V2_SizeTbBHS2224 = operand{
 11335  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11336  		{encodeZm1621V2, enc_Zm},
 11337  		{encodeSizeTbBHS2224, enc_size},
 11338  	},
 11339  }
 11340  
 11341  var a_ARNG_Zm1621V2_SizeTbBS2224 = operand{
 11342  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11343  		{encodeZm1621V2, enc_Zm},
 11344  		{encodeSizeTbBS2224, enc_size},
 11345  	},
 11346  }
 11347  
 11348  var a_ARNG_Zm1621V2_SizeTbHSD2224Offset1 = operand{
 11349  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11350  		{encodeZm1621V2, enc_Zm},
 11351  		{encodeSizeTbHSD2224Offset1, enc_size},
 11352  	},
 11353  }
 11354  
 11355  var a_ARNG_Zm1621V2_SzSD2223 = operand{
 11356  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11357  		{encodeZm1621V2, enc_Zm},
 11358  		{encodeSzSD2223, enc_sz},
 11359  	},
 11360  }
 11361  
 11362  var a_ARNG_Zm510V1_ArngBCheck = operand{
 11363  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11364  		{encodeZm510V1, enc_Zm},
 11365  		{encodeArngBCheck, enc_NIL},
 11366  	},
 11367  }
 11368  
 11369  var a_ARNG_Zm510V1_ArngDCheck = operand{
 11370  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11371  		{encodeZm510V1, enc_Zm},
 11372  		{encodeArngDCheck, enc_NIL},
 11373  	},
 11374  }
 11375  
 11376  var a_ARNG_Zm510V1_ArngHCheck = operand{
 11377  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11378  		{encodeZm510V1, enc_Zm},
 11379  		{encodeArngHCheck, enc_NIL},
 11380  	},
 11381  }
 11382  
 11383  var a_ARNG_Zm510V1_ArngSCheck = operand{
 11384  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11385  		{encodeZm510V1, enc_Zm},
 11386  		{encodeArngSCheck, enc_NIL},
 11387  	},
 11388  }
 11389  
 11390  var a_ARNG_Zm510V1_Size0SD2223 = operand{
 11391  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11392  		{encodeZm510V1, enc_Zm},
 11393  		{encodeSize0SD2223, enc_size0},
 11394  	},
 11395  }
 11396  
 11397  var a_ARNG_Zm510V1_SizeBHSD2224 = operand{
 11398  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11399  		{encodeZm510V1, enc_Zm},
 11400  		{encodeSizeBHSD2224, enc_size},
 11401  	},
 11402  }
 11403  
 11404  var a_ARNG_Zm510V1_SizeBhsdTsz1921 = operand{
 11405  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11406  		{encodeZm510V1, enc_Zm},
 11407  		{encodeSizeBhsdTsz1921, enc_tszh_tszl},
 11408  	},
 11409  }
 11410  
 11411  var a_ARNG_Zm510V1_SizeHSD2224 = operand{
 11412  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11413  		{encodeZm510V1, enc_Zm},
 11414  		{encodeSizeHSD2224, enc_size},
 11415  	},
 11416  }
 11417  
 11418  var a_ARNG_Zm510V1_SizeHSD2224No00 = operand{
 11419  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11420  		{encodeZm510V1, enc_Zm},
 11421  		{encodeSizeHSD2224No00, enc_size},
 11422  	},
 11423  }
 11424  
 11425  var a_ARNG_Zm510V2_SizeBHSD2224 = operand{
 11426  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11427  		{encodeZm510V2, enc_Zm},
 11428  		{encodeSizeBHSD2224, enc_size},
 11429  	},
 11430  }
 11431  
 11432  var a_ARNG_Zm510V2_SizeHSD2224 = operand{
 11433  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11434  		{encodeZm510V2, enc_Zm},
 11435  		{encodeSizeHSD2224, enc_size},
 11436  	},
 11437  }
 11438  
 11439  var a_ARNG_Zn510Src_ArngBCheck = operand{
 11440  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11441  		{encodeZn510Src, enc_Zn},
 11442  		{encodeArngBCheck, enc_NIL},
 11443  	},
 11444  }
 11445  
 11446  var a_ARNG_Zn510Src_ArngDCheck = operand{
 11447  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11448  		{encodeZn510Src, enc_Zn},
 11449  		{encodeArngDCheck, enc_NIL},
 11450  	},
 11451  }
 11452  
 11453  var a_ARNG_Zn510Src_ArngHCheck = operand{
 11454  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11455  		{encodeZn510Src, enc_Zn},
 11456  		{encodeArngHCheck, enc_NIL},
 11457  	},
 11458  }
 11459  
 11460  var a_ARNG_Zn510Src_ArngQCheck = operand{
 11461  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11462  		{encodeZn510Src, enc_Zn},
 11463  		{encodeArngQCheck, enc_NIL},
 11464  	},
 11465  }
 11466  
 11467  var a_ARNG_Zn510Src_ArngSCheck = operand{
 11468  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11469  		{encodeZn510Src, enc_Zn},
 11470  		{encodeArngSCheck, enc_NIL},
 11471  	},
 11472  }
 11473  
 11474  var a_ARNG_Zn510Src_Size0HalfwordMergeZero = operand{
 11475  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11476  		{encodeZn510Src, enc_Zn},
 11477  		{encodeSize0HalfwordMergeZero, enc_size0},
 11478  	},
 11479  }
 11480  
 11481  var a_ARNG_Zn510Src_SizeBHS2224 = operand{
 11482  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11483  		{encodeZn510Src, enc_Zn},
 11484  		{encodeSizeBHS2224, enc_size},
 11485  	},
 11486  }
 11487  
 11488  var a_ARNG_Zn510Src_SizeBHSD2224 = operand{
 11489  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11490  		{encodeZn510Src, enc_Zn},
 11491  		{encodeSizeBHSD2224, enc_size},
 11492  	},
 11493  }
 11494  
 11495  var a_ARNG_Zn510Src_SizeBhsTsz1921Unique = operand{
 11496  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11497  		{encodeZn510Src, enc_Zn},
 11498  		{encodeSizeBhsTsz1921Unique, enc_tszh_tszl},
 11499  	},
 11500  }
 11501  
 11502  var a_ARNG_Zn510Src_SizeBhsdTsz1921 = operand{
 11503  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11504  		{encodeZn510Src, enc_Zn},
 11505  		{encodeSizeBhsdTsz1921, enc_tszh_tszl},
 11506  	},
 11507  }
 11508  
 11509  var a_ARNG_Zn510Src_SizeByteMergeZero = operand{
 11510  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11511  		{encodeZn510Src, enc_Zn},
 11512  		{encodeSizeByteMergeZero, enc_size},
 11513  	},
 11514  }
 11515  
 11516  var a_ARNG_Zn510Src_SizeHSD1315 = operand{
 11517  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11518  		{encodeZn510Src, enc_Zn},
 11519  		{encodeSizeHSD1315, enc_size},
 11520  	},
 11521  }
 11522  
 11523  var a_ARNG_Zn510Src_SizeHSD1719 = operand{
 11524  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11525  		{encodeZn510Src, enc_Zn},
 11526  		{encodeSizeHSD1719, enc_size},
 11527  	},
 11528  }
 11529  
 11530  var a_ARNG_Zn510Src_SizeHSD2224 = operand{
 11531  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11532  		{encodeZn510Src, enc_Zn},
 11533  		{encodeSizeHSD2224, enc_size},
 11534  	},
 11535  }
 11536  
 11537  var a_ARNG_Zn510Src_SizeHsdTsz1921Unique = operand{
 11538  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11539  		{encodeZn510Src, enc_Zn},
 11540  		{encodeSizeHsdTsz1921Unique, enc_tszh_tszl},
 11541  	},
 11542  }
 11543  
 11544  var a_ARNG_Zn510Src_SizeTbBHS2224 = operand{
 11545  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11546  		{encodeZn510Src, enc_Zn},
 11547  		{encodeSizeTbBHS2224, enc_size},
 11548  	},
 11549  }
 11550  
 11551  var a_ARNG_Zn510Src_SizeTbBHSD2224 = operand{
 11552  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11553  		{encodeZn510Src, enc_Zn},
 11554  		{encodeSizeTbBHSD2224, enc_size},
 11555  	},
 11556  }
 11557  
 11558  var a_ARNG_Zn510Src_SizeTbHSD2224Offset1 = operand{
 11559  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11560  		{encodeZn510Src, enc_Zn},
 11561  		{encodeSizeTbHSD2224Offset1, enc_size},
 11562  	},
 11563  }
 11564  
 11565  var a_ARNG_Zn510Src_SzByteHalfword = operand{
 11566  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11567  		{encodeZn510Src, enc_Zn},
 11568  		{encodeSzByteHalfword, enc_sz},
 11569  	},
 11570  }
 11571  
 11572  var a_ARNG_Zn510Src_SzSD1415 = operand{
 11573  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11574  		{encodeZn510Src, enc_Zn},
 11575  		{encodeSzSD1415, enc_sz},
 11576  	},
 11577  }
 11578  
 11579  var a_ARNG_Zn510Src_SzSD1718 = operand{
 11580  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11581  		{encodeZn510Src, enc_Zn},
 11582  		{encodeSzSD1718, enc_sz},
 11583  	},
 11584  }
 11585  
 11586  var a_ARNG_Zn510Src_SzWordDoubleword = operand{
 11587  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11588  		{encodeZn510Src, enc_Zn},
 11589  		{encodeSzWordDoubleword, enc_sz},
 11590  	},
 11591  }
 11592  
 11593  var a_ARNG_Zn510Src_TszhTszlTbHSD = operand{
 11594  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11595  		{encodeZn510Src, enc_Zn},
 11596  		{encodeTszhTszlTbHSD, enc_tszh_tszl},
 11597  	},
 11598  }
 11599  
 11600  var a_ARNG_Zn510V1_ArngBCheck = operand{
 11601  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11602  		{encodeZn510V1, enc_Zn},
 11603  		{encodeArngBCheck, enc_NIL},
 11604  	},
 11605  }
 11606  
 11607  var a_ARNG_Zn510V1_ArngDCheck = operand{
 11608  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11609  		{encodeZn510V1, enc_Zn},
 11610  		{encodeArngDCheck, enc_NIL},
 11611  	},
 11612  }
 11613  
 11614  var a_ARNG_Zn510V1_ArngHCheck = operand{
 11615  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11616  		{encodeZn510V1, enc_Zn},
 11617  		{encodeArngHCheck, enc_NIL},
 11618  	},
 11619  }
 11620  
 11621  var a_ARNG_Zn510V1_ArngQCheck = operand{
 11622  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11623  		{encodeZn510V1, enc_Zn},
 11624  		{encodeArngQCheck, enc_NIL},
 11625  	},
 11626  }
 11627  
 11628  var a_ARNG_Zn510V1_ArngSCheck = operand{
 11629  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11630  		{encodeZn510V1, enc_Zn},
 11631  		{encodeArngSCheck, enc_NIL},
 11632  	},
 11633  }
 11634  
 11635  var a_ARNG_Zn510V1_Size0BH2223 = operand{
 11636  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11637  		{encodeZn510V1, enc_Zn},
 11638  		{encodeSize0BH2223, enc_size0},
 11639  	},
 11640  }
 11641  
 11642  var a_ARNG_Zn510V1_Size0SD2223 = operand{
 11643  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11644  		{encodeZn510V1, enc_Zn},
 11645  		{encodeSize0SD2223, enc_size0},
 11646  	},
 11647  }
 11648  
 11649  var a_ARNG_Zn510V1_Size0TbBH2223 = operand{
 11650  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11651  		{encodeZn510V1, enc_Zn},
 11652  		{encodeSize0TbBH2223, enc_size0},
 11653  	},
 11654  }
 11655  
 11656  var a_ARNG_Zn510V1_SizeBHS2224 = operand{
 11657  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11658  		{encodeZn510V1, enc_Zn},
 11659  		{encodeSizeBHS2224, enc_size},
 11660  	},
 11661  }
 11662  
 11663  var a_ARNG_Zn510V1_SizeBHSD2224 = operand{
 11664  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11665  		{encodeZn510V1, enc_Zn},
 11666  		{encodeSizeBHSD2224, enc_size},
 11667  	},
 11668  }
 11669  
 11670  var a_ARNG_Zn510V1_SizeBhsdTsz1921 = operand{
 11671  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11672  		{encodeZn510V1, enc_Zn},
 11673  		{encodeSizeBhsdTsz1921, enc_tszh_tszl},
 11674  	},
 11675  }
 11676  
 11677  var a_ARNG_Zn510V1_SizeHSD2224 = operand{
 11678  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11679  		{encodeZn510V1, enc_Zn},
 11680  		{encodeSizeHSD2224, enc_size},
 11681  	},
 11682  }
 11683  
 11684  var a_ARNG_Zn510V1_SizeHSD2224No00 = operand{
 11685  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11686  		{encodeZn510V1, enc_Zn},
 11687  		{encodeSizeHSD2224No00, enc_size},
 11688  	},
 11689  }
 11690  
 11691  var a_ARNG_Zn510V1_SizeTbBHS2224 = operand{
 11692  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11693  		{encodeZn510V1, enc_Zn},
 11694  		{encodeSizeTbBHS2224, enc_size},
 11695  	},
 11696  }
 11697  
 11698  var a_ARNG_Zn510V1_SizeTbBS2224 = operand{
 11699  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11700  		{encodeZn510V1, enc_Zn},
 11701  		{encodeSizeTbBS2224, enc_size},
 11702  	},
 11703  }
 11704  
 11705  var a_ARNG_Zn510V1_SizeTbHSD2224Offset1 = operand{
 11706  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11707  		{encodeZn510V1, enc_Zn},
 11708  		{encodeSizeTbHSD2224Offset1, enc_size},
 11709  	},
 11710  }
 11711  
 11712  var a_ARNG_Zn510V1_SzSD2223 = operand{
 11713  	class: AC_ARNG, elemEncoders: []elemEncoder{
 11714  		{encodeZn510V1, enc_Zn},
 11715  		{encodeSzSD2223, enc_sz},
 11716  	},
 11717  }
 11718  
 11719  var a_IMM_Fimm0_0_1_0_56 = operand{
 11720  	class: AC_IMM, elemEncoders: []elemEncoder{
 11721  		{encodeFimm0_0_1_0_56, enc_i1},
 11722  	},
 11723  }
 11724  
 11725  var a_IMM_Fimm0_0_56 = operand{
 11726  	class: AC_IMM, elemEncoders: []elemEncoder{
 11727  		{encodeFimm0_0_56, enc_NIL},
 11728  	},
 11729  }
 11730  
 11731  var a_IMM_Fimm0_5_1_0_56 = operand{
 11732  	class: AC_IMM, elemEncoders: []elemEncoder{
 11733  		{encodeFimm0_5_1_0_56, enc_i1},
 11734  	},
 11735  }
 11736  
 11737  var a_IMM_Fimm0_5_2_0_56 = operand{
 11738  	class: AC_IMM, elemEncoders: []elemEncoder{
 11739  		{encodeFimm0_5_2_0_56, enc_i1},
 11740  	},
 11741  }
 11742  
 11743  var a_IMM_Imm13_518 = operand{
 11744  	class: AC_IMM, elemEncoders: []elemEncoder{
 11745  		{encodeImm13_518, enc_imm13},
 11746  	},
 11747  }
 11748  
 11749  var a_IMM_Imm31619 = operand{
 11750  	class: AC_IMM, elemEncoders: []elemEncoder{
 11751  		{encodeImm31619, enc_imm3},
 11752  	},
 11753  }
 11754  
 11755  var a_IMM_Imm3Tsize1621Stub = operand{
 11756  	class: AC_IMM, elemEncoders: []elemEncoder{
 11757  		{encodeImm3Tsize1621Stub, enc_tsize_imm3},
 11758  	},
 11759  }
 11760  
 11761  var a_IMM_Imm3Unsigned_1619 = operand{
 11762  	class: AC_IMM, elemEncoders: []elemEncoder{
 11763  		{encodeImm3Unsigned_1619, enc_imm3},
 11764  	},
 11765  }
 11766  
 11767  var a_IMM_Imm41620V7 = operand{
 11768  	class: AC_IMM, elemEncoders: []elemEncoder{
 11769  		{encodeImm41620V7, enc_imm4},
 11770  	},
 11771  }
 11772  
 11773  var a_IMM_Imm4Unsigned_1620 = operand{
 11774  	class: AC_IMM, elemEncoders: []elemEncoder{
 11775  		{encodeImm4Unsigned_1620, enc_imm4},
 11776  	},
 11777  }
 11778  
 11779  var a_IMM_Imm5Signed510Unique = operand{
 11780  	class: AC_IMM, elemEncoders: []elemEncoder{
 11781  		{encodeImm5Signed510Unique, enc_imm5},
 11782  	},
 11783  }
 11784  
 11785  var a_IMM_Imm5Signed_1621V1 = operand{
 11786  	class: AC_IMM, elemEncoders: []elemEncoder{
 11787  		{encodeImm5Signed_1621V1, enc_imm5},
 11788  	},
 11789  }
 11790  
 11791  var a_IMM_Imm5Signed_1621V2 = operand{
 11792  	class: AC_IMM, elemEncoders: []elemEncoder{
 11793  		{encodeImm5Signed_1621V2, enc_imm5},
 11794  	},
 11795  }
 11796  
 11797  var a_IMM_Imm5Signed_510 = operand{
 11798  	class: AC_IMM, elemEncoders: []elemEncoder{
 11799  		{encodeImm5Signed_510, enc_imm5},
 11800  	},
 11801  }
 11802  
 11803  var a_IMM_Imm5bSigned_1621 = operand{
 11804  	class: AC_IMM, elemEncoders: []elemEncoder{
 11805  		{encodeImm5bSigned_1621, enc_imm5b},
 11806  	},
 11807  }
 11808  
 11809  var a_IMM_Imm6Signed_511 = operand{
 11810  	class: AC_IMM, elemEncoders: []elemEncoder{
 11811  		{encodeImm6Signed_511, enc_imm6},
 11812  	},
 11813  }
 11814  
 11815  var a_IMM_Imm7Unsigned_1421 = operand{
 11816  	class: AC_IMM, elemEncoders: []elemEncoder{
 11817  		{encodeImm7Unsigned_1421, enc_imm7},
 11818  	},
 11819  }
 11820  
 11821  var a_IMM_Imm8SignedLsl8 = operand{
 11822  	class: AC_IMM, elemEncoders: []elemEncoder{
 11823  		{encodeImm8SignedLsl8, enc_imm8},
 11824  	},
 11825  }
 11826  
 11827  var a_IMM_Imm8Signed_513 = operand{
 11828  	class: AC_IMM, elemEncoders: []elemEncoder{
 11829  		{encodeImm8Signed_513, enc_imm8},
 11830  	},
 11831  }
 11832  
 11833  var a_IMM_Imm8UnsignedLsl8 = operand{
 11834  	class: AC_IMM, elemEncoders: []elemEncoder{
 11835  		{encodeImm8UnsignedLsl8, enc_imm8},
 11836  	},
 11837  }
 11838  
 11839  var a_IMM_Imm8Unsigned_513 = operand{
 11840  	class: AC_IMM, elemEncoders: []elemEncoder{
 11841  		{encodeImm8Unsigned_513, enc_imm8},
 11842  	},
 11843  }
 11844  
 11845  var a_IMM_Imm8_513_Fimm = operand{
 11846  	class: AC_IMM, elemEncoders: []elemEncoder{
 11847  		{encodeImm8_513_Fimm, enc_imm8},
 11848  	},
 11849  }
 11850  
 11851  var a_IMM_Imm8hImm8l_Unsigned = operand{
 11852  	class: AC_IMM, elemEncoders: []elemEncoder{
 11853  		{encodeImm8hImm8l_Unsigned, enc_imm8h_imm8l},
 11854  	},
 11855  }
 11856  
 11857  var a_IMM_Rot0_90_180_270_1012 = operand{
 11858  	class: AC_IMM, elemEncoders: []elemEncoder{
 11859  		{encodeRot0_90_180_270_1012, enc_rot},
 11860  	},
 11861  }
 11862  
 11863  var a_IMM_Rot0_90_180_270_1315 = operand{
 11864  	class: AC_IMM, elemEncoders: []elemEncoder{
 11865  		{encodeRot0_90_180_270_1315, enc_rot},
 11866  	},
 11867  }
 11868  
 11869  var a_IMM_Rot90_270_1011 = operand{
 11870  	class: AC_IMM, elemEncoders: []elemEncoder{
 11871  		{encodeRot90_270_1011, enc_rot},
 11872  	},
 11873  }
 11874  
 11875  var a_IMM_Rot90_270_1617 = operand{
 11876  	class: AC_IMM, elemEncoders: []elemEncoder{
 11877  		{encodeRot90_270_1617, enc_rot},
 11878  	},
 11879  }
 11880  
 11881  var a_IMM_ShiftTsz1619Range0V1 = operand{
 11882  	class: AC_IMM, elemEncoders: []elemEncoder{
 11883  		{encodeShiftTsz1619Range0V1, enc_tszh_tszl_imm3},
 11884  	},
 11885  }
 11886  
 11887  var a_IMM_ShiftTsz1619Range0V2 = operand{
 11888  	class: AC_IMM, elemEncoders: []elemEncoder{
 11889  		{encodeShiftTsz1619Range0V2, enc_tszh_tszl_imm3},
 11890  	},
 11891  }
 11892  
 11893  var a_IMM_ShiftTsz1619Range1V1 = operand{
 11894  	class: AC_IMM, elemEncoders: []elemEncoder{
 11895  		{encodeShiftTsz1619Range1V1, enc_tszh_tszl_imm3},
 11896  	},
 11897  }
 11898  
 11899  var a_IMM_ShiftTsz1619Range1V2 = operand{
 11900  	class: AC_IMM, elemEncoders: []elemEncoder{
 11901  		{encodeShiftTsz1619Range1V2, enc_tszh_tszl_imm3},
 11902  	},
 11903  }
 11904  
 11905  var a_IMM_ShiftTsz58Range0 = operand{
 11906  	class: AC_IMM, elemEncoders: []elemEncoder{
 11907  		{encodeShiftTsz58Range0, enc_tszh_tszl_imm3},
 11908  	},
 11909  }
 11910  
 11911  var a_IMM_ShiftTsz58Range1 = operand{
 11912  	class: AC_IMM, elemEncoders: []elemEncoder{
 11913  		{encodeShiftTsz58Range1, enc_tszh_tszl_imm3},
 11914  	},
 11915  }
 11916  
 11917  var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check = operand{
 11918  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11919  		{encodeRn510SPV2, enc_Rn},
 11920  		{encodeNoop, enc_NIL},
 11921  		{encodeRm1621V2, enc_Rm},
 11922  		{encodeNoop, enc_NIL},
 11923  		{encodeModLSLCheck, enc_NIL},
 11924  		{encodeModAmt1Check, enc_NIL},
 11925  	},
 11926  }
 11927  
 11928  var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check = operand{
 11929  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11930  		{encodeRn510SPV2, enc_Rn},
 11931  		{encodeNoop, enc_NIL},
 11932  		{encodeRm1621V2, enc_Rm},
 11933  		{encodeNoop, enc_NIL},
 11934  		{encodeModLSLCheck, enc_NIL},
 11935  		{encodeModAmt2Check, enc_NIL},
 11936  	},
 11937  }
 11938  
 11939  var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check = operand{
 11940  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11941  		{encodeRn510SPV2, enc_Rn},
 11942  		{encodeNoop, enc_NIL},
 11943  		{encodeRm1621V2, enc_Rm},
 11944  		{encodeNoop, enc_NIL},
 11945  		{encodeModLSLCheck, enc_NIL},
 11946  		{encodeModAmt3Check, enc_NIL},
 11947  	},
 11948  }
 11949  
 11950  var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check = operand{
 11951  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11952  		{encodeRn510SPV2, enc_Rn},
 11953  		{encodeNoop, enc_NIL},
 11954  		{encodeRm1621V2, enc_Rm},
 11955  		{encodeNoop, enc_NIL},
 11956  		{encodeModLSLCheck, enc_NIL},
 11957  		{encodeModAmt4Check, enc_NIL},
 11958  	},
 11959  }
 11960  
 11961  var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck = operand{
 11962  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11963  		{encodeRn510SPV2, enc_Rn},
 11964  		{encodeNoop, enc_NIL},
 11965  		{encodeRm1621V2, enc_Rm},
 11966  		{encodeNoop, enc_NIL},
 11967  		{encodeNoModCheck, enc_NIL},
 11968  		{encodeNoAmtCheck, enc_NIL},
 11969  	},
 11970  }
 11971  
 11972  var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check = operand{
 11973  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11974  		{encodeRn510SPV2, enc_Rn},
 11975  		{encodeNoop, enc_NIL},
 11976  		{encodeRm1621XZR, enc_Rm},
 11977  		{encodeNoop, enc_NIL},
 11978  		{encodeModLSLCheck, enc_NIL},
 11979  		{encodeModAmt1Check, enc_NIL},
 11980  	},
 11981  }
 11982  
 11983  var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check = operand{
 11984  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11985  		{encodeRn510SPV2, enc_Rn},
 11986  		{encodeNoop, enc_NIL},
 11987  		{encodeRm1621XZR, enc_Rm},
 11988  		{encodeNoop, enc_NIL},
 11989  		{encodeModLSLCheck, enc_NIL},
 11990  		{encodeModAmt2Check, enc_NIL},
 11991  	},
 11992  }
 11993  
 11994  var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check = operand{
 11995  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 11996  		{encodeRn510SPV2, enc_Rn},
 11997  		{encodeNoop, enc_NIL},
 11998  		{encodeRm1621XZR, enc_Rm},
 11999  		{encodeNoop, enc_NIL},
 12000  		{encodeModLSLCheck, enc_NIL},
 12001  		{encodeModAmt3Check, enc_NIL},
 12002  	},
 12003  }
 12004  
 12005  var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{
 12006  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12007  		{encodeRn510SPV2, enc_Rn},
 12008  		{encodeNoop, enc_NIL},
 12009  		{encodeRm1621XZR, enc_Rm},
 12010  		{encodeNoop, enc_NIL},
 12011  		{encodeNoModCheck, enc_NIL},
 12012  		{encodeNoAmtCheck, enc_NIL},
 12013  	},
 12014  }
 12015  
 12016  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check = operand{
 12017  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12018  		{encodeRn510SPV2, enc_Rn},
 12019  		{encodeNoop, enc_NIL},
 12020  		{encodeZm1621V3, enc_Zm},
 12021  		{encodeArngDCheck, enc_NIL},
 12022  		{encodeModLSLCheck, enc_NIL},
 12023  		{encodeModAmt1Check, enc_NIL},
 12024  	},
 12025  }
 12026  
 12027  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check = operand{
 12028  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12029  		{encodeRn510SPV2, enc_Rn},
 12030  		{encodeNoop, enc_NIL},
 12031  		{encodeZm1621V3, enc_Zm},
 12032  		{encodeArngDCheck, enc_NIL},
 12033  		{encodeModLSLCheck, enc_NIL},
 12034  		{encodeModAmt2Check, enc_NIL},
 12035  	},
 12036  }
 12037  
 12038  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check = operand{
 12039  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12040  		{encodeRn510SPV2, enc_Rn},
 12041  		{encodeNoop, enc_NIL},
 12042  		{encodeZm1621V3, enc_Zm},
 12043  		{encodeArngDCheck, enc_NIL},
 12044  		{encodeModLSLCheck, enc_NIL},
 12045  		{encodeModAmt3Check, enc_NIL},
 12046  	},
 12047  }
 12048  
 12049  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck = operand{
 12050  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12051  		{encodeRn510SPV2, enc_Rn},
 12052  		{encodeNoop, enc_NIL},
 12053  		{encodeZm1621V3, enc_Zm},
 12054  		{encodeArngDCheck, enc_NIL},
 12055  		{encodeNoModCheck, enc_NIL},
 12056  		{encodeNoAmtCheck, enc_NIL},
 12057  	},
 12058  }
 12059  
 12060  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check = operand{
 12061  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12062  		{encodeRn510SPV2, enc_Rn},
 12063  		{encodeNoop, enc_NIL},
 12064  		{encodeZm1621V3, enc_Zm},
 12065  		{encodeArngDCheck, enc_NIL},
 12066  		{encodeXs1415, enc_xs},
 12067  		{encodeModAmt1Check, enc_NIL},
 12068  	},
 12069  }
 12070  
 12071  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check = operand{
 12072  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12073  		{encodeRn510SPV2, enc_Rn},
 12074  		{encodeNoop, enc_NIL},
 12075  		{encodeZm1621V3, enc_Zm},
 12076  		{encodeArngDCheck, enc_NIL},
 12077  		{encodeXs1415, enc_xs},
 12078  		{encodeModAmt2Check, enc_NIL},
 12079  	},
 12080  }
 12081  
 12082  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check = operand{
 12083  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12084  		{encodeRn510SPV2, enc_Rn},
 12085  		{encodeNoop, enc_NIL},
 12086  		{encodeZm1621V3, enc_Zm},
 12087  		{encodeArngDCheck, enc_NIL},
 12088  		{encodeXs1415, enc_xs},
 12089  		{encodeModAmt3Check, enc_NIL},
 12090  	},
 12091  }
 12092  
 12093  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck = operand{
 12094  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12095  		{encodeRn510SPV2, enc_Rn},
 12096  		{encodeNoop, enc_NIL},
 12097  		{encodeZm1621V3, enc_Zm},
 12098  		{encodeArngDCheck, enc_NIL},
 12099  		{encodeXs1415, enc_xs},
 12100  		{encodeNoAmtCheck, enc_NIL},
 12101  	},
 12102  }
 12103  
 12104  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check = operand{
 12105  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12106  		{encodeRn510SPV2, enc_Rn},
 12107  		{encodeNoop, enc_NIL},
 12108  		{encodeZm1621V3, enc_Zm},
 12109  		{encodeArngDCheck, enc_NIL},
 12110  		{encodeXs2223, enc_xs},
 12111  		{encodeModAmt1Check, enc_NIL},
 12112  	},
 12113  }
 12114  
 12115  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check = operand{
 12116  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12117  		{encodeRn510SPV2, enc_Rn},
 12118  		{encodeNoop, enc_NIL},
 12119  		{encodeZm1621V3, enc_Zm},
 12120  		{encodeArngDCheck, enc_NIL},
 12121  		{encodeXs2223, enc_xs},
 12122  		{encodeModAmt2Check, enc_NIL},
 12123  	},
 12124  }
 12125  
 12126  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check = operand{
 12127  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12128  		{encodeRn510SPV2, enc_Rn},
 12129  		{encodeNoop, enc_NIL},
 12130  		{encodeZm1621V3, enc_Zm},
 12131  		{encodeArngDCheck, enc_NIL},
 12132  		{encodeXs2223, enc_xs},
 12133  		{encodeModAmt3Check, enc_NIL},
 12134  	},
 12135  }
 12136  
 12137  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck = operand{
 12138  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12139  		{encodeRn510SPV2, enc_Rn},
 12140  		{encodeNoop, enc_NIL},
 12141  		{encodeZm1621V3, enc_Zm},
 12142  		{encodeArngDCheck, enc_NIL},
 12143  		{encodeXs2223, enc_xs},
 12144  		{encodeNoAmtCheck, enc_NIL},
 12145  	},
 12146  }
 12147  
 12148  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check = operand{
 12149  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12150  		{encodeRn510SPV2, enc_Rn},
 12151  		{encodeNoop, enc_NIL},
 12152  		{encodeZm1621V3, enc_Zm},
 12153  		{encodeArngSCheck, enc_NIL},
 12154  		{encodeXs1415, enc_xs},
 12155  		{encodeModAmt1Check, enc_NIL},
 12156  	},
 12157  }
 12158  
 12159  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check = operand{
 12160  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12161  		{encodeRn510SPV2, enc_Rn},
 12162  		{encodeNoop, enc_NIL},
 12163  		{encodeZm1621V3, enc_Zm},
 12164  		{encodeArngSCheck, enc_NIL},
 12165  		{encodeXs1415, enc_xs},
 12166  		{encodeModAmt2Check, enc_NIL},
 12167  	},
 12168  }
 12169  
 12170  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck = operand{
 12171  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12172  		{encodeRn510SPV2, enc_Rn},
 12173  		{encodeNoop, enc_NIL},
 12174  		{encodeZm1621V3, enc_Zm},
 12175  		{encodeArngSCheck, enc_NIL},
 12176  		{encodeXs1415, enc_xs},
 12177  		{encodeNoAmtCheck, enc_NIL},
 12178  	},
 12179  }
 12180  
 12181  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check = operand{
 12182  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12183  		{encodeRn510SPV2, enc_Rn},
 12184  		{encodeNoop, enc_NIL},
 12185  		{encodeZm1621V3, enc_Zm},
 12186  		{encodeArngSCheck, enc_NIL},
 12187  		{encodeXs2223, enc_xs},
 12188  		{encodeModAmt1Check, enc_NIL},
 12189  	},
 12190  }
 12191  
 12192  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check = operand{
 12193  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12194  		{encodeRn510SPV2, enc_Rn},
 12195  		{encodeNoop, enc_NIL},
 12196  		{encodeZm1621V3, enc_Zm},
 12197  		{encodeArngSCheck, enc_NIL},
 12198  		{encodeXs2223, enc_xs},
 12199  		{encodeModAmt2Check, enc_NIL},
 12200  	},
 12201  }
 12202  
 12203  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt3Check = operand{
 12204  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12205  		{encodeRn510SPV2, enc_Rn},
 12206  		{encodeNoop, enc_NIL},
 12207  		{encodeZm1621V3, enc_Zm},
 12208  		{encodeArngSCheck, enc_NIL},
 12209  		{encodeXs2223, enc_xs},
 12210  		{encodeModAmt3Check, enc_NIL},
 12211  	},
 12212  }
 12213  
 12214  var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck = operand{
 12215  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12216  		{encodeRn510SPV2, enc_Rn},
 12217  		{encodeNoop, enc_NIL},
 12218  		{encodeZm1621V3, enc_Zm},
 12219  		{encodeArngSCheck, enc_NIL},
 12220  		{encodeXs2223, enc_xs},
 12221  		{encodeNoAmtCheck, enc_NIL},
 12222  	},
 12223  }
 12224  
 12225  var a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{
 12226  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12227  		{encodeZn510V2, enc_Zn},
 12228  		{encodeArngDCheck, enc_NIL},
 12229  		{encodeRm1621XZR, enc_Rm},
 12230  		{encodeNoop, enc_NIL},
 12231  		{encodeNoModCheck, enc_NIL},
 12232  		{encodeNoAmtCheck, enc_NIL},
 12233  	},
 12234  }
 12235  
 12236  var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount = operand{
 12237  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12238  		{encodeZn510V2, enc_Zn},
 12239  		{encodeArngDCheck, enc_NIL},
 12240  		{encodeZm1621V3, enc_Zm},
 12241  		{encodeArngDCheck, enc_NIL},
 12242  		{encodeModSXTWCheck, enc_NIL},
 12243  		{encodeMsz1012Amount, enc_msz},
 12244  	},
 12245  }
 12246  
 12247  var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount = operand{
 12248  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12249  		{encodeZn510V2, enc_Zn},
 12250  		{encodeArngDCheck, enc_NIL},
 12251  		{encodeZm1621V3, enc_Zm},
 12252  		{encodeArngDCheck, enc_NIL},
 12253  		{encodeModUXTWCheck, enc_NIL},
 12254  		{encodeMsz1012Amount, enc_msz},
 12255  	},
 12256  }
 12257  
 12258  var a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{
 12259  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12260  		{encodeZn510V2, enc_Zn},
 12261  		{encodeArngSCheck, enc_NIL},
 12262  		{encodeRm1621XZR, enc_Rm},
 12263  		{encodeNoop, enc_NIL},
 12264  		{encodeNoModCheck, enc_NIL},
 12265  		{encodeNoAmtCheck, enc_NIL},
 12266  	},
 12267  }
 12268  
 12269  var a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount = operand{
 12270  	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 12271  		{encodeZn510V2, enc_Zn},
 12272  		{encodeSzSD2223, enc_sz},
 12273  		{encodeZm1621V3, enc_Zm},
 12274  		{encodeSzSD2223, enc_sz},
 12275  		{encodeMsz1012, enc_msz},
 12276  		{encodeMsz1012Amount, enc_msz},
 12277  	},
 12278  }
 12279  
 12280  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3 = operand{
 12281  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12282  		{encodeRn510SPV2, enc_Rn},
 12283  		{encodeNoop, enc_NIL},
 12284  		{encodeImm41620V3, enc_imm4},
 12285  	},
 12286  }
 12287  
 12288  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4 = operand{
 12289  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12290  		{encodeRn510SPV2, enc_Rn},
 12291  		{encodeNoop, enc_NIL},
 12292  		{encodeImm41620V4, enc_imm4},
 12293  	},
 12294  }
 12295  
 12296  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5 = operand{
 12297  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12298  		{encodeRn510SPV2, enc_Rn},
 12299  		{encodeNoop, enc_NIL},
 12300  		{encodeImm41620V5, enc_imm4},
 12301  	},
 12302  }
 12303  
 12304  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6 = operand{
 12305  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12306  		{encodeRn510SPV2, enc_Rn},
 12307  		{encodeNoop, enc_NIL},
 12308  		{encodeImm41620V6, enc_imm4},
 12309  	},
 12310  }
 12311  
 12312  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8 = operand{
 12313  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12314  		{encodeRn510SPV2, enc_Rn},
 12315  		{encodeNoop, enc_NIL},
 12316  		{encodeImm41620V8, enc_imm4},
 12317  	},
 12318  }
 12319  
 12320  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9 = operand{
 12321  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12322  		{encodeRn510SPV2, enc_Rn},
 12323  		{encodeNoop, enc_NIL},
 12324  		{encodeImm41620V9, enc_imm4},
 12325  	},
 12326  }
 12327  
 12328  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm61622V5 = operand{
 12329  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12330  		{encodeRn510SPV2, enc_Rn},
 12331  		{encodeNoop, enc_NIL},
 12332  		{encodeImm61622V5, enc_imm6},
 12333  	},
 12334  }
 12335  
 12336  var a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013 = operand{
 12337  	class: AC_MEMOFFMULVL, elemEncoders: []elemEncoder{
 12338  		{encodeRn510SPV2, enc_Rn},
 12339  		{encodeNoop, enc_NIL},
 12340  		{encodeImm9h1622L1013, enc_imm9h_imm9l},
 12341  	},
 12342  }
 12343  
 12344  var a_MEMOFF_Rn510SPV2_Noop_Imm41620V1 = operand{
 12345  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12346  		{encodeRn510SPV2, enc_Rn},
 12347  		{encodeNoop, enc_NIL},
 12348  		{encodeImm41620V1, enc_imm4},
 12349  	},
 12350  }
 12351  
 12352  var a_MEMOFF_Rn510SPV2_Noop_Imm41620V2 = operand{
 12353  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12354  		{encodeRn510SPV2, enc_Rn},
 12355  		{encodeNoop, enc_NIL},
 12356  		{encodeImm41620V2, enc_imm4},
 12357  	},
 12358  }
 12359  
 12360  var a_MEMOFF_Rn510SPV2_Noop_Imm61622V1 = operand{
 12361  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12362  		{encodeRn510SPV2, enc_Rn},
 12363  		{encodeNoop, enc_NIL},
 12364  		{encodeImm61622V1, enc_imm6},
 12365  	},
 12366  }
 12367  
 12368  var a_MEMOFF_Rn510SPV2_Noop_Imm61622V2 = operand{
 12369  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12370  		{encodeRn510SPV2, enc_Rn},
 12371  		{encodeNoop, enc_NIL},
 12372  		{encodeImm61622V2, enc_imm6},
 12373  	},
 12374  }
 12375  
 12376  var a_MEMOFF_Rn510SPV2_Noop_Imm61622V3 = operand{
 12377  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12378  		{encodeRn510SPV2, enc_Rn},
 12379  		{encodeNoop, enc_NIL},
 12380  		{encodeImm61622V3, enc_imm6},
 12381  	},
 12382  }
 12383  
 12384  var a_MEMOFF_Rn510SPV2_Noop_Imm61622V4 = operand{
 12385  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12386  		{encodeRn510SPV2, enc_Rn},
 12387  		{encodeNoop, enc_NIL},
 12388  		{encodeImm61622V4, enc_imm6},
 12389  	},
 12390  }
 12391  
 12392  var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1 = operand{
 12393  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12394  		{encodeZn510V2, enc_Zn},
 12395  		{encodeArngDCheck, enc_NIL},
 12396  		{encodeImm51621V1, enc_imm5},
 12397  	},
 12398  }
 12399  
 12400  var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2 = operand{
 12401  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12402  		{encodeZn510V2, enc_Zn},
 12403  		{encodeArngDCheck, enc_NIL},
 12404  		{encodeImm51621V2, enc_imm5},
 12405  	},
 12406  }
 12407  
 12408  var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3 = operand{
 12409  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12410  		{encodeZn510V2, enc_Zn},
 12411  		{encodeArngDCheck, enc_NIL},
 12412  		{encodeImm51621V3, enc_imm5},
 12413  	},
 12414  }
 12415  
 12416  var a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4 = operand{
 12417  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12418  		{encodeZn510V2, enc_Zn},
 12419  		{encodeArngDCheck, enc_NIL},
 12420  		{encodeImm51621V4, enc_imm5},
 12421  	},
 12422  }
 12423  
 12424  var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1 = operand{
 12425  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12426  		{encodeZn510V2, enc_Zn},
 12427  		{encodeArngSCheck, enc_NIL},
 12428  		{encodeImm51621V1, enc_imm5},
 12429  	},
 12430  }
 12431  
 12432  var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2 = operand{
 12433  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12434  		{encodeZn510V2, enc_Zn},
 12435  		{encodeArngSCheck, enc_NIL},
 12436  		{encodeImm51621V2, enc_imm5},
 12437  	},
 12438  }
 12439  
 12440  var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V3 = operand{
 12441  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12442  		{encodeZn510V2, enc_Zn},
 12443  		{encodeArngSCheck, enc_NIL},
 12444  		{encodeImm51621V3, enc_imm5},
 12445  	},
 12446  }
 12447  
 12448  var a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4 = operand{
 12449  	class: AC_MEMOFF, elemEncoders: []elemEncoder{
 12450  		{encodeZn510V2, enc_Zn},
 12451  		{encodeArngSCheck, enc_NIL},
 12452  		{encodeImm51621V4, enc_imm5},
 12453  	},
 12454  }
 12455  
 12456  var a_PREGIDX_PnN_58_Noop_I189 = operand{
 12457  	class: AC_PREGIDX, elemEncoders: []elemEncoder{
 12458  		{encodePnN_58, enc_PNn},
 12459  		{encodeNoop, enc_NIL},
 12460  		{encodeI189, enc_i1},
 12461  	},
 12462  }
 12463  
 12464  var a_PREGIDX_PnN_58_Noop_Imm2_810 = operand{
 12465  	class: AC_PREGIDX, elemEncoders: []elemEncoder{
 12466  		{encodePnN_58, enc_PNn},
 12467  		{encodeNoop, enc_NIL},
 12468  		{encodeImm2_810, enc_imm2},
 12469  	},
 12470  }
 12471  
 12472  var a_PREGZM_PNg1013_ZeroPredCheck = operand{
 12473  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12474  		{encodePNg1013, enc_PNg},
 12475  		{encodeZeroPredCheck, enc_NIL},
 12476  	},
 12477  }
 12478  
 12479  var a_PREGZM_Pg1013_MergePredCheck = operand{
 12480  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12481  		{encodePg1013, enc_Pg},
 12482  		{encodeMergePredCheck, enc_NIL},
 12483  	},
 12484  }
 12485  
 12486  var a_PREGZM_Pg1013_PredQualM1617 = operand{
 12487  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12488  		{encodePg1013, enc_Pg},
 12489  		{encodePredQualM1617, enc_M},
 12490  	},
 12491  }
 12492  
 12493  var a_PREGZM_Pg1013_ZeroPredCheck = operand{
 12494  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12495  		{encodePg1013, enc_Pg},
 12496  		{encodeZeroPredCheck, enc_NIL},
 12497  	},
 12498  }
 12499  
 12500  var a_PREGZM_Pg1014_PredQualM45 = operand{
 12501  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12502  		{encodePg1014, enc_Pg},
 12503  		{encodePredQualM45, enc_M},
 12504  	},
 12505  }
 12506  
 12507  var a_PREGZM_Pg1014_ZeroPredCheck = operand{
 12508  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12509  		{encodePg1014, enc_Pg},
 12510  		{encodeZeroPredCheck, enc_NIL},
 12511  	},
 12512  }
 12513  
 12514  var a_PREGZM_Pg1620_MergePredCheck = operand{
 12515  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12516  		{encodePg1620, enc_Pg},
 12517  		{encodeMergePredCheck, enc_NIL},
 12518  	},
 12519  }
 12520  
 12521  var a_PREGZM_Pg1620_ZeroPredCheck = operand{
 12522  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12523  		{encodePg1620, enc_Pg},
 12524  		{encodeZeroPredCheck, enc_NIL},
 12525  	},
 12526  }
 12527  
 12528  var a_PREGZM_Pg59_ZeroPredCheck = operand{
 12529  	class: AC_PREGZM, elemEncoders: []elemEncoder{
 12530  		{encodePg59, enc_Pg},
 12531  		{encodeZeroPredCheck, enc_NIL},
 12532  	},
 12533  }
 12534  
 12535  var a_PREG_PNg1013_Noop = operand{
 12536  	class: AC_PREG, elemEncoders: []elemEncoder{
 12537  		{encodePNg1013, enc_PNg},
 12538  		{encodeNoop, enc_NIL},
 12539  	},
 12540  }
 12541  
 12542  var a_PREG_Pg1013_Noop = operand{
 12543  	class: AC_PREG, elemEncoders: []elemEncoder{
 12544  		{encodePg1013, enc_Pg},
 12545  		{encodeNoop, enc_NIL},
 12546  	},
 12547  }
 12548  
 12549  var a_PREG_Pg1014_Noop = operand{
 12550  	class: AC_PREG, elemEncoders: []elemEncoder{
 12551  		{encodePg1014, enc_Pg},
 12552  		{encodeNoop, enc_NIL},
 12553  	},
 12554  }
 12555  
 12556  var a_PREG_Pg59_Noop = operand{
 12557  	class: AC_PREG, elemEncoders: []elemEncoder{
 12558  		{encodePg59, enc_Pg},
 12559  		{encodeNoop, enc_NIL},
 12560  	},
 12561  }
 12562  
 12563  var a_PREG_Pt04V1_Noop = operand{
 12564  	class: AC_PREG, elemEncoders: []elemEncoder{
 12565  		{encodePt04V1, enc_Pt},
 12566  		{encodeNoop, enc_NIL},
 12567  	},
 12568  }
 12569  
 12570  var a_PREG_Pt04V2_Noop = operand{
 12571  	class: AC_PREG, elemEncoders: []elemEncoder{
 12572  		{encodePt04V2, enc_Pt},
 12573  		{encodeNoop, enc_NIL},
 12574  	},
 12575  }
 12576  
 12577  var a_PREG_Pv1013_Noop = operand{
 12578  	class: AC_PREG, elemEncoders: []elemEncoder{
 12579  		{encodePv1013, enc_Pv},
 12580  		{encodeNoop, enc_NIL},
 12581  	},
 12582  }
 12583  
 12584  var a_PREG_Pv1014_Noop = operand{
 12585  	class: AC_PREG, elemEncoders: []elemEncoder{
 12586  		{encodePv1014, enc_Pv},
 12587  		{encodeNoop, enc_NIL},
 12588  	},
 12589  }
 12590  
 12591  var a_PREG_Pv59_Noop = operand{
 12592  	class: AC_PREG, elemEncoders: []elemEncoder{
 12593  		{encodePv59, enc_Pv},
 12594  		{encodeNoop, enc_NIL},
 12595  	},
 12596  }
 12597  
 12598  var a_REGLIST1_Zn510Table3_ArngBCheck = operand{
 12599  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12600  		{encodeZn510Table3, enc_Zn},
 12601  		{encodeArngBCheck, enc_NIL},
 12602  	},
 12603  }
 12604  
 12605  var a_REGLIST1_Zn510Table3_ArngHCheck = operand{
 12606  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12607  		{encodeZn510Table3, enc_Zn},
 12608  		{encodeArngHCheck, enc_NIL},
 12609  	},
 12610  }
 12611  
 12612  var a_REGLIST1_Zn510V1_SizeBHSD2224 = operand{
 12613  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12614  		{encodeZn510V1, enc_Zn},
 12615  		{encodeSizeBHSD2224, enc_size},
 12616  	},
 12617  }
 12618  
 12619  var a_REGLIST1_Zt05_ArngBCheck = operand{
 12620  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12621  		{encodeZt05, enc_Zt},
 12622  		{encodeArngBCheck, enc_NIL},
 12623  	},
 12624  }
 12625  
 12626  var a_REGLIST1_Zt05_ArngDCheck = operand{
 12627  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12628  		{encodeZt05, enc_Zt},
 12629  		{encodeArngDCheck, enc_NIL},
 12630  	},
 12631  }
 12632  
 12633  var a_REGLIST1_Zt05_ArngHCheck = operand{
 12634  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12635  		{encodeZt05, enc_Zt},
 12636  		{encodeArngHCheck, enc_NIL},
 12637  	},
 12638  }
 12639  
 12640  var a_REGLIST1_Zt05_ArngQCheck = operand{
 12641  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12642  		{encodeZt05, enc_Zt},
 12643  		{encodeArngQCheck, enc_NIL},
 12644  	},
 12645  }
 12646  
 12647  var a_REGLIST1_Zt05_ArngSCheck = operand{
 12648  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12649  		{encodeZt05, enc_Zt},
 12650  		{encodeArngSCheck, enc_NIL},
 12651  	},
 12652  }
 12653  
 12654  var a_REGLIST1_Zt05_Size2123V1 = operand{
 12655  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12656  		{encodeZt05, enc_Zt},
 12657  		{encodeSize2123V1, enc_size},
 12658  	},
 12659  }
 12660  
 12661  var a_REGLIST1_Zt05_Size2123V2 = operand{
 12662  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12663  		{encodeZt05, enc_Zt},
 12664  		{encodeSize2123V2, enc_size},
 12665  	},
 12666  }
 12667  
 12668  var a_REGLIST1_Zt05_Sz2122 = operand{
 12669  	class: AC_REGLIST1, elemEncoders: []elemEncoder{
 12670  		{encodeZt05, enc_Zt},
 12671  		{encodeSz2122, enc_sz},
 12672  	},
 12673  }
 12674  
 12675  var a_REGLIST2_GenZn510V1_SizeBHSD2224_GenZn510V2_SizeBHSD2224 = operand{
 12676  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12677  		{encodeGenZn510V1, enc_Zn},
 12678  		{encodeSizeBHSD2224, enc_size},
 12679  		{encodeGenZn510V2, enc_Zn},
 12680  		{encodeSizeBHSD2224, enc_size},
 12681  	},
 12682  }
 12683  
 12684  var a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224 = operand{
 12685  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12686  		{encodePd04, enc_Pd},
 12687  		{encodeSizeBHSD2224, enc_size},
 12688  		{encodePd04Plus1, enc_Pd},
 12689  		{encodeSizeBHSD2224, enc_size},
 12690  	},
 12691  }
 12692  
 12693  var a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224 = operand{
 12694  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12695  		{encodePd14, enc_Pd},
 12696  		{encodeSizeBHSD2224, enc_size},
 12697  		{encodePd14Plus1, enc_Pd},
 12698  		{encodeSizeBHSD2224, enc_size},
 12699  	},
 12700  }
 12701  
 12702  var a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck = operand{
 12703  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12704  		{encodeZn510MultiSrc1, enc_Zn},
 12705  		{encodeArngBCheck, enc_NIL},
 12706  		{encodeZn510MultiSrc2, enc_Zn},
 12707  		{encodeArngBCheck, enc_NIL},
 12708  	},
 12709  }
 12710  
 12711  var a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224 = operand{
 12712  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12713  		{encodeZn510MultiSrc1, enc_Zn},
 12714  		{encodeSizeBHSD2224, enc_size},
 12715  		{encodeZn510MultiSrc2, enc_Zn},
 12716  		{encodeSizeBHSD2224, enc_size},
 12717  	},
 12718  }
 12719  
 12720  var a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck = operand{
 12721  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12722  		{encodeZn510Table1, enc_Zn},
 12723  		{encodeArngBCheck, enc_NIL},
 12724  		{encodeZn510Table2, enc_Zn},
 12725  		{encodeArngBCheck, enc_NIL},
 12726  	},
 12727  }
 12728  
 12729  var a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck = operand{
 12730  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12731  		{encodeZn510Table1, enc_Zn},
 12732  		{encodeArngHCheck, enc_NIL},
 12733  		{encodeZn510Table2, enc_Zn},
 12734  		{encodeArngHCheck, enc_NIL},
 12735  	},
 12736  }
 12737  
 12738  var a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck = operand{
 12739  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12740  		{encodeZt051, enc_Zt},
 12741  		{encodeArngBCheck, enc_NIL},
 12742  		{encodeZt052, enc_Zt},
 12743  		{encodeArngBCheck, enc_NIL},
 12744  	},
 12745  }
 12746  
 12747  var a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck = operand{
 12748  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12749  		{encodeZt051, enc_Zt},
 12750  		{encodeArngDCheck, enc_NIL},
 12751  		{encodeZt052, enc_Zt},
 12752  		{encodeArngDCheck, enc_NIL},
 12753  	},
 12754  }
 12755  
 12756  var a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck = operand{
 12757  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12758  		{encodeZt051, enc_Zt},
 12759  		{encodeArngHCheck, enc_NIL},
 12760  		{encodeZt052, enc_Zt},
 12761  		{encodeArngHCheck, enc_NIL},
 12762  	},
 12763  }
 12764  
 12765  var a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck = operand{
 12766  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12767  		{encodeZt051, enc_Zt},
 12768  		{encodeArngQCheck, enc_NIL},
 12769  		{encodeZt052, enc_Zt},
 12770  		{encodeArngQCheck, enc_NIL},
 12771  	},
 12772  }
 12773  
 12774  var a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck = operand{
 12775  	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 12776  		{encodeZt051, enc_Zt},
 12777  		{encodeArngSCheck, enc_NIL},
 12778  		{encodeZt052, enc_Zt},
 12779  		{encodeArngSCheck, enc_NIL},
 12780  	},
 12781  }
 12782  
 12783  var a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck = operand{
 12784  	class: AC_REGLIST3, elemEncoders: []elemEncoder{
 12785  		{encodeZt051, enc_Zt},
 12786  		{encodeArngBCheck, enc_NIL},
 12787  		{encodeZt052, enc_Zt},
 12788  		{encodeArngBCheck, enc_NIL},
 12789  		{encodeZt053, enc_Zt},
 12790  		{encodeArngBCheck, enc_NIL},
 12791  	},
 12792  }
 12793  
 12794  var a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck = operand{
 12795  	class: AC_REGLIST3, elemEncoders: []elemEncoder{
 12796  		{encodeZt051, enc_Zt},
 12797  		{encodeArngDCheck, enc_NIL},
 12798  		{encodeZt052, enc_Zt},
 12799  		{encodeArngDCheck, enc_NIL},
 12800  		{encodeZt053, enc_Zt},
 12801  		{encodeArngDCheck, enc_NIL},
 12802  	},
 12803  }
 12804  
 12805  var a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck = operand{
 12806  	class: AC_REGLIST3, elemEncoders: []elemEncoder{
 12807  		{encodeZt051, enc_Zt},
 12808  		{encodeArngHCheck, enc_NIL},
 12809  		{encodeZt052, enc_Zt},
 12810  		{encodeArngHCheck, enc_NIL},
 12811  		{encodeZt053, enc_Zt},
 12812  		{encodeArngHCheck, enc_NIL},
 12813  	},
 12814  }
 12815  
 12816  var a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck = operand{
 12817  	class: AC_REGLIST3, elemEncoders: []elemEncoder{
 12818  		{encodeZt051, enc_Zt},
 12819  		{encodeArngQCheck, enc_NIL},
 12820  		{encodeZt052, enc_Zt},
 12821  		{encodeArngQCheck, enc_NIL},
 12822  		{encodeZt053, enc_Zt},
 12823  		{encodeArngQCheck, enc_NIL},
 12824  	},
 12825  }
 12826  
 12827  var a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck = operand{
 12828  	class: AC_REGLIST3, elemEncoders: []elemEncoder{
 12829  		{encodeZt051, enc_Zt},
 12830  		{encodeArngSCheck, enc_NIL},
 12831  		{encodeZt052, enc_Zt},
 12832  		{encodeArngSCheck, enc_NIL},
 12833  		{encodeZt053, enc_Zt},
 12834  		{encodeArngSCheck, enc_NIL},
 12835  	},
 12836  }
 12837  
 12838  var a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck = operand{
 12839  	class: AC_REGLIST4, elemEncoders: []elemEncoder{
 12840  		{encodeZt051, enc_Zt},
 12841  		{encodeArngBCheck, enc_NIL},
 12842  		{encodeZt052, enc_Zt},
 12843  		{encodeArngBCheck, enc_NIL},
 12844  		{encodeZt053, enc_Zt},
 12845  		{encodeArngBCheck, enc_NIL},
 12846  		{encodeZt054, enc_Zt},
 12847  		{encodeArngBCheck, enc_NIL},
 12848  	},
 12849  }
 12850  
 12851  var a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck = operand{
 12852  	class: AC_REGLIST4, elemEncoders: []elemEncoder{
 12853  		{encodeZt051, enc_Zt},
 12854  		{encodeArngDCheck, enc_NIL},
 12855  		{encodeZt052, enc_Zt},
 12856  		{encodeArngDCheck, enc_NIL},
 12857  		{encodeZt053, enc_Zt},
 12858  		{encodeArngDCheck, enc_NIL},
 12859  		{encodeZt054, enc_Zt},
 12860  		{encodeArngDCheck, enc_NIL},
 12861  	},
 12862  }
 12863  
 12864  var a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck = operand{
 12865  	class: AC_REGLIST4, elemEncoders: []elemEncoder{
 12866  		{encodeZt051, enc_Zt},
 12867  		{encodeArngHCheck, enc_NIL},
 12868  		{encodeZt052, enc_Zt},
 12869  		{encodeArngHCheck, enc_NIL},
 12870  		{encodeZt053, enc_Zt},
 12871  		{encodeArngHCheck, enc_NIL},
 12872  		{encodeZt054, enc_Zt},
 12873  		{encodeArngHCheck, enc_NIL},
 12874  	},
 12875  }
 12876  
 12877  var a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck = operand{
 12878  	class: AC_REGLIST4, elemEncoders: []elemEncoder{
 12879  		{encodeZt051, enc_Zt},
 12880  		{encodeArngQCheck, enc_NIL},
 12881  		{encodeZt052, enc_Zt},
 12882  		{encodeArngQCheck, enc_NIL},
 12883  		{encodeZt053, enc_Zt},
 12884  		{encodeArngQCheck, enc_NIL},
 12885  		{encodeZt054, enc_Zt},
 12886  		{encodeArngQCheck, enc_NIL},
 12887  	},
 12888  }
 12889  
 12890  var a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck = operand{
 12891  	class: AC_REGLIST4, elemEncoders: []elemEncoder{
 12892  		{encodeZt051, enc_Zt},
 12893  		{encodeArngSCheck, enc_NIL},
 12894  		{encodeZt052, enc_Zt},
 12895  		{encodeArngSCheck, enc_NIL},
 12896  		{encodeZt053, enc_Zt},
 12897  		{encodeArngSCheck, enc_NIL},
 12898  		{encodeZt054, enc_Zt},
 12899  		{encodeArngSCheck, enc_NIL},
 12900  	},
 12901  }
 12902  
 12903  var a_REGLIST_RANGE_Zd15V1_ArngQCheck_Zd15V2_ArngQCheck = operand{
 12904  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12905  		{encodeZd15V1, enc_Zd},
 12906  		{encodeArngQCheck, enc_NIL},
 12907  		{encodeZd15V2, enc_Zd},
 12908  		{encodeArngQCheck, enc_NIL},
 12909  	},
 12910  }
 12911  
 12912  var a_REGLIST_RANGE_Zda15V1_ArngQCheck_Zda15V2_ArngQCheck = operand{
 12913  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12914  		{encodeZda15V1, enc_Zda},
 12915  		{encodeArngQCheck, enc_NIL},
 12916  		{encodeZda15V2, enc_Zda},
 12917  		{encodeArngQCheck, enc_NIL},
 12918  	},
 12919  }
 12920  
 12921  var a_REGLIST_RANGE_Zdn15V1_ArngBCheck_Zdn15V2_ArngBCheck = operand{
 12922  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12923  		{encodeZdn15V1, enc_Zdn},
 12924  		{encodeArngBCheck, enc_NIL},
 12925  		{encodeZdn15V2, enc_Zdn},
 12926  		{encodeArngBCheck, enc_NIL},
 12927  	},
 12928  }
 12929  
 12930  var a_REGLIST_RANGE_Zdn25V1_ArngBCheck_Zdn25V2_ArngBCheck = operand{
 12931  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12932  		{encodeZdn25V1, enc_Zdn},
 12933  		{encodeArngBCheck, enc_NIL},
 12934  		{encodeZdn25V2, enc_Zdn},
 12935  		{encodeArngBCheck, enc_NIL},
 12936  	},
 12937  }
 12938  
 12939  var a_REGLIST_RANGE_Zn610V1_ArngHCheck_Zn610V2_ArngHCheck = operand{
 12940  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12941  		{encodeZn610V1, enc_Zn},
 12942  		{encodeArngHCheck, enc_NIL},
 12943  		{encodeZn610V2, enc_Zn},
 12944  		{encodeArngHCheck, enc_NIL},
 12945  	},
 12946  }
 12947  
 12948  var a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck = operand{
 12949  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12950  		{encodeZn610V1, enc_Zn},
 12951  		{encodeArngSCheck, enc_NIL},
 12952  		{encodeZn610V2, enc_Zn},
 12953  		{encodeArngSCheck, enc_NIL},
 12954  	},
 12955  }
 12956  
 12957  var a_REGLIST_RANGE_Zn610V1_SizeTbHSD2224Offset1_Zn610V2_SizeTbHSD2224Offset1 = operand{
 12958  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12959  		{encodeZn610V1, enc_Zn},
 12960  		{encodeSizeTbHSD2224Offset1, enc_size},
 12961  		{encodeZn610V2, enc_Zn},
 12962  		{encodeSizeTbHSD2224Offset1, enc_size},
 12963  	},
 12964  }
 12965  
 12966  var a_REGLIST_RANGE_Zn610V1_Tsize1921V2_Zn610V2_Tsize1921V2 = operand{
 12967  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12968  		{encodeZn610V1, enc_Zn},
 12969  		{encodeTsize1921V2, enc_tsize},
 12970  		{encodeZn610V2, enc_Zn},
 12971  		{encodeTsize1921V2, enc_tsize},
 12972  	},
 12973  }
 12974  
 12975  var a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck = operand{
 12976  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12977  		{encodeZt15V1, enc_Zt},
 12978  		{encodeArngBCheck, enc_NIL},
 12979  		{encodeZt15V2, enc_Zt},
 12980  		{encodeArngBCheck, enc_NIL},
 12981  	},
 12982  }
 12983  
 12984  var a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck = operand{
 12985  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12986  		{encodeZt15V1, enc_Zt},
 12987  		{encodeArngDCheck, enc_NIL},
 12988  		{encodeZt15V2, enc_Zt},
 12989  		{encodeArngDCheck, enc_NIL},
 12990  	},
 12991  }
 12992  
 12993  var a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck = operand{
 12994  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 12995  		{encodeZt15V1, enc_Zt},
 12996  		{encodeArngHCheck, enc_NIL},
 12997  		{encodeZt15V2, enc_Zt},
 12998  		{encodeArngHCheck, enc_NIL},
 12999  	},
 13000  }
 13001  
 13002  var a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck = operand{
 13003  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 13004  		{encodeZt15V1, enc_Zt},
 13005  		{encodeArngSCheck, enc_NIL},
 13006  		{encodeZt15V2, enc_Zt},
 13007  		{encodeArngSCheck, enc_NIL},
 13008  	},
 13009  }
 13010  
 13011  var a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck = operand{
 13012  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 13013  		{encodeZt25V1, enc_Zt},
 13014  		{encodeArngBCheck, enc_NIL},
 13015  		{encodeZt25V2, enc_Zt},
 13016  		{encodeArngBCheck, enc_NIL},
 13017  	},
 13018  }
 13019  
 13020  var a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck = operand{
 13021  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 13022  		{encodeZt25V1, enc_Zt},
 13023  		{encodeArngDCheck, enc_NIL},
 13024  		{encodeZt25V2, enc_Zt},
 13025  		{encodeArngDCheck, enc_NIL},
 13026  	},
 13027  }
 13028  
 13029  var a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck = operand{
 13030  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 13031  		{encodeZt25V1, enc_Zt},
 13032  		{encodeArngHCheck, enc_NIL},
 13033  		{encodeZt25V2, enc_Zt},
 13034  		{encodeArngHCheck, enc_NIL},
 13035  	},
 13036  }
 13037  
 13038  var a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck = operand{
 13039  	class: AC_REGLIST_RANGE, elemEncoders: []elemEncoder{
 13040  		{encodeZt25V1, enc_Zt},
 13041  		{encodeArngSCheck, enc_NIL},
 13042  		{encodeZt25V2, enc_Zt},
 13043  		{encodeArngSCheck, enc_NIL},
 13044  	},
 13045  }
 13046  
 13047  var a_SPECIAL_Prfop04 = operand{
 13048  	class: AC_SPECIAL, elemEncoders: []elemEncoder{
 13049  		{encodePrfop04, enc_prfop},
 13050  	},
 13051  }
 13052  
 13053  var a_SPECIAL_Vl1011 = operand{
 13054  	class: AC_SPECIAL, elemEncoders: []elemEncoder{
 13055  		{encodeVl1011, enc_vl},
 13056  	},
 13057  }
 13058  
 13059  var a_SPECIAL_Vl1314 = operand{
 13060  	class: AC_SPECIAL, elemEncoders: []elemEncoder{
 13061  		{encodeVl1314, enc_vl},
 13062  	},
 13063  }
 13064  
 13065  var a_SPZGREG_Noop_Rd05 = operand{
 13066  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13067  		{encodeNoop, enc_NIL},
 13068  		{encodeRd05, enc_Rd},
 13069  	},
 13070  }
 13071  
 13072  var a_SPZGREG_Noop_Rd05ZR = operand{
 13073  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13074  		{encodeNoop, enc_NIL},
 13075  		{encodeRd05ZR, enc_Rd},
 13076  	},
 13077  }
 13078  
 13079  var a_SPZGREG_Noop_Rdn05ZR = operand{
 13080  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13081  		{encodeNoop, enc_NIL},
 13082  		{encodeRdn05ZR, enc_Rdn},
 13083  	},
 13084  }
 13085  
 13086  var a_SPZGREG_Noop_Rm1621V1 = operand{
 13087  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13088  		{encodeNoop, enc_NIL},
 13089  		{encodeRm1621V1, enc_Rm},
 13090  	},
 13091  }
 13092  
 13093  var a_SPZGREG_Noop_Rm1621ZR = operand{
 13094  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13095  		{encodeNoop, enc_NIL},
 13096  		{encodeRm1621ZR, enc_Rm},
 13097  	},
 13098  }
 13099  
 13100  var a_SPZGREG_Noop_Rm510ZR = operand{
 13101  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13102  		{encodeNoop, enc_NIL},
 13103  		{encodeRm510ZR, enc_Rm},
 13104  	},
 13105  }
 13106  
 13107  var a_SPZGREG_Noop_Rn510 = operand{
 13108  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13109  		{encodeNoop, enc_NIL},
 13110  		{encodeRn510, enc_Rn},
 13111  	},
 13112  }
 13113  
 13114  var a_SPZGREG_Noop_Rn510SPV1 = operand{
 13115  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13116  		{encodeNoop, enc_NIL},
 13117  		{encodeRn510SPV1, enc_Rn},
 13118  	},
 13119  }
 13120  
 13121  var a_SPZGREG_Noop_Rn510ZR = operand{
 13122  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13123  		{encodeNoop, enc_NIL},
 13124  		{encodeRn510ZR, enc_Rn},
 13125  	},
 13126  }
 13127  
 13128  var a_SPZGREG_Noop_Wdn05 = operand{
 13129  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13130  		{encodeNoop, enc_NIL},
 13131  		{encodeWdn05, enc_Rdn},
 13132  	},
 13133  }
 13134  
 13135  var a_SPZGREG_Noop_Xdn05 = operand{
 13136  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13137  		{encodeNoop, enc_NIL},
 13138  		{encodeXdn05, enc_Rdn},
 13139  	},
 13140  }
 13141  
 13142  var a_SPZGREG_XCheck_Rd05_SPAllowed = operand{
 13143  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13144  		{encodeXCheck, enc_NIL},
 13145  		{encodeRd05_SPAllowed, enc_Rd},
 13146  	},
 13147  }
 13148  
 13149  var a_SPZGREG_XCheck_Rn1621_SPAllowed = operand{
 13150  	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 13151  		{encodeXCheck, enc_NIL},
 13152  		{encodeRn1621_SPAllowed, enc_Rn},
 13153  	},
 13154  }
 13155  
 13156  var a_VREG_Noop_Vd05 = operand{
 13157  	class: AC_VREG, elemEncoders: []elemEncoder{
 13158  		{encodeNoop, enc_NIL},
 13159  		{encodeVd05, enc_Vd},
 13160  	},
 13161  }
 13162  
 13163  var a_VREG_Noop_Vd0564 = operand{
 13164  	class: AC_VREG, elemEncoders: []elemEncoder{
 13165  		{encodeNoop, enc_NIL},
 13166  		{encodeVd0564, enc_Vd},
 13167  	},
 13168  }
 13169  
 13170  var a_VREG_Noop_Vdn05 = operand{
 13171  	class: AC_VREG, elemEncoders: []elemEncoder{
 13172  		{encodeNoop, enc_NIL},
 13173  		{encodeVdn05, enc_Vdn},
 13174  	},
 13175  }
 13176  
 13177  var a_VREG_Noop_Vm510 = operand{
 13178  	class: AC_VREG, elemEncoders: []elemEncoder{
 13179  		{encodeNoop, enc_NIL},
 13180  		{encodeVm510, enc_Vm},
 13181  	},
 13182  }
 13183  
 13184  var a_VREG_Noop_Vn510 = operand{
 13185  	class: AC_VREG, elemEncoders: []elemEncoder{
 13186  		{encodeNoop, enc_NIL},
 13187  		{encodeVn510, enc_Vn},
 13188  	},
 13189  }
 13190  
 13191  var a_ZREGIDX_Zd_Noop_I1_1718_Halfword = operand{
 13192  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13193  		{encodeZd, enc_Zd},
 13194  		{encodeNoop, enc_NIL},
 13195  		{encodeI1_1718_Halfword, enc_i1},
 13196  	},
 13197  }
 13198  
 13199  var a_ZREGIDX_Zd_Noop_I2_1719_Word = operand{
 13200  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13201  		{encodeZd, enc_Zd},
 13202  		{encodeNoop, enc_NIL},
 13203  		{encodeI2_1719_Word, enc_i2},
 13204  	},
 13205  }
 13206  
 13207  var a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword = operand{
 13208  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13209  		{encodeZd, enc_Zd},
 13210  		{encodeNoop, enc_NIL},
 13211  		{encodeI3hI3l_1722_Doubleword, enc_i3h_i3l},
 13212  	},
 13213  }
 13214  
 13215  var a_ZREGIDX_Zm1621V1_Noop_I12324 = operand{
 13216  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13217  		{encodeZm1621V1, enc_Zm},
 13218  		{encodeNoop, enc_NIL},
 13219  		{encodeI12324, enc_i1},
 13220  	},
 13221  }
 13222  
 13223  var a_ZREGIDX_Zm1621V1_Noop_I12324B = operand{
 13224  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13225  		{encodeZm1621V1, enc_Zm},
 13226  		{encodeNoop, enc_NIL},
 13227  		{encodeI12324B, enc_i1},
 13228  	},
 13229  }
 13230  
 13231  var a_ZREGIDX_Zm1621V1_Noop_I22224 = operand{
 13232  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13233  		{encodeZm1621V1, enc_Zm},
 13234  		{encodeNoop, enc_NIL},
 13235  		{encodeI22224, enc_i2},
 13236  	},
 13237  }
 13238  
 13239  var a_ZREGIDX_Zm1621V1_Noop_I22224HW = operand{
 13240  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13241  		{encodeZm1621V1, enc_Zm},
 13242  		{encodeNoop, enc_NIL},
 13243  		{encodeI22224HW, enc_i2},
 13244  	},
 13245  }
 13246  
 13247  var a_ZREGIDX_Zm1621V1_Noop_I3224I31213 = operand{
 13248  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13249  		{encodeZm1621V1, enc_Zm},
 13250  		{encodeNoop, enc_NIL},
 13251  		{encodeI3224I31213, enc_i3h_i3l},
 13252  	},
 13253  }
 13254  
 13255  var a_ZREGIDX_Zn510Src_Noop_I1_1718_Halfword = operand{
 13256  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13257  		{encodeZn510Src, enc_Zn},
 13258  		{encodeNoop, enc_NIL},
 13259  		{encodeI1_1718_Halfword, enc_i1},
 13260  	},
 13261  }
 13262  
 13263  var a_ZREGIDX_Zn510Src_Noop_I2_1719_Word = operand{
 13264  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13265  		{encodeZn510Src, enc_Zn},
 13266  		{encodeNoop, enc_NIL},
 13267  		{encodeI2_1719_Word, enc_i2},
 13268  	},
 13269  }
 13270  
 13271  var a_ZREGIDX_Zn510Src_Noop_I3hI3l_1722_Doubleword = operand{
 13272  	class: AC_ZREGIDX, elemEncoders: []elemEncoder{
 13273  		{encodeZn510Src, enc_Zn},
 13274  		{encodeNoop, enc_NIL},
 13275  		{encodeI3hI3l_1722_Doubleword, enc_i3h_i3l},
 13276  	},
 13277  }
 13278  
 13279  var a_ZREG_Zd_Noop = operand{
 13280  	class: AC_ZREG, elemEncoders: []elemEncoder{
 13281  		{encodeZd, enc_Zd},
 13282  		{encodeNoop, enc_NIL},
 13283  	},
 13284  }
 13285  
 13286  var a_ZREG_Zm1621V1_Noop = operand{
 13287  	class: AC_ZREG, elemEncoders: []elemEncoder{
 13288  		{encodeZm1621V1, enc_Zm},
 13289  		{encodeNoop, enc_NIL},
 13290  	},
 13291  }
 13292  
 13293  var a_ZREG_Zn510Src_Noop = operand{
 13294  	class: AC_ZREG, elemEncoders: []elemEncoder{
 13295  		{encodeZn510Src, enc_Zn},
 13296  		{encodeNoop, enc_NIL},
 13297  	},
 13298  }
 13299  
 13300  var a_ZREG_Zt05_Noop = operand{
 13301  	class: AC_ZREG, elemEncoders: []elemEncoder{
 13302  		{encodeZt05, enc_Zt},
 13303  		{encodeNoop, enc_NIL},
 13304  	},
 13305  }
 13306  
 13307  var PNd_T = []operand{
 13308  	a_ARNG_PNd_SizeBHSD2224,
 13309  }
 13310  
 13311  var PNn_imm___Pd_T = []operand{
 13312  	a_PREGIDX_PnN_58_Noop_Imm2_810,
 13313  	a_ARNG_Pd_SizeBHSD2224,
 13314  }
 13315  
 13316  var PNn_imm____Pd1_T__Pd2_T_ = []operand{
 13317  	a_PREGIDX_PnN_58_Noop_I189,
 13318  	a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224,
 13319  }
 13320  
 13321  var Pd_B = []operand{
 13322  	a_ARNG_Pd_ArngBCheck,
 13323  }
 13324  
 13325  var Pdm_B__Pn_B__PgZ__Pdm_B = []operand{
 13326  	a_ARNG_PdmDest_ArngBCheck,
 13327  	a_ARNG_Pn59_ArngBCheck,
 13328  	a_PREGZM_Pg1014_ZeroPredCheck,
 13329  	a_ARNG_PdmDest_ArngBCheck,
 13330  }
 13331  
 13332  var Pdn_B__Pg__Pdn_B = []operand{
 13333  	a_ARNG_PdnSrcDst_ArngBCheck,
 13334  	a_PREG_Pg59_Noop,
 13335  	a_ARNG_PdnSrcDst_ArngBCheck,
 13336  }
 13337  
 13338  var Pdn_T__Pv__Pdn_T = []operand{
 13339  	a_ARNG_PdnDest_SizeBHSD2224,
 13340  	a_PREG_Pv59_Noop,
 13341  	a_ARNG_PdnDest_SizeBHSD2224,
 13342  }
 13343  
 13344  var PgZ__Pd_B = []operand{
 13345  	a_PREGZM_Pg59_ZeroPredCheck,
 13346  	a_ARNG_Pd_ArngBCheck,
 13347  }
 13348  
 13349  var Pm_B__Pn_B__PgZ__Pd_B = []operand{
 13350  	a_ARNG_Pm1620_ArngBCheck,
 13351  	a_ARNG_Pn59_ArngBCheck,
 13352  	a_PREGZM_Pg1014_ZeroPredCheck,
 13353  	a_ARNG_Pd_ArngBCheck,
 13354  }
 13355  
 13356  var Pm_B__Pn_B__Pg__Pd_B = []operand{
 13357  	a_ARNG_Pm1620_ArngBCheck,
 13358  	a_ARNG_Pn59_ArngBCheck,
 13359  	a_PREG_Pg1014_Noop,
 13360  	a_ARNG_Pd_ArngBCheck,
 13361  }
 13362  
 13363  var Pm_T__Pn_T__Pd_T = []operand{
 13364  	a_ARNG_Pm1620_SizeBHSD2224,
 13365  	a_ARNG_Pn59_SizeBHSD2224,
 13366  	a_ARNG_Pd_SizeBHSD2224,
 13367  }
 13368  
 13369  var Pm_T__Wdn = []operand{
 13370  	a_ARNG_Pm59V1_SizeBHSD2224,
 13371  	a_SPZGREG_Noop_Wdn05,
 13372  }
 13373  
 13374  var Pm_T__Xdn = []operand{
 13375  	a_ARNG_Pm59V1_SizeBHSD2224,
 13376  	a_SPZGREG_Noop_Xdn05,
 13377  }
 13378  
 13379  var Pm_T__Zdn_T = []operand{
 13380  	a_ARNG_Pm59V1_SizeHSD2224,
 13381  	a_ARNG_ZdnSrcDst_SizeHSD2224,
 13382  }
 13383  
 13384  var Pn_B = []operand{
 13385  	a_ARNG_Pn59V2_ArngBCheck,
 13386  }
 13387  
 13388  var Pn_B__Pd_H = []operand{
 13389  	a_ARNG_Pn59V2_ArngBCheck,
 13390  	a_ARNG_Pd_ArngHCheck,
 13391  }
 13392  
 13393  var Pn_B__Pg = []operand{
 13394  	a_ARNG_Pn59V2_ArngBCheck,
 13395  	a_PREG_Pg1014_Noop,
 13396  }
 13397  
 13398  var Pn_B__PgZM__Pd_B = []operand{
 13399  	a_ARNG_Pn59V2_ArngBCheck,
 13400  	a_PREGZM_Pg1014_PredQualM45,
 13401  	a_ARNG_Pd_ArngBCheck,
 13402  }
 13403  
 13404  var Pn_B__PgZ__Pd_B = []operand{
 13405  	a_ARNG_Pn59V2_ArngBCheck,
 13406  	a_PREGZM_Pg1014_ZeroPredCheck,
 13407  	a_ARNG_Pd_ArngBCheck,
 13408  }
 13409  
 13410  var Pn_B__Zd = []operand{
 13411  	a_ARNG_Pn59V2_ArngBCheck,
 13412  	a_ZREG_Zd_Noop,
 13413  }
 13414  
 13415  var Pn_D__Zd_imm_ = []operand{
 13416  	a_ARNG_Pn59V2_ArngDCheck,
 13417  	a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword,
 13418  }
 13419  
 13420  var Pn_H__Zd_imm_ = []operand{
 13421  	a_ARNG_Pn59V2_ArngHCheck,
 13422  	a_ZREGIDX_Zd_Noop_I1_1718_Halfword,
 13423  }
 13424  
 13425  var Pn_S__Zd_imm_ = []operand{
 13426  	a_ARNG_Pn59V2_ArngSCheck,
 13427  	a_ZREGIDX_Zd_Noop_I2_1719_Word,
 13428  }
 13429  
 13430  var Pn_T__Pd_T = []operand{
 13431  	a_ARNG_Pn59V2_SizeBHSD2224,
 13432  	a_ARNG_Pd_SizeBHSD2224,
 13433  }
 13434  
 13435  var Pn_T__Pg__Xd = []operand{
 13436  	a_ARNG_Pn59V2_SizeBHSD2224,
 13437  	a_PREG_Pg1014_Noop,
 13438  	a_SPZGREG_Noop_Rd05,
 13439  }
 13440  
 13441  var Rm__Rn = []operand{
 13442  	a_SPZGREG_Noop_Rm1621ZR,
 13443  	a_SPZGREG_Noop_Rn510ZR,
 13444  }
 13445  
 13446  var Rm__Rn__Pd_T = []operand{
 13447  	a_SPZGREG_Noop_Rm1621ZR,
 13448  	a_SPZGREG_Noop_Rn510ZR,
 13449  	a_ARNG_Pd_SizeBHSD2224,
 13450  }
 13451  
 13452  var Rm__Rn__Zd_T = []operand{
 13453  	a_SPZGREG_Noop_Rm1621ZR,
 13454  	a_SPZGREG_Noop_Rn510ZR,
 13455  	a_ARNG_Zd_SizeBHSD2224,
 13456  }
 13457  
 13458  var Rm__Zdn_T = []operand{
 13459  	a_SPZGREG_Noop_Rm510ZR,
 13460  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 13461  }
 13462  
 13463  var Rm__cimm__Zd_T = []operand{
 13464  	a_SPZGREG_Noop_Rm1621ZR,
 13465  	a_IMM_Imm5Signed510Unique,
 13466  	a_ARNG_Zd_SizeBHSD2224,
 13467  }
 13468  
 13469  var RnSP__PgM__Zd_T = []operand{
 13470  	a_SPZGREG_Noop_Rn510SPV1,
 13471  	a_PREGZM_Pg1013_MergePredCheck,
 13472  	a_ARNG_Zd_SizeBHSD2224,
 13473  }
 13474  
 13475  var RnSP__Zd_T = []operand{
 13476  	a_SPZGREG_Noop_Rn510SPV1,
 13477  	a_ARNG_Zd_SizeBHSD2224,
 13478  }
 13479  
 13480  var Vm__Zdn_T = []operand{
 13481  	a_VREG_Noop_Vm510,
 13482  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 13483  }
 13484  
 13485  var Vn__PgM__Zd_T = []operand{
 13486  	a_VREG_Noop_Vn510,
 13487  	a_PREGZM_Pg1013_MergePredCheck,
 13488  	a_ARNG_Zd_SizeBHSD2224,
 13489  }
 13490  
 13491  var Wdn__Pm_T__Xdn = []operand{
 13492  	a_SPZGREG_Noop_Wdn05,
 13493  	a_ARNG_Pm59V1_SizeBHSD2224,
 13494  	a_SPZGREG_Noop_Xdn05,
 13495  }
 13496  
 13497  var Xm__Xn__Pd_T = []operand{
 13498  	a_SPZGREG_Noop_Rm1621V1,
 13499  	a_SPZGREG_Noop_Rn510,
 13500  	a_ARNG_Pd_SizeBHSD2224,
 13501  }
 13502  
 13503  var Xm__Xn___Pd1_T__Pd2_T_ = []operand{
 13504  	a_SPZGREG_Noop_Rm1621V1,
 13505  	a_SPZGREG_Noop_Rn510,
 13506  	a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224,
 13507  }
 13508  
 13509  var XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt2_H_ = []operand{
 13510  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13511  	a_PREGZM_PNg1013_ZeroPredCheck,
 13512  	a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck,
 13513  }
 13514  
 13515  var XnSP__Xm__LSL_c1___PNgZ___Zt1_H_Zt4_H_ = []operand{
 13516  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13517  	a_PREGZM_PNg1013_ZeroPredCheck,
 13518  	a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck,
 13519  }
 13520  
 13521  var XnSP__Xm__LSL_c1___PNg___Zt1_H_Zt2_H_ = []operand{
 13522  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13523  	a_PREG_PNg1013_Noop,
 13524  	a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck,
 13525  }
 13526  
 13527  var XnSP__Xm__LSL_c1___PNg___Zt1_H_Zt4_H_ = []operand{
 13528  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13529  	a_PREG_PNg1013_Noop,
 13530  	a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck,
 13531  }
 13532  
 13533  var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_ = []operand{
 13534  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13535  	a_PREGZM_Pg1013_ZeroPredCheck,
 13536  	a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
 13537  }
 13538  
 13539  var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_ = []operand{
 13540  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13541  	a_PREGZM_Pg1013_ZeroPredCheck,
 13542  	a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
 13543  }
 13544  
 13545  var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
 13546  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13547  	a_PREGZM_Pg1013_ZeroPredCheck,
 13548  	a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
 13549  }
 13550  
 13551  var XnSP__Xm__LSL_c1___PgZ___Zt_D_ = []operand{
 13552  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13553  	a_PREGZM_Pg1013_ZeroPredCheck,
 13554  	a_REGLIST1_Zt05_ArngDCheck,
 13555  }
 13556  
 13557  var XnSP__Xm__LSL_c1___PgZ___Zt_D__V2 = []operand{
 13558  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check,
 13559  	a_PREGZM_Pg1013_ZeroPredCheck,
 13560  	a_REGLIST1_Zt05_ArngDCheck,
 13561  }
 13562  
 13563  var XnSP__Xm__LSL_c1___PgZ___Zt_H_ = []operand{
 13564  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13565  	a_PREGZM_Pg1013_ZeroPredCheck,
 13566  	a_REGLIST1_Zt05_ArngHCheck,
 13567  }
 13568  
 13569  var XnSP__Xm__LSL_c1___PgZ___Zt_H__V2 = []operand{
 13570  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check,
 13571  	a_PREGZM_Pg1013_ZeroPredCheck,
 13572  	a_REGLIST1_Zt05_ArngHCheck,
 13573  }
 13574  
 13575  var XnSP__Xm__LSL_c1___PgZ___Zt_S_ = []operand{
 13576  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13577  	a_PREGZM_Pg1013_ZeroPredCheck,
 13578  	a_REGLIST1_Zt05_ArngSCheck,
 13579  }
 13580  
 13581  var XnSP__Xm__LSL_c1___PgZ___Zt_S__V2 = []operand{
 13582  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check,
 13583  	a_PREGZM_Pg1013_ZeroPredCheck,
 13584  	a_REGLIST1_Zt05_ArngSCheck,
 13585  }
 13586  
 13587  var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H_ = []operand{
 13588  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13589  	a_PREG_Pg1013_Noop,
 13590  	a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
 13591  }
 13592  
 13593  var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H_ = []operand{
 13594  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13595  	a_PREG_Pg1013_Noop,
 13596  	a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
 13597  }
 13598  
 13599  var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
 13600  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13601  	a_PREG_Pg1013_Noop,
 13602  	a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
 13603  }
 13604  
 13605  var XnSP__Xm__LSL_c1___Pg___Zt_H_ = []operand{
 13606  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13607  	a_PREG_Pg1013_Noop,
 13608  	a_REGLIST1_Zt05_ArngHCheck,
 13609  }
 13610  
 13611  var XnSP__Xm__LSL_c1___Pg___Zt_T_ = []operand{
 13612  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13613  	a_PREG_Pg1013_Noop,
 13614  	a_REGLIST1_Zt05_Size2123V2,
 13615  }
 13616  
 13617  var XnSP__Xm__LSL_c1___Pg__prfop = []operand{
 13618  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
 13619  	a_PREG_Pg1013_Noop,
 13620  	a_SPECIAL_Prfop04,
 13621  }
 13622  
 13623  var XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt2_S_ = []operand{
 13624  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13625  	a_PREGZM_PNg1013_ZeroPredCheck,
 13626  	a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck,
 13627  }
 13628  
 13629  var XnSP__Xm__LSL_c2___PNgZ___Zt1_S_Zt4_S_ = []operand{
 13630  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13631  	a_PREGZM_PNg1013_ZeroPredCheck,
 13632  	a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck,
 13633  }
 13634  
 13635  var XnSP__Xm__LSL_c2___PNg___Zt1_S_Zt2_S_ = []operand{
 13636  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13637  	a_PREG_PNg1013_Noop,
 13638  	a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck,
 13639  }
 13640  
 13641  var XnSP__Xm__LSL_c2___PNg___Zt1_S_Zt4_S_ = []operand{
 13642  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13643  	a_PREG_PNg1013_Noop,
 13644  	a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck,
 13645  }
 13646  
 13647  var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_ = []operand{
 13648  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13649  	a_PREGZM_Pg1013_ZeroPredCheck,
 13650  	a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
 13651  }
 13652  
 13653  var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_ = []operand{
 13654  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13655  	a_PREGZM_Pg1013_ZeroPredCheck,
 13656  	a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
 13657  }
 13658  
 13659  var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
 13660  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13661  	a_PREGZM_Pg1013_ZeroPredCheck,
 13662  	a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
 13663  }
 13664  
 13665  var XnSP__Xm__LSL_c2___PgZ___Zt_D_ = []operand{
 13666  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13667  	a_PREGZM_Pg1013_ZeroPredCheck,
 13668  	a_REGLIST1_Zt05_ArngDCheck,
 13669  }
 13670  
 13671  var XnSP__Xm__LSL_c2___PgZ___Zt_D__V2 = []operand{
 13672  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check,
 13673  	a_PREGZM_Pg1013_ZeroPredCheck,
 13674  	a_REGLIST1_Zt05_ArngDCheck,
 13675  }
 13676  
 13677  var XnSP__Xm__LSL_c2___PgZ___Zt_Q_ = []operand{
 13678  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13679  	a_PREGZM_Pg1013_ZeroPredCheck,
 13680  	a_REGLIST1_Zt05_ArngQCheck,
 13681  }
 13682  
 13683  var XnSP__Xm__LSL_c2___PgZ___Zt_S_ = []operand{
 13684  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13685  	a_PREGZM_Pg1013_ZeroPredCheck,
 13686  	a_REGLIST1_Zt05_ArngSCheck,
 13687  }
 13688  
 13689  var XnSP__Xm__LSL_c2___PgZ___Zt_S__V2 = []operand{
 13690  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check,
 13691  	a_PREGZM_Pg1013_ZeroPredCheck,
 13692  	a_REGLIST1_Zt05_ArngSCheck,
 13693  }
 13694  
 13695  var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S_ = []operand{
 13696  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13697  	a_PREG_Pg1013_Noop,
 13698  	a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
 13699  }
 13700  
 13701  var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S_ = []operand{
 13702  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13703  	a_PREG_Pg1013_Noop,
 13704  	a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
 13705  }
 13706  
 13707  var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
 13708  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13709  	a_PREG_Pg1013_Noop,
 13710  	a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
 13711  }
 13712  
 13713  var XnSP__Xm__LSL_c2___Pg___Zt_Q_ = []operand{
 13714  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13715  	a_PREG_Pg1013_Noop,
 13716  	a_REGLIST1_Zt05_ArngQCheck,
 13717  }
 13718  
 13719  var XnSP__Xm__LSL_c2___Pg___Zt_S_ = []operand{
 13720  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13721  	a_PREG_Pg1013_Noop,
 13722  	a_REGLIST1_Zt05_ArngSCheck,
 13723  }
 13724  
 13725  var XnSP__Xm__LSL_c2___Pg___Zt_T_ = []operand{
 13726  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13727  	a_PREG_Pg1013_Noop,
 13728  	a_REGLIST1_Zt05_Sz2122,
 13729  }
 13730  
 13731  var XnSP__Xm__LSL_c2___Pg__prfop = []operand{
 13732  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 13733  	a_PREG_Pg1013_Noop,
 13734  	a_SPECIAL_Prfop04,
 13735  }
 13736  
 13737  var XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt2_D_ = []operand{
 13738  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13739  	a_PREGZM_PNg1013_ZeroPredCheck,
 13740  	a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck,
 13741  }
 13742  
 13743  var XnSP__Xm__LSL_c3___PNgZ___Zt1_D_Zt4_D_ = []operand{
 13744  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13745  	a_PREGZM_PNg1013_ZeroPredCheck,
 13746  	a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck,
 13747  }
 13748  
 13749  var XnSP__Xm__LSL_c3___PNg___Zt1_D_Zt2_D_ = []operand{
 13750  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13751  	a_PREG_PNg1013_Noop,
 13752  	a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck,
 13753  }
 13754  
 13755  var XnSP__Xm__LSL_c3___PNg___Zt1_D_Zt4_D_ = []operand{
 13756  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13757  	a_PREG_PNg1013_Noop,
 13758  	a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck,
 13759  }
 13760  
 13761  var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_ = []operand{
 13762  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13763  	a_PREGZM_Pg1013_ZeroPredCheck,
 13764  	a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
 13765  }
 13766  
 13767  var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_ = []operand{
 13768  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13769  	a_PREGZM_Pg1013_ZeroPredCheck,
 13770  	a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
 13771  }
 13772  
 13773  var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
 13774  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13775  	a_PREGZM_Pg1013_ZeroPredCheck,
 13776  	a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
 13777  }
 13778  
 13779  var XnSP__Xm__LSL_c3___PgZ___Zt_D_ = []operand{
 13780  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13781  	a_PREGZM_Pg1013_ZeroPredCheck,
 13782  	a_REGLIST1_Zt05_ArngDCheck,
 13783  }
 13784  
 13785  var XnSP__Xm__LSL_c3___PgZ___Zt_D__V2 = []operand{
 13786  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check,
 13787  	a_PREGZM_Pg1013_ZeroPredCheck,
 13788  	a_REGLIST1_Zt05_ArngDCheck,
 13789  }
 13790  
 13791  var XnSP__Xm__LSL_c3___PgZ___Zt_Q_ = []operand{
 13792  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13793  	a_PREGZM_Pg1013_ZeroPredCheck,
 13794  	a_REGLIST1_Zt05_ArngQCheck,
 13795  }
 13796  
 13797  var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D_ = []operand{
 13798  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13799  	a_PREG_Pg1013_Noop,
 13800  	a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
 13801  }
 13802  
 13803  var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D_ = []operand{
 13804  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13805  	a_PREG_Pg1013_Noop,
 13806  	a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
 13807  }
 13808  
 13809  var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
 13810  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13811  	a_PREG_Pg1013_Noop,
 13812  	a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
 13813  }
 13814  
 13815  var XnSP__Xm__LSL_c3___Pg___Zt_D_ = []operand{
 13816  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13817  	a_PREG_Pg1013_Noop,
 13818  	a_REGLIST1_Zt05_ArngDCheck,
 13819  }
 13820  
 13821  var XnSP__Xm__LSL_c3___Pg___Zt_Q_ = []operand{
 13822  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13823  	a_PREG_Pg1013_Noop,
 13824  	a_REGLIST1_Zt05_ArngQCheck,
 13825  }
 13826  
 13827  var XnSP__Xm__LSL_c3___Pg__prfop = []operand{
 13828  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 13829  	a_PREG_Pg1013_Noop,
 13830  	a_SPECIAL_Prfop04,
 13831  }
 13832  
 13833  var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_ = []operand{
 13834  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
 13835  	a_PREGZM_Pg1013_ZeroPredCheck,
 13836  	a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
 13837  }
 13838  
 13839  var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
 13840  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
 13841  	a_PREGZM_Pg1013_ZeroPredCheck,
 13842  	a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
 13843  }
 13844  
 13845  var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
 13846  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
 13847  	a_PREGZM_Pg1013_ZeroPredCheck,
 13848  	a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
 13849  }
 13850  
 13851  var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q_ = []operand{
 13852  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
 13853  	a_PREG_Pg1013_Noop,
 13854  	a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
 13855  }
 13856  
 13857  var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
 13858  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
 13859  	a_PREG_Pg1013_Noop,
 13860  	a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
 13861  }
 13862  
 13863  var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
 13864  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
 13865  	a_PREG_Pg1013_Noop,
 13866  	a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
 13867  }
 13868  
 13869  var XnSP__Xm___PNgZ___Zt1_B_Zt2_B_ = []operand{
 13870  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13871  	a_PREGZM_PNg1013_ZeroPredCheck,
 13872  	a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck,
 13873  }
 13874  
 13875  var XnSP__Xm___PNgZ___Zt1_B_Zt4_B_ = []operand{
 13876  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13877  	a_PREGZM_PNg1013_ZeroPredCheck,
 13878  	a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck,
 13879  }
 13880  
 13881  var XnSP__Xm___PNg___Zt1_B_Zt2_B_ = []operand{
 13882  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13883  	a_PREG_PNg1013_Noop,
 13884  	a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck,
 13885  }
 13886  
 13887  var XnSP__Xm___PNg___Zt1_B_Zt4_B_ = []operand{
 13888  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13889  	a_PREG_PNg1013_Noop,
 13890  	a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck,
 13891  }
 13892  
 13893  var XnSP__Xm___PgZ___Zt1_B__Zt2_B_ = []operand{
 13894  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13895  	a_PREGZM_Pg1013_ZeroPredCheck,
 13896  	a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
 13897  }
 13898  
 13899  var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_ = []operand{
 13900  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13901  	a_PREGZM_Pg1013_ZeroPredCheck,
 13902  	a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
 13903  }
 13904  
 13905  var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
 13906  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13907  	a_PREGZM_Pg1013_ZeroPredCheck,
 13908  	a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
 13909  }
 13910  
 13911  var XnSP__Xm___PgZ___Zt_B_ = []operand{
 13912  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13913  	a_PREGZM_Pg1013_ZeroPredCheck,
 13914  	a_REGLIST1_Zt05_ArngBCheck,
 13915  }
 13916  
 13917  var XnSP__Xm___PgZ___Zt_B__V2 = []operand{
 13918  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 13919  	a_PREGZM_Pg1013_ZeroPredCheck,
 13920  	a_REGLIST1_Zt05_ArngBCheck,
 13921  }
 13922  
 13923  var XnSP__Xm___PgZ___Zt_D_ = []operand{
 13924  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13925  	a_PREGZM_Pg1013_ZeroPredCheck,
 13926  	a_REGLIST1_Zt05_ArngDCheck,
 13927  }
 13928  
 13929  var XnSP__Xm___PgZ___Zt_D__V2 = []operand{
 13930  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 13931  	a_PREGZM_Pg1013_ZeroPredCheck,
 13932  	a_REGLIST1_Zt05_ArngDCheck,
 13933  }
 13934  
 13935  var XnSP__Xm___PgZ___Zt_H_ = []operand{
 13936  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13937  	a_PREGZM_Pg1013_ZeroPredCheck,
 13938  	a_REGLIST1_Zt05_ArngHCheck,
 13939  }
 13940  
 13941  var XnSP__Xm___PgZ___Zt_H__V2 = []operand{
 13942  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 13943  	a_PREGZM_Pg1013_ZeroPredCheck,
 13944  	a_REGLIST1_Zt05_ArngHCheck,
 13945  }
 13946  
 13947  var XnSP__Xm___PgZ___Zt_S_ = []operand{
 13948  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13949  	a_PREGZM_Pg1013_ZeroPredCheck,
 13950  	a_REGLIST1_Zt05_ArngSCheck,
 13951  }
 13952  
 13953  var XnSP__Xm___PgZ___Zt_S__V2 = []operand{
 13954  	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 13955  	a_PREGZM_Pg1013_ZeroPredCheck,
 13956  	a_REGLIST1_Zt05_ArngSCheck,
 13957  }
 13958  
 13959  var XnSP__Xm___Pg___Zt1_B__Zt2_B_ = []operand{
 13960  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13961  	a_PREG_Pg1013_Noop,
 13962  	a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
 13963  }
 13964  
 13965  var XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B_ = []operand{
 13966  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13967  	a_PREG_Pg1013_Noop,
 13968  	a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
 13969  }
 13970  
 13971  var XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
 13972  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13973  	a_PREG_Pg1013_Noop,
 13974  	a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
 13975  }
 13976  
 13977  var XnSP__Xm___Pg___Zt_B_ = []operand{
 13978  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13979  	a_PREG_Pg1013_Noop,
 13980  	a_REGLIST1_Zt05_ArngBCheck,
 13981  }
 13982  
 13983  var XnSP__Xm___Pg___Zt_T_ = []operand{
 13984  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13985  	a_PREG_Pg1013_Noop,
 13986  	a_REGLIST1_Zt05_Size2123V1,
 13987  }
 13988  
 13989  var XnSP__Xm___Pg__prfop = []operand{
 13990  	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
 13991  	a_PREG_Pg1013_Noop,
 13992  	a_SPECIAL_Prfop04,
 13993  }
 13994  
 13995  var XnSP__Zm_D__LSL_c1___PgZ___Zt_D_ = []operand{
 13996  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check,
 13997  	a_PREGZM_Pg1013_ZeroPredCheck,
 13998  	a_REGLIST1_Zt05_ArngDCheck,
 13999  }
 14000  
 14001  var XnSP__Zm_D__LSL_c1___Pg___Zt_D_ = []operand{
 14002  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check,
 14003  	a_PREG_Pg1013_Noop,
 14004  	a_REGLIST1_Zt05_ArngDCheck,
 14005  }
 14006  
 14007  var XnSP__Zm_D__LSL_c1___Pg__prfop = []operand{
 14008  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check,
 14009  	a_PREG_Pg1013_Noop,
 14010  	a_SPECIAL_Prfop04,
 14011  }
 14012  
 14013  var XnSP__Zm_D__LSL_c2___PgZ___Zt_D_ = []operand{
 14014  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check,
 14015  	a_PREGZM_Pg1013_ZeroPredCheck,
 14016  	a_REGLIST1_Zt05_ArngDCheck,
 14017  }
 14018  
 14019  var XnSP__Zm_D__LSL_c2___Pg___Zt_D_ = []operand{
 14020  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check,
 14021  	a_PREG_Pg1013_Noop,
 14022  	a_REGLIST1_Zt05_ArngDCheck,
 14023  }
 14024  
 14025  var XnSP__Zm_D__LSL_c2___Pg__prfop = []operand{
 14026  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check,
 14027  	a_PREG_Pg1013_Noop,
 14028  	a_SPECIAL_Prfop04,
 14029  }
 14030  
 14031  var XnSP__Zm_D__LSL_c3___PgZ___Zt_D_ = []operand{
 14032  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check,
 14033  	a_PREGZM_Pg1013_ZeroPredCheck,
 14034  	a_REGLIST1_Zt05_ArngDCheck,
 14035  }
 14036  
 14037  var XnSP__Zm_D__LSL_c3___Pg___Zt_D_ = []operand{
 14038  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check,
 14039  	a_PREG_Pg1013_Noop,
 14040  	a_REGLIST1_Zt05_ArngDCheck,
 14041  }
 14042  
 14043  var XnSP__Zm_D__LSL_c3___Pg__prfop = []operand{
 14044  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check,
 14045  	a_PREG_Pg1013_Noop,
 14046  	a_SPECIAL_Prfop04,
 14047  }
 14048  
 14049  var XnSP__Zm_D___PgZ___Zt_D_ = []operand{
 14050  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck,
 14051  	a_PREGZM_Pg1013_ZeroPredCheck,
 14052  	a_REGLIST1_Zt05_ArngDCheck,
 14053  }
 14054  
 14055  var XnSP__Zm_D___Pg___Zt_D_ = []operand{
 14056  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck,
 14057  	a_PREG_Pg1013_Noop,
 14058  	a_REGLIST1_Zt05_ArngDCheck,
 14059  }
 14060  
 14061  var XnSP__Zm_D___Pg__prfop = []operand{
 14062  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck,
 14063  	a_PREG_Pg1013_Noop,
 14064  	a_SPECIAL_Prfop04,
 14065  }
 14066  
 14067  var XnSP__Zm_D__mod___PgZ___Zt_D_ = []operand{
 14068  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck,
 14069  	a_PREGZM_Pg1013_ZeroPredCheck,
 14070  	a_REGLIST1_Zt05_ArngDCheck,
 14071  }
 14072  
 14073  var XnSP__Zm_D__mod___Pg___Zt_D_ = []operand{
 14074  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck,
 14075  	a_PREG_Pg1013_Noop,
 14076  	a_REGLIST1_Zt05_ArngDCheck,
 14077  }
 14078  
 14079  var XnSP__Zm_D__mod___Pg__prfop = []operand{
 14080  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck,
 14081  	a_PREG_Pg1013_Noop,
 14082  	a_SPECIAL_Prfop04,
 14083  }
 14084  
 14085  var XnSP__Zm_D__mod_c1___PgZ___Zt_D_ = []operand{
 14086  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check,
 14087  	a_PREGZM_Pg1013_ZeroPredCheck,
 14088  	a_REGLIST1_Zt05_ArngDCheck,
 14089  }
 14090  
 14091  var XnSP__Zm_D__mod_c1___Pg___Zt_D_ = []operand{
 14092  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check,
 14093  	a_PREG_Pg1013_Noop,
 14094  	a_REGLIST1_Zt05_ArngDCheck,
 14095  }
 14096  
 14097  var XnSP__Zm_D__mod_c1___Pg__prfop = []operand{
 14098  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check,
 14099  	a_PREG_Pg1013_Noop,
 14100  	a_SPECIAL_Prfop04,
 14101  }
 14102  
 14103  var XnSP__Zm_D__mod_c2___PgZ___Zt_D_ = []operand{
 14104  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check,
 14105  	a_PREGZM_Pg1013_ZeroPredCheck,
 14106  	a_REGLIST1_Zt05_ArngDCheck,
 14107  }
 14108  
 14109  var XnSP__Zm_D__mod_c2___Pg___Zt_D_ = []operand{
 14110  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check,
 14111  	a_PREG_Pg1013_Noop,
 14112  	a_REGLIST1_Zt05_ArngDCheck,
 14113  }
 14114  
 14115  var XnSP__Zm_D__mod_c2___Pg__prfop = []operand{
 14116  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check,
 14117  	a_PREG_Pg1013_Noop,
 14118  	a_SPECIAL_Prfop04,
 14119  }
 14120  
 14121  var XnSP__Zm_D__mod_c3___PgZ___Zt_D_ = []operand{
 14122  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check,
 14123  	a_PREGZM_Pg1013_ZeroPredCheck,
 14124  	a_REGLIST1_Zt05_ArngDCheck,
 14125  }
 14126  
 14127  var XnSP__Zm_D__mod_c3___Pg___Zt_D_ = []operand{
 14128  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check,
 14129  	a_PREG_Pg1013_Noop,
 14130  	a_REGLIST1_Zt05_ArngDCheck,
 14131  }
 14132  
 14133  var XnSP__Zm_D__mod_c3___Pg__prfop = []operand{
 14134  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check,
 14135  	a_PREG_Pg1013_Noop,
 14136  	a_SPECIAL_Prfop04,
 14137  }
 14138  
 14139  var XnSP__Zm_S__mod___PgZ___Zt_S_ = []operand{
 14140  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck,
 14141  	a_PREGZM_Pg1013_ZeroPredCheck,
 14142  	a_REGLIST1_Zt05_ArngSCheck,
 14143  }
 14144  
 14145  var XnSP__Zm_S__mod___Pg___Zt_S_ = []operand{
 14146  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck,
 14147  	a_PREG_Pg1013_Noop,
 14148  	a_REGLIST1_Zt05_ArngSCheck,
 14149  }
 14150  
 14151  var XnSP__Zm_S__mod___Pg__prfop = []operand{
 14152  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck,
 14153  	a_PREG_Pg1013_Noop,
 14154  	a_SPECIAL_Prfop04,
 14155  }
 14156  
 14157  var XnSP__Zm_S__mod_c1___PgZ___Zt_S_ = []operand{
 14158  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check,
 14159  	a_PREGZM_Pg1013_ZeroPredCheck,
 14160  	a_REGLIST1_Zt05_ArngSCheck,
 14161  }
 14162  
 14163  var XnSP__Zm_S__mod_c1___Pg___Zt_S_ = []operand{
 14164  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check,
 14165  	a_PREG_Pg1013_Noop,
 14166  	a_REGLIST1_Zt05_ArngSCheck,
 14167  }
 14168  
 14169  var XnSP__Zm_S__mod_c1___Pg__prfop = []operand{
 14170  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check,
 14171  	a_PREG_Pg1013_Noop,
 14172  	a_SPECIAL_Prfop04,
 14173  }
 14174  
 14175  var XnSP__Zm_S__mod_c2___PgZ___Zt_S_ = []operand{
 14176  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check,
 14177  	a_PREGZM_Pg1013_ZeroPredCheck,
 14178  	a_REGLIST1_Zt05_ArngSCheck,
 14179  }
 14180  
 14181  var XnSP__Zm_S__mod_c2___Pg___Zt_S_ = []operand{
 14182  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check,
 14183  	a_PREG_Pg1013_Noop,
 14184  	a_REGLIST1_Zt05_ArngSCheck,
 14185  }
 14186  
 14187  var XnSP__Zm_S__mod_c2___Pg__prfop = []operand{
 14188  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check,
 14189  	a_PREG_Pg1013_Noop,
 14190  	a_SPECIAL_Prfop04,
 14191  }
 14192  
 14193  var XnSP__Zm_S__mod_c3___Pg__prfop = []operand{
 14194  	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt3Check,
 14195  	a_PREG_Pg1013_Noop,
 14196  	a_SPECIAL_Prfop04,
 14197  }
 14198  
 14199  var XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt2_B_ = []operand{
 14200  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14201  	a_PREGZM_PNg1013_ZeroPredCheck,
 14202  	a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck,
 14203  }
 14204  
 14205  var XnSP__cimm__MUL_VL___PNgZ___Zt1_B_Zt4_B_ = []operand{
 14206  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14207  	a_PREGZM_PNg1013_ZeroPredCheck,
 14208  	a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck,
 14209  }
 14210  
 14211  var XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt2_D_ = []operand{
 14212  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14213  	a_PREGZM_PNg1013_ZeroPredCheck,
 14214  	a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck,
 14215  }
 14216  
 14217  var XnSP__cimm__MUL_VL___PNgZ___Zt1_D_Zt4_D_ = []operand{
 14218  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14219  	a_PREGZM_PNg1013_ZeroPredCheck,
 14220  	a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck,
 14221  }
 14222  
 14223  var XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt2_H_ = []operand{
 14224  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14225  	a_PREGZM_PNg1013_ZeroPredCheck,
 14226  	a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck,
 14227  }
 14228  
 14229  var XnSP__cimm__MUL_VL___PNgZ___Zt1_H_Zt4_H_ = []operand{
 14230  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14231  	a_PREGZM_PNg1013_ZeroPredCheck,
 14232  	a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck,
 14233  }
 14234  
 14235  var XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt2_S_ = []operand{
 14236  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14237  	a_PREGZM_PNg1013_ZeroPredCheck,
 14238  	a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck,
 14239  }
 14240  
 14241  var XnSP__cimm__MUL_VL___PNgZ___Zt1_S_Zt4_S_ = []operand{
 14242  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14243  	a_PREGZM_PNg1013_ZeroPredCheck,
 14244  	a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck,
 14245  }
 14246  
 14247  var XnSP__cimm__MUL_VL___PNg___Zt1_B_Zt2_B_ = []operand{
 14248  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14249  	a_PREG_PNg1013_Noop,
 14250  	a_REGLIST_RANGE_Zt15V1_ArngBCheck_Zt15V2_ArngBCheck,
 14251  }
 14252  
 14253  var XnSP__cimm__MUL_VL___PNg___Zt1_B_Zt4_B_ = []operand{
 14254  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14255  	a_PREG_PNg1013_Noop,
 14256  	a_REGLIST_RANGE_Zt25V1_ArngBCheck_Zt25V2_ArngBCheck,
 14257  }
 14258  
 14259  var XnSP__cimm__MUL_VL___PNg___Zt1_D_Zt2_D_ = []operand{
 14260  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14261  	a_PREG_PNg1013_Noop,
 14262  	a_REGLIST_RANGE_Zt15V1_ArngDCheck_Zt15V2_ArngDCheck,
 14263  }
 14264  
 14265  var XnSP__cimm__MUL_VL___PNg___Zt1_D_Zt4_D_ = []operand{
 14266  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14267  	a_PREG_PNg1013_Noop,
 14268  	a_REGLIST_RANGE_Zt25V1_ArngDCheck_Zt25V2_ArngDCheck,
 14269  }
 14270  
 14271  var XnSP__cimm__MUL_VL___PNg___Zt1_H_Zt2_H_ = []operand{
 14272  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14273  	a_PREG_PNg1013_Noop,
 14274  	a_REGLIST_RANGE_Zt15V1_ArngHCheck_Zt15V2_ArngHCheck,
 14275  }
 14276  
 14277  var XnSP__cimm__MUL_VL___PNg___Zt1_H_Zt4_H_ = []operand{
 14278  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14279  	a_PREG_PNg1013_Noop,
 14280  	a_REGLIST_RANGE_Zt25V1_ArngHCheck_Zt25V2_ArngHCheck,
 14281  }
 14282  
 14283  var XnSP__cimm__MUL_VL___PNg___Zt1_S_Zt2_S_ = []operand{
 14284  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V9,
 14285  	a_PREG_PNg1013_Noop,
 14286  	a_REGLIST_RANGE_Zt15V1_ArngSCheck_Zt15V2_ArngSCheck,
 14287  }
 14288  
 14289  var XnSP__cimm__MUL_VL___PNg___Zt1_S_Zt4_S_ = []operand{
 14290  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V8,
 14291  	a_PREG_PNg1013_Noop,
 14292  	a_REGLIST_RANGE_Zt25V1_ArngSCheck_Zt25V2_ArngSCheck,
 14293  }
 14294  
 14295  var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B_ = []operand{
 14296  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14297  	a_PREGZM_Pg1013_ZeroPredCheck,
 14298  	a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
 14299  }
 14300  
 14301  var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B_ = []operand{
 14302  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14303  	a_PREGZM_Pg1013_ZeroPredCheck,
 14304  	a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
 14305  }
 14306  
 14307  var XnSP__cimm__MUL_VL___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
 14308  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14309  	a_PREGZM_Pg1013_ZeroPredCheck,
 14310  	a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
 14311  }
 14312  
 14313  var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D_ = []operand{
 14314  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14315  	a_PREGZM_Pg1013_ZeroPredCheck,
 14316  	a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
 14317  }
 14318  
 14319  var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D_ = []operand{
 14320  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14321  	a_PREGZM_Pg1013_ZeroPredCheck,
 14322  	a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
 14323  }
 14324  
 14325  var XnSP__cimm__MUL_VL___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
 14326  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14327  	a_PREGZM_Pg1013_ZeroPredCheck,
 14328  	a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
 14329  }
 14330  
 14331  var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H_ = []operand{
 14332  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14333  	a_PREGZM_Pg1013_ZeroPredCheck,
 14334  	a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
 14335  }
 14336  
 14337  var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H_ = []operand{
 14338  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14339  	a_PREGZM_Pg1013_ZeroPredCheck,
 14340  	a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
 14341  }
 14342  
 14343  var XnSP__cimm__MUL_VL___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
 14344  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14345  	a_PREGZM_Pg1013_ZeroPredCheck,
 14346  	a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
 14347  }
 14348  
 14349  var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q_ = []operand{
 14350  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14351  	a_PREGZM_Pg1013_ZeroPredCheck,
 14352  	a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
 14353  }
 14354  
 14355  var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
 14356  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14357  	a_PREGZM_Pg1013_ZeroPredCheck,
 14358  	a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
 14359  }
 14360  
 14361  var XnSP__cimm__MUL_VL___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
 14362  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14363  	a_PREGZM_Pg1013_ZeroPredCheck,
 14364  	a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
 14365  }
 14366  
 14367  var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S_ = []operand{
 14368  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14369  	a_PREGZM_Pg1013_ZeroPredCheck,
 14370  	a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
 14371  }
 14372  
 14373  var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S_ = []operand{
 14374  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14375  	a_PREGZM_Pg1013_ZeroPredCheck,
 14376  	a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
 14377  }
 14378  
 14379  var XnSP__cimm__MUL_VL___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
 14380  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14381  	a_PREGZM_Pg1013_ZeroPredCheck,
 14382  	a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
 14383  }
 14384  
 14385  var XnSP__cimm__MUL_VL___PgZ___Zt_B_ = []operand{
 14386  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14387  	a_PREGZM_Pg1013_ZeroPredCheck,
 14388  	a_REGLIST1_Zt05_ArngBCheck,
 14389  }
 14390  
 14391  var XnSP__cimm__MUL_VL___PgZ___Zt_D_ = []operand{
 14392  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14393  	a_PREGZM_Pg1013_ZeroPredCheck,
 14394  	a_REGLIST1_Zt05_ArngDCheck,
 14395  }
 14396  
 14397  var XnSP__cimm__MUL_VL___PgZ___Zt_H_ = []operand{
 14398  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14399  	a_PREGZM_Pg1013_ZeroPredCheck,
 14400  	a_REGLIST1_Zt05_ArngHCheck,
 14401  }
 14402  
 14403  var XnSP__cimm__MUL_VL___PgZ___Zt_Q_ = []operand{
 14404  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14405  	a_PREGZM_Pg1013_ZeroPredCheck,
 14406  	a_REGLIST1_Zt05_ArngQCheck,
 14407  }
 14408  
 14409  var XnSP__cimm__MUL_VL___PgZ___Zt_S_ = []operand{
 14410  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14411  	a_PREGZM_Pg1013_ZeroPredCheck,
 14412  	a_REGLIST1_Zt05_ArngSCheck,
 14413  }
 14414  
 14415  var XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B_ = []operand{
 14416  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14417  	a_PREG_Pg1013_Noop,
 14418  	a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
 14419  }
 14420  
 14421  var XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B_ = []operand{
 14422  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14423  	a_PREG_Pg1013_Noop,
 14424  	a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
 14425  }
 14426  
 14427  var XnSP__cimm__MUL_VL___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
 14428  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14429  	a_PREG_Pg1013_Noop,
 14430  	a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
 14431  }
 14432  
 14433  var XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D_ = []operand{
 14434  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14435  	a_PREG_Pg1013_Noop,
 14436  	a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
 14437  }
 14438  
 14439  var XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D_ = []operand{
 14440  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14441  	a_PREG_Pg1013_Noop,
 14442  	a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
 14443  }
 14444  
 14445  var XnSP__cimm__MUL_VL___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
 14446  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14447  	a_PREG_Pg1013_Noop,
 14448  	a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
 14449  }
 14450  
 14451  var XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H_ = []operand{
 14452  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14453  	a_PREG_Pg1013_Noop,
 14454  	a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
 14455  }
 14456  
 14457  var XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H_ = []operand{
 14458  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14459  	a_PREG_Pg1013_Noop,
 14460  	a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
 14461  }
 14462  
 14463  var XnSP__cimm__MUL_VL___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
 14464  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14465  	a_PREG_Pg1013_Noop,
 14466  	a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
 14467  }
 14468  
 14469  var XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q_ = []operand{
 14470  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14471  	a_PREG_Pg1013_Noop,
 14472  	a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
 14473  }
 14474  
 14475  var XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
 14476  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14477  	a_PREG_Pg1013_Noop,
 14478  	a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
 14479  }
 14480  
 14481  var XnSP__cimm__MUL_VL___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
 14482  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14483  	a_PREG_Pg1013_Noop,
 14484  	a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
 14485  }
 14486  
 14487  var XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S_ = []operand{
 14488  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V6,
 14489  	a_PREG_Pg1013_Noop,
 14490  	a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
 14491  }
 14492  
 14493  var XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S_ = []operand{
 14494  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V3,
 14495  	a_PREG_Pg1013_Noop,
 14496  	a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
 14497  }
 14498  
 14499  var XnSP__cimm__MUL_VL___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
 14500  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V4,
 14501  	a_PREG_Pg1013_Noop,
 14502  	a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
 14503  }
 14504  
 14505  var XnSP__cimm__MUL_VL___Pg___Zt_B_ = []operand{
 14506  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14507  	a_PREG_Pg1013_Noop,
 14508  	a_REGLIST1_Zt05_ArngBCheck,
 14509  }
 14510  
 14511  var XnSP__cimm__MUL_VL___Pg___Zt_D_ = []operand{
 14512  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14513  	a_PREG_Pg1013_Noop,
 14514  	a_REGLIST1_Zt05_ArngDCheck,
 14515  }
 14516  
 14517  var XnSP__cimm__MUL_VL___Pg___Zt_H_ = []operand{
 14518  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14519  	a_PREG_Pg1013_Noop,
 14520  	a_REGLIST1_Zt05_ArngHCheck,
 14521  }
 14522  
 14523  var XnSP__cimm__MUL_VL___Pg___Zt_Q_ = []operand{
 14524  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14525  	a_PREG_Pg1013_Noop,
 14526  	a_REGLIST1_Zt05_ArngQCheck,
 14527  }
 14528  
 14529  var XnSP__cimm__MUL_VL___Pg___Zt_S_ = []operand{
 14530  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14531  	a_PREG_Pg1013_Noop,
 14532  	a_REGLIST1_Zt05_ArngSCheck,
 14533  }
 14534  
 14535  var XnSP__cimm__MUL_VL___Pg___Zt_T___1 = []operand{
 14536  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14537  	a_PREG_Pg1013_Noop,
 14538  	a_REGLIST1_Zt05_Size2123V1,
 14539  }
 14540  
 14541  var XnSP__cimm__MUL_VL___Pg___Zt_T___2 = []operand{
 14542  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14543  	a_PREG_Pg1013_Noop,
 14544  	a_REGLIST1_Zt05_Size2123V2,
 14545  }
 14546  
 14547  var XnSP__cimm__MUL_VL___Pg___Zt_T___3 = []operand{
 14548  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm41620V5,
 14549  	a_PREG_Pg1013_Noop,
 14550  	a_REGLIST1_Zt05_Sz2122,
 14551  }
 14552  
 14553  var XnSP__cimm__MUL_VL___Pg__prfop = []operand{
 14554  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm61622V5,
 14555  	a_PREG_Pg1013_Noop,
 14556  	a_SPECIAL_Prfop04,
 14557  }
 14558  
 14559  var XnSP__cimm__MUL_VL___Pt__1 = []operand{
 14560  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013,
 14561  	a_PREG_Pt04V1_Noop,
 14562  }
 14563  
 14564  var XnSP__cimm__MUL_VL___Pt__2 = []operand{
 14565  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013,
 14566  	a_PREG_Pt04V2_Noop,
 14567  }
 14568  
 14569  var XnSP__cimm__MUL_VL___Zt = []operand{
 14570  	a_MEMOFFMULVL_Rn510SPV2_Noop_Imm9h1622L1013,
 14571  	a_ZREG_Zt05_Noop,
 14572  }
 14573  
 14574  var XnSP__cimm___PgZ___Zt_B___1 = []operand{
 14575  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
 14576  	a_PREGZM_Pg1013_ZeroPredCheck,
 14577  	a_REGLIST1_Zt05_ArngBCheck,
 14578  }
 14579  
 14580  var XnSP__cimm___PgZ___Zt_B___2 = []operand{
 14581  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
 14582  	a_PREGZM_Pg1013_ZeroPredCheck,
 14583  	a_REGLIST1_Zt05_ArngBCheck,
 14584  }
 14585  
 14586  var XnSP__cimm___PgZ___Zt_B___3 = []operand{
 14587  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
 14588  	a_PREGZM_Pg1013_ZeroPredCheck,
 14589  	a_REGLIST1_Zt05_ArngBCheck,
 14590  }
 14591  
 14592  var XnSP__cimm___PgZ___Zt_D___1 = []operand{
 14593  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
 14594  	a_PREGZM_Pg1013_ZeroPredCheck,
 14595  	a_REGLIST1_Zt05_ArngDCheck,
 14596  }
 14597  
 14598  var XnSP__cimm___PgZ___Zt_D___2 = []operand{
 14599  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V1,
 14600  	a_PREGZM_Pg1013_ZeroPredCheck,
 14601  	a_REGLIST1_Zt05_ArngDCheck,
 14602  }
 14603  
 14604  var XnSP__cimm___PgZ___Zt_D___3 = []operand{
 14605  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V2,
 14606  	a_PREGZM_Pg1013_ZeroPredCheck,
 14607  	a_REGLIST1_Zt05_ArngDCheck,
 14608  }
 14609  
 14610  var XnSP__cimm___PgZ___Zt_D___4 = []operand{
 14611  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V3,
 14612  	a_PREGZM_Pg1013_ZeroPredCheck,
 14613  	a_REGLIST1_Zt05_ArngDCheck,
 14614  }
 14615  
 14616  var XnSP__cimm___PgZ___Zt_D___5 = []operand{
 14617  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
 14618  	a_PREGZM_Pg1013_ZeroPredCheck,
 14619  	a_REGLIST1_Zt05_ArngDCheck,
 14620  }
 14621  
 14622  var XnSP__cimm___PgZ___Zt_D___6 = []operand{
 14623  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
 14624  	a_PREGZM_Pg1013_ZeroPredCheck,
 14625  	a_REGLIST1_Zt05_ArngDCheck,
 14626  }
 14627  
 14628  var XnSP__cimm___PgZ___Zt_H___1 = []operand{
 14629  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
 14630  	a_PREGZM_Pg1013_ZeroPredCheck,
 14631  	a_REGLIST1_Zt05_ArngHCheck,
 14632  }
 14633  
 14634  var XnSP__cimm___PgZ___Zt_H___2 = []operand{
 14635  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V1,
 14636  	a_PREGZM_Pg1013_ZeroPredCheck,
 14637  	a_REGLIST1_Zt05_ArngHCheck,
 14638  }
 14639  
 14640  var XnSP__cimm___PgZ___Zt_H___3 = []operand{
 14641  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
 14642  	a_PREGZM_Pg1013_ZeroPredCheck,
 14643  	a_REGLIST1_Zt05_ArngHCheck,
 14644  }
 14645  
 14646  var XnSP__cimm___PgZ___Zt_H___4 = []operand{
 14647  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
 14648  	a_PREGZM_Pg1013_ZeroPredCheck,
 14649  	a_REGLIST1_Zt05_ArngHCheck,
 14650  }
 14651  
 14652  var XnSP__cimm___PgZ___Zt_S___1 = []operand{
 14653  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V4,
 14654  	a_PREGZM_Pg1013_ZeroPredCheck,
 14655  	a_REGLIST1_Zt05_ArngSCheck,
 14656  }
 14657  
 14658  var XnSP__cimm___PgZ___Zt_S___2 = []operand{
 14659  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V1,
 14660  	a_PREGZM_Pg1013_ZeroPredCheck,
 14661  	a_REGLIST1_Zt05_ArngSCheck,
 14662  }
 14663  
 14664  var XnSP__cimm___PgZ___Zt_S___3 = []operand{
 14665  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V2,
 14666  	a_PREGZM_Pg1013_ZeroPredCheck,
 14667  	a_REGLIST1_Zt05_ArngSCheck,
 14668  }
 14669  
 14670  var XnSP__cimm___PgZ___Zt_S___4 = []operand{
 14671  	a_MEMOFF_Rn510SPV2_Noop_Imm41620V1,
 14672  	a_PREGZM_Pg1013_ZeroPredCheck,
 14673  	a_REGLIST1_Zt05_ArngSCheck,
 14674  }
 14675  
 14676  var XnSP__cimm___PgZ___Zt_S___5 = []operand{
 14677  	a_MEMOFF_Rn510SPV2_Noop_Imm61622V2,
 14678  	a_PREGZM_Pg1013_ZeroPredCheck,
 14679  	a_REGLIST1_Zt05_ArngSCheck,
 14680  }
 14681  
 14682  var Za_D__Zm_D__Zdn_D = []operand{
 14683  	a_ARNG_Za5103Rd_ArngDCheck,
 14684  	a_ARNG_Zm1621V2_ArngDCheck,
 14685  	a_ARNG_ZdnDest_ArngDCheck,
 14686  }
 14687  
 14688  var Za_T__Zm_T__PgM__Zdn_T__1 = []operand{
 14689  	a_ARNG_Za16213Rd_SizeHSD2224,
 14690  	a_ARNG_Zm510V1_SizeHSD2224,
 14691  	a_PREGZM_Pg1013_MergePredCheck,
 14692  	a_ARNG_ZdnDest_SizeHSD2224,
 14693  }
 14694  
 14695  var Za_T__Zm_T__PgM__Zdn_T__2 = []operand{
 14696  	a_ARNG_Za5103Rd_SizeBHSD2224,
 14697  	a_ARNG_Zm1621V2_SizeBHSD2224,
 14698  	a_PREGZM_Pg1013_MergePredCheck,
 14699  	a_ARNG_ZdnDest_SizeBHSD2224,
 14700  }
 14701  
 14702  var Zdn_B__Zdn_B = []operand{
 14703  	a_ARNG_ZdnSrcDst_ArngBCheck,
 14704  	a_ARNG_ZdnSrcDst_ArngBCheck,
 14705  }
 14706  
 14707  var Zk_D__Zm_D__Zdn_D__Zdn_D = []operand{
 14708  	a_ARNG_Zk5103Rd_ArngDCheck,
 14709  	a_ARNG_Zm1621V2_ArngDCheck,
 14710  	a_ARNG_ZdnDest_ArngDCheck,
 14711  	a_ARNG_ZdnDest_ArngDCheck,
 14712  }
 14713  
 14714  var Zm_B__Zdn_B__Zdn_B = []operand{
 14715  	a_ARNG_Zm510V1_ArngBCheck,
 14716  	a_ARNG_ZdnDest_ArngBCheck,
 14717  	a_ARNG_ZdnDest_ArngBCheck,
 14718  }
 14719  
 14720  var Zm_B__Zn_B__Zd_B = []operand{
 14721  	a_ARNG_Zm1621V2_ArngBCheck,
 14722  	a_ARNG_Zn510V1_ArngBCheck,
 14723  	a_ARNG_Zd_ArngBCheck,
 14724  }
 14725  
 14726  var Zm_B__Zn_B__Zda_H = []operand{
 14727  	a_ARNG_Zm1621V2_ArngBCheck,
 14728  	a_ARNG_Zn510V1_ArngBCheck,
 14729  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14730  }
 14731  
 14732  var Zm_B__Zn_B__Zda_S = []operand{
 14733  	a_ARNG_Zm1621V2_ArngBCheck,
 14734  	a_ARNG_Zn510V1_ArngBCheck,
 14735  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14736  }
 14737  
 14738  var Zm_B_imm___Zn_B__Zda_H__1 = []operand{
 14739  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019,
 14740  	a_ARNG_Zn510V1_ArngBCheck,
 14741  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14742  }
 14743  
 14744  var Zm_B_imm___Zn_B__Zda_H__2 = []operand{
 14745  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit,
 14746  	a_ARNG_Zn510V1_ArngBCheck,
 14747  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14748  }
 14749  
 14750  var Zm_B_imm___Zn_B__Zda_H__3 = []operand{
 14751  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit,
 14752  	a_ARNG_Zn510V1_ArngBCheck,
 14753  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14754  }
 14755  
 14756  var Zm_B_imm___Zn_B__Zda_S__1 = []operand{
 14757  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019,
 14758  	a_ARNG_Zn510V1_ArngBCheck,
 14759  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14760  }
 14761  
 14762  var Zm_B_imm___Zn_B__Zda_S__2 = []operand{
 14763  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup,
 14764  	a_ARNG_Zn510V1_ArngBCheck,
 14765  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14766  }
 14767  
 14768  var Zm_B_imm___Zn_B__Zda_S__3 = []operand{
 14769  	a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit,
 14770  	a_ARNG_Zn510V1_ArngBCheck,
 14771  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14772  }
 14773  
 14774  var Zm_D__Zdn_D__PgM__Zdn_D = []operand{
 14775  	a_ARNG_Zm510V1_ArngDCheck,
 14776  	a_ARNG_ZdnDest_ArngDCheck,
 14777  	a_PREGZM_Pg1013_MergePredCheck,
 14778  	a_ARNG_ZdnDest_ArngDCheck,
 14779  }
 14780  
 14781  var Zm_D__Zdn_T__PgM__Zdn_T = []operand{
 14782  	a_ARNG_Zm510V1_ArngDCheck,
 14783  	a_ARNG_ZdnDest_SizeBHS2224,
 14784  	a_PREGZM_Pg1013_MergePredCheck,
 14785  	a_ARNG_ZdnDest_SizeBHS2224,
 14786  }
 14787  
 14788  var Zm_D__Zn_D__Zd_D = []operand{
 14789  	a_ARNG_Zm1621V2_ArngDCheck,
 14790  	a_ARNG_Zn510V1_ArngDCheck,
 14791  	a_ARNG_Zd_ArngDCheck,
 14792  }
 14793  
 14794  var Zm_D__Zn_D__Zd_Q = []operand{
 14795  	a_ARNG_Zm1621V2_ArngDCheck,
 14796  	a_ARNG_Zn510V1_ArngDCheck,
 14797  	a_ARNG_Zd_ArngQCheck,
 14798  }
 14799  
 14800  var Zm_D__Zn_D__Zda_D = []operand{
 14801  	a_ARNG_Zm1621V2_ArngDCheck,
 14802  	a_ARNG_Zn510V1_ArngDCheck,
 14803  	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 14804  }
 14805  
 14806  var Zm_D__Zn_D___Zd1_Q_Zd2_Q_ = []operand{
 14807  	a_ARNG_Zm1621V2_ArngDCheck,
 14808  	a_ARNG_Zn510V1_ArngDCheck,
 14809  	a_REGLIST_RANGE_Zd15V1_ArngQCheck_Zd15V2_ArngQCheck,
 14810  }
 14811  
 14812  var Zm_D__Zn_D___Zda1_Q_Zda2_Q_ = []operand{
 14813  	a_ARNG_Zm1621V2_ArngDCheck,
 14814  	a_ARNG_Zn510V1_ArngDCheck,
 14815  	a_REGLIST_RANGE_Zda15V1_ArngQCheck_Zda15V2_ArngQCheck,
 14816  }
 14817  
 14818  var Zm_D__Zn_T__PgZ__Pd_T = []operand{
 14819  	a_ARNG_Zm1621V2_ArngDCheck,
 14820  	a_ARNG_Zn510V1_SizeBHS2224,
 14821  	a_PREGZM_Pg1013_ZeroPredCheck,
 14822  	a_ARNG_Pd_SizeBHS2224,
 14823  }
 14824  
 14825  var Zm_D__Zn_T__Zd_T = []operand{
 14826  	a_ARNG_Zm1621V2_ArngDCheck,
 14827  	a_ARNG_Zn510V1_SizeBHS2224,
 14828  	a_ARNG_Zd_SizeBHS2224,
 14829  }
 14830  
 14831  var Zm_D_imm___Zn_D__Zd_D__1 = []operand{
 14832  	a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit,
 14833  	a_ARNG_Zn510V1_ArngDCheck,
 14834  	a_ARNG_Zd_ArngDCheck,
 14835  }
 14836  
 14837  var Zm_D_imm___Zn_D__Zd_D__2 = []operand{
 14838  	a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision,
 14839  	a_ARNG_Zn510V1_ArngDCheck,
 14840  	a_ARNG_Zd_ArngDCheck,
 14841  }
 14842  
 14843  var Zm_D_imm___Zn_D__Zda_D__1 = []operand{
 14844  	a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit,
 14845  	a_ARNG_Zn510V1_ArngDCheck,
 14846  	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 14847  }
 14848  
 14849  var Zm_D_imm___Zn_D__Zda_D__2 = []operand{
 14850  	a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision,
 14851  	a_ARNG_Zn510V1_ArngDCheck,
 14852  	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 14853  }
 14854  
 14855  var Zm_H__Zdn_H__PgM__Zdn_H = []operand{
 14856  	a_ARNG_Zm510V1_ArngHCheck,
 14857  	a_ARNG_ZdnDest_ArngHCheck,
 14858  	a_PREGZM_Pg1013_MergePredCheck,
 14859  	a_ARNG_ZdnDest_ArngHCheck,
 14860  }
 14861  
 14862  var Zm_H__Zn_H__PgM__Zda_H = []operand{
 14863  	a_ARNG_Zm1621V2_ArngHCheck,
 14864  	a_ARNG_Zn510V1_ArngHCheck,
 14865  	a_PREGZM_Pg1013_MergePredCheck,
 14866  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14867  }
 14868  
 14869  var Zm_H__Zn_H__Zd_H = []operand{
 14870  	a_ARNG_Zm1621V2_ArngHCheck,
 14871  	a_ARNG_Zn510V1_ArngHCheck,
 14872  	a_ARNG_Zd_ArngHCheck,
 14873  }
 14874  
 14875  var Zm_H__Zn_H__Zda_H = []operand{
 14876  	a_ARNG_Zm1621V2_ArngHCheck,
 14877  	a_ARNG_Zn510V1_ArngHCheck,
 14878  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14879  }
 14880  
 14881  var Zm_H__Zn_H__Zda_S = []operand{
 14882  	a_ARNG_Zm1621V2_ArngHCheck,
 14883  	a_ARNG_Zn510V1_ArngHCheck,
 14884  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14885  }
 14886  
 14887  var Zm_H_imm___Zn_H__Zd_H__1 = []operand{
 14888  	a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit,
 14889  	a_ARNG_Zn510V1_ArngHCheck,
 14890  	a_ARNG_Zd_ArngHCheck,
 14891  }
 14892  
 14893  var Zm_H_imm___Zn_H__Zd_H__2 = []operand{
 14894  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922,
 14895  	a_ARNG_Zn510V1_ArngHCheck,
 14896  	a_ARNG_Zd_ArngHCheck,
 14897  }
 14898  
 14899  var Zm_H_imm___Zn_H__Zd_H__3 = []operand{
 14900  	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision,
 14901  	a_ARNG_Zn510V1_ArngHCheck,
 14902  	a_ARNG_Zd_ArngHCheck,
 14903  }
 14904  
 14905  var Zm_H_imm___Zn_H__Zd_S = []operand{
 14906  	a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit,
 14907  	a_ARNG_Zn510V1_ArngHCheck,
 14908  	a_ARNG_Zd_ArngSCheck,
 14909  }
 14910  
 14911  var Zm_H_imm___Zn_H__Zda_D = []operand{
 14912  	a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit,
 14913  	a_ARNG_Zn510V1_ArngHCheck,
 14914  	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 14915  }
 14916  
 14917  var Zm_H_imm___Zn_H__Zda_H__1 = []operand{
 14918  	a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit,
 14919  	a_ARNG_Zn510V1_ArngHCheck,
 14920  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14921  }
 14922  
 14923  var Zm_H_imm___Zn_H__Zda_H__2 = []operand{
 14924  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922,
 14925  	a_ARNG_Zn510V1_ArngHCheck,
 14926  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14927  }
 14928  
 14929  var Zm_H_imm___Zn_H__Zda_H__3 = []operand{
 14930  	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision,
 14931  	a_ARNG_Zn510V1_ArngHCheck,
 14932  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 14933  }
 14934  
 14935  var Zm_H_imm___Zn_H__Zda_S__1 = []operand{
 14936  	a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit,
 14937  	a_ARNG_Zn510V1_ArngHCheck,
 14938  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14939  }
 14940  
 14941  var Zm_H_imm___Zn_H__Zda_S__2 = []operand{
 14942  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119,
 14943  	a_ARNG_Zn510V1_ArngHCheck,
 14944  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14945  }
 14946  
 14947  var Zm_H_imm___Zn_H__Zda_S__3 = []operand{
 14948  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit,
 14949  	a_ARNG_Zn510V1_ArngHCheck,
 14950  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14951  }
 14952  
 14953  var Zm_H_imm___Zn_H__Zda_S__4 = []operand{
 14954  	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit,
 14955  	a_ARNG_Zn510V1_ArngHCheck,
 14956  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14957  }
 14958  
 14959  var Zm_Q__Zn_Q__Zd_Q = []operand{
 14960  	a_ARNG_Zm1621V2_ArngQCheck,
 14961  	a_ARNG_Zn510V1_ArngQCheck,
 14962  	a_ARNG_Zd_ArngQCheck,
 14963  }
 14964  
 14965  var Zm_Q_index____Zdn1_B_Zdn2_B____Zdn1_B_Zdn2_B_ = []operand{
 14966  	a_ARNGIDX_Zm510V1_ArngQCheck_I21921,
 14967  	a_REGLIST_RANGE_Zdn15V1_ArngBCheck_Zdn15V2_ArngBCheck,
 14968  	a_REGLIST_RANGE_Zdn15V1_ArngBCheck_Zdn15V2_ArngBCheck,
 14969  }
 14970  
 14971  var Zm_Q_index____Zdn1_B_Zdn4_B____Zdn1_B_Zdn4_B_ = []operand{
 14972  	a_ARNGIDX_Zm510V1_ArngQCheck_I21921,
 14973  	a_REGLIST_RANGE_Zdn25V1_ArngBCheck_Zdn25V2_ArngBCheck,
 14974  	a_REGLIST_RANGE_Zdn25V1_ArngBCheck_Zdn25V2_ArngBCheck,
 14975  }
 14976  
 14977  var Zm_S__Zdn_S__Zdn_S = []operand{
 14978  	a_ARNG_Zm510V1_ArngSCheck,
 14979  	a_ARNG_ZdnDest_ArngSCheck,
 14980  	a_ARNG_ZdnDest_ArngSCheck,
 14981  }
 14982  
 14983  var Zm_S__Zn_S__Zd_S = []operand{
 14984  	a_ARNG_Zm1621V2_ArngSCheck,
 14985  	a_ARNG_Zn510V1_ArngSCheck,
 14986  	a_ARNG_Zd_ArngSCheck,
 14987  }
 14988  
 14989  var Zm_S__Zn_S__Zda_S = []operand{
 14990  	a_ARNG_Zm1621V2_ArngSCheck,
 14991  	a_ARNG_Zn510V1_ArngSCheck,
 14992  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 14993  }
 14994  
 14995  var Zm_S_imm___Zn_S__Zd_D = []operand{
 14996  	a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit,
 14997  	a_ARNG_Zn510V1_ArngSCheck,
 14998  	a_ARNG_Zd_ArngDCheck,
 14999  }
 15000  
 15001  var Zm_S_imm___Zn_S__Zd_S__1 = []operand{
 15002  	a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit,
 15003  	a_ARNG_Zn510V1_ArngSCheck,
 15004  	a_ARNG_Zd_ArngSCheck,
 15005  }
 15006  
 15007  var Zm_S_imm___Zn_S__Zd_S__2 = []operand{
 15008  	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision,
 15009  	a_ARNG_Zn510V1_ArngSCheck,
 15010  	a_ARNG_Zd_ArngSCheck,
 15011  }
 15012  
 15013  var Zm_S_imm___Zn_S__Zda_D = []operand{
 15014  	a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit,
 15015  	a_ARNG_Zn510V1_ArngSCheck,
 15016  	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 15017  }
 15018  
 15019  var Zm_S_imm___Zn_S__Zda_S__1 = []operand{
 15020  	a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit,
 15021  	a_ARNG_Zn510V1_ArngSCheck,
 15022  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 15023  }
 15024  
 15025  var Zm_S_imm___Zn_S__Zda_S__2 = []operand{
 15026  	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision,
 15027  	a_ARNG_Zn510V1_ArngSCheck,
 15028  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 15029  }
 15030  
 15031  var Zm_T__Rdn__Pg__Rdn = []operand{
 15032  	a_ARNG_Zm510V2_SizeBHSD2224,
 15033  	a_SPZGREG_Noop_Rdn05ZR,
 15034  	a_PREG_Pg1013_Noop,
 15035  	a_SPZGREG_Noop_Rdn05ZR,
 15036  }
 15037  
 15038  var Zm_T__Vdn__Pg__Vdn__1 = []operand{
 15039  	a_ARNG_Zm510V2_SizeBHSD2224,
 15040  	a_VREG_Noop_Vdn05,
 15041  	a_PREG_Pg1013_Noop,
 15042  	a_VREG_Noop_Vdn05,
 15043  }
 15044  
 15045  var Zm_T__Vdn__Pg__Vdn__2 = []operand{
 15046  	a_ARNG_Zm510V2_SizeHSD2224,
 15047  	a_VREG_Noop_Vdn05,
 15048  	a_PREG_Pg1013_Noop,
 15049  	a_VREG_Noop_Vdn05,
 15050  }
 15051  
 15052  var Zm_T__Zdn_T__PgM__Zdn_T__1 = []operand{
 15053  	a_ARNG_Zm510V1_SizeBHSD2224,
 15054  	a_ARNG_ZdnDest_SizeBHSD2224,
 15055  	a_PREGZM_Pg1013_MergePredCheck,
 15056  	a_ARNG_ZdnDest_SizeBHSD2224,
 15057  }
 15058  
 15059  var Zm_T__Zdn_T__PgM__Zdn_T__2 = []operand{
 15060  	a_ARNG_Zm510V1_SizeHSD2224,
 15061  	a_ARNG_ZdnDest_SizeHSD2224,
 15062  	a_PREGZM_Pg1013_MergePredCheck,
 15063  	a_ARNG_ZdnDest_SizeHSD2224,
 15064  }
 15065  
 15066  var Zm_T__Zdn_T__PgM__Zdn_T__3 = []operand{
 15067  	a_ARNG_Zm510V1_SizeHSD2224No00,
 15068  	a_ARNG_ZdnDest_SizeHSD2224No00,
 15069  	a_PREGZM_Pg1013_MergePredCheck,
 15070  	a_ARNG_ZdnDest_SizeHSD2224No00,
 15071  }
 15072  
 15073  var Zm_T__Zdn_T__PgM__Zdn_T__4 = []operand{
 15074  	a_ARNG_Zm510V1_Size0SD2223,
 15075  	a_ARNG_ZdnDest_Size0SD2223,
 15076  	a_PREGZM_Pg1013_MergePredCheck,
 15077  	a_ARNG_ZdnDest_Size0SD2223,
 15078  }
 15079  
 15080  var Zm_T__Zdn_T__Pg__Zdn_T = []operand{
 15081  	a_ARNG_Zm510V1_SizeBHSD2224,
 15082  	a_ARNG_ZdnDest_SizeBHSD2224,
 15083  	a_PREG_Pg1013_Noop,
 15084  	a_ARNG_ZdnDest_SizeBHSD2224,
 15085  }
 15086  
 15087  var Zm_T__Zdn_T__Pv__Zdn_T = []operand{
 15088  	a_ARNG_Zm510V1_SizeBHSD2224,
 15089  	a_ARNG_ZdnDest_SizeBHSD2224,
 15090  	a_PREG_Pv1013_Noop,
 15091  	a_ARNG_ZdnDest_SizeBHSD2224,
 15092  }
 15093  
 15094  var Zm_T__Zn_T__PgM__Zda_T__1 = []operand{
 15095  	a_ARNG_Zm1621V2_SizeHSD2224No00,
 15096  	a_ARNG_Zn510V1_SizeHSD2224No00,
 15097  	a_PREGZM_Pg1013_MergePredCheck,
 15098  	a_ARNG_Zda3RdSrcDst_SizeHSD2224No00,
 15099  }
 15100  
 15101  var Zm_T__Zn_T__PgM__Zda_T__2 = []operand{
 15102  	a_ARNG_Zm1621V2_SizeBHSD2224,
 15103  	a_ARNG_Zn510V1_SizeBHSD2224,
 15104  	a_PREGZM_Pg1013_MergePredCheck,
 15105  	a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
 15106  }
 15107  
 15108  var Zm_T__Zn_T__PgZ__Pd_T__1 = []operand{
 15109  	a_ARNG_Zm1621V2_SizeHSD2224,
 15110  	a_ARNG_Zn510V1_SizeHSD2224,
 15111  	a_PREGZM_Pg1013_ZeroPredCheck,
 15112  	a_ARNG_Pd_SizeHSD2224,
 15113  }
 15114  
 15115  var Zm_T__Zn_T__PgZ__Pd_T__2 = []operand{
 15116  	a_ARNG_Zm1621V2_SizeBHSD2224,
 15117  	a_ARNG_Zn510V1_SizeBHSD2224,
 15118  	a_PREGZM_Pg1013_ZeroPredCheck,
 15119  	a_ARNG_Pd_SizeBHSD2224,
 15120  }
 15121  
 15122  var Zm_T__Zn_T__PgZ__Pd_T__3 = []operand{
 15123  	a_ARNG_Zm1621V2_Size0BH2223,
 15124  	a_ARNG_Zn510V1_Size0BH2223,
 15125  	a_PREGZM_Pg1013_ZeroPredCheck,
 15126  	a_ARNG_Pd_Size0BH2223,
 15127  }
 15128  
 15129  var Zm_T__Zn_T__PgZ__Zd_T = []operand{
 15130  	a_ARNG_Zm1621V2_Size0SD2223,
 15131  	a_ARNG_Zn510V1_Size0SD2223,
 15132  	a_PREGZM_Pg1013_ZeroPredCheck,
 15133  	a_ARNG_Zd_Size0SD2223,
 15134  }
 15135  
 15136  var Zm_T__Zn_T__Pv__Zd_T = []operand{
 15137  	a_ARNG_Zm1621V2_SizeBHSD2224,
 15138  	a_ARNG_Zn510V1_SizeBHSD2224,
 15139  	a_PREG_Pv1014_Noop,
 15140  	a_ARNG_Zd_SizeBHSD2224,
 15141  }
 15142  
 15143  var Zm_T__Zn_T__Zd_T__1 = []operand{
 15144  	a_ARNG_Zm1621V2_SizeBHSD2224,
 15145  	a_ARNG_Zn510V1_SizeBHSD2224,
 15146  	a_ARNG_Zd_SizeBHSD2224,
 15147  }
 15148  
 15149  var Zm_T__Zn_T__Zd_T__2 = []operand{
 15150  	a_ARNG_Zm1621V2_SizeHSD2224No00,
 15151  	a_ARNG_Zn510V1_SizeHSD2224No00,
 15152  	a_ARNG_Zd_SizeHSD2224No00,
 15153  }
 15154  
 15155  var Zm_T__Zn_T__Zd_T__3 = []operand{
 15156  	a_ARNG_Zm1621V2_SizeHSD2224,
 15157  	a_ARNG_Zn510V1_SizeHSD2224,
 15158  	a_ARNG_Zd_SizeHSD2224,
 15159  }
 15160  
 15161  var Zm_T__Zn_T__Zda_T__1 = []operand{
 15162  	a_ARNG_Zm1621V2_SzSD2223,
 15163  	a_ARNG_Zn510V1_SzSD2223,
 15164  	a_ARNG_Zda3RdSrcDst_SzSD2223,
 15165  }
 15166  
 15167  var Zm_T__Zn_T__Zda_T__2 = []operand{
 15168  	a_ARNG_Zm1621V2_SizeBHSD2224,
 15169  	a_ARNG_Zn510V1_SizeBHSD2224,
 15170  	a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
 15171  }
 15172  
 15173  var Zm_T___Zn1_T__Zn2_T___Zd_T = []operand{
 15174  	a_ARNG_Zm1621V2_SizeBHSD2224,
 15175  	a_REGLIST2_GenZn510V1_SizeBHSD2224_GenZn510V2_SizeBHSD2224,
 15176  	a_ARNG_Zd_SizeBHSD2224,
 15177  }
 15178  
 15179  var Zm_T___Zn_T___Zd_T = []operand{
 15180  	a_ARNG_Zm1621V2_SizeBHSD2224,
 15181  	a_REGLIST1_Zn510V1_SizeBHSD2224,
 15182  	a_ARNG_Zd_SizeBHSD2224,
 15183  }
 15184  
 15185  var Zm_Tb__Zn_T__Zd_T = []operand{
 15186  	a_ARNG_Zm1621V2_SizeTbBHS2224,
 15187  	a_ARNG_Zn510V1_SizeHSD2224,
 15188  	a_ARNG_Zd_SizeHSD2224,
 15189  }
 15190  
 15191  var Zm_Tb__Zn_Tb__Zd_T__1 = []operand{
 15192  	a_ARNG_Zm1621V2_SizeTbBHS2224,
 15193  	a_ARNG_Zn510V1_SizeTbBHS2224,
 15194  	a_ARNG_Zd_SizeHSD2224,
 15195  }
 15196  
 15197  var Zm_Tb__Zn_Tb__Zd_T__2 = []operand{
 15198  	a_ARNG_Zm1621V2_SizeTbHSD2224Offset1,
 15199  	a_ARNG_Zn510V1_SizeTbHSD2224Offset1,
 15200  	a_ARNG_Zd_SizeBHS2224Offset1,
 15201  }
 15202  
 15203  var Zm_Tb__Zn_Tb__Zd_T__3 = []operand{
 15204  	a_ARNG_Zm1621V2_SizeTbBS2224,
 15205  	a_ARNG_Zn510V1_SizeTbBS2224,
 15206  	a_ARNG_Zd_SizeHD2224,
 15207  }
 15208  
 15209  var Zm_Tb__Zn_Tb__Zda_T__1 = []operand{
 15210  	a_ARNG_Zm1621V2_SizeTbBHS2224,
 15211  	a_ARNG_Zn510V1_SizeTbBHS2224,
 15212  	a_ARNG_Zda3RdSrcDst_SizeHSD2224,
 15213  }
 15214  
 15215  var Zm_Tb__Zn_Tb__Zda_T__2 = []operand{
 15216  	a_ARNG_Zm1621V2_Size0TbBH2223,
 15217  	a_ARNG_Zn510V1_Size0TbBH2223,
 15218  	a_ARNG_Zda3RdSrcDst_Size0SD2223,
 15219  }
 15220  
 15221  var Zm___Zn1_B__Zn2_B___Zd_B = []operand{
 15222  	a_ZREG_Zm1621V1_Noop,
 15223  	a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck,
 15224  	a_ARNG_Zd_ArngBCheck,
 15225  }
 15226  
 15227  var Zm_index____Zn1_H__Zn2_H___Zd_H__1 = []operand{
 15228  	a_ZREGIDX_Zm1621V1_Noop_I22224HW,
 15229  	a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck,
 15230  	a_ARNG_Zd_ArngHCheck,
 15231  }
 15232  
 15233  var Zm_index____Zn1_H__Zn2_H___Zd_H__2 = []operand{
 15234  	a_ZREGIDX_Zm1621V1_Noop_I12324,
 15235  	a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck,
 15236  	a_ARNG_Zd_ArngHCheck,
 15237  }
 15238  
 15239  var Zm_index____Zn_B___Zd_B__1 = []operand{
 15240  	a_ZREGIDX_Zm1621V1_Noop_I22224,
 15241  	a_REGLIST1_Zn510Table3_ArngBCheck,
 15242  	a_ARNG_Zd_ArngBCheck,
 15243  }
 15244  
 15245  var Zm_index____Zn_B___Zd_B__2 = []operand{
 15246  	a_ZREGIDX_Zm1621V1_Noop_I12324B,
 15247  	a_REGLIST1_Zn510Table3_ArngBCheck,
 15248  	a_ARNG_Zd_ArngBCheck,
 15249  }
 15250  
 15251  var Zm_index____Zn_H___Zd_H__1 = []operand{
 15252  	a_ZREGIDX_Zm1621V1_Noop_I3224I31213,
 15253  	a_REGLIST1_Zn510Table3_ArngHCheck,
 15254  	a_ARNG_Zd_ArngHCheck,
 15255  }
 15256  
 15257  var Zm_index____Zn_H___Zd_H__2 = []operand{
 15258  	a_ZREGIDX_Zm1621V1_Noop_I22224HW,
 15259  	a_REGLIST1_Zn510Table3_ArngHCheck,
 15260  	a_ARNG_Zd_ArngHCheck,
 15261  }
 15262  
 15263  var Zn1_H_Zn2_H___Zd_B = []operand{
 15264  	a_REGLIST_RANGE_Zn610V1_ArngHCheck_Zn610V2_ArngHCheck,
 15265  	a_ARNG_Zd_ArngBCheck,
 15266  }
 15267  
 15268  var Zn1_S_Zn2_S___Zd_B = []operand{
 15269  	a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck,
 15270  	a_ARNG_Zd_ArngBCheck,
 15271  }
 15272  
 15273  var Zn1_S_Zn2_S___Zd_H = []operand{
 15274  	a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck,
 15275  	a_ARNG_Zd_ArngHCheck,
 15276  }
 15277  
 15278  var Zn1_T__Zn2_T___Pv__Zd_T = []operand{
 15279  	a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224,
 15280  	a_PREG_Pv1013_Noop,
 15281  	a_ARNG_Zd_SizeBHSD2224,
 15282  }
 15283  
 15284  var Zn1_Tb_Zn2_Tb___Zd_T = []operand{
 15285  	a_REGLIST_RANGE_Zn610V1_SizeTbHSD2224Offset1_Zn610V2_SizeTbHSD2224Offset1,
 15286  	a_ARNG_Zd_SizeBHS2224Offset1,
 15287  }
 15288  
 15289  var Zn_B__Zd_H = []operand{
 15290  	a_ARNG_Zn510Src_ArngBCheck,
 15291  	a_ARNG_Zd_ArngHCheck,
 15292  }
 15293  
 15294  var Zn_D__PgM__Zd_D = []operand{
 15295  	a_ARNG_Zn510Src_ArngDCheck,
 15296  	a_PREGZM_Pg1013_MergePredCheck,
 15297  	a_ARNG_Zd_ArngDCheck,
 15298  }
 15299  
 15300  var Zn_D__PgM__Zd_H = []operand{
 15301  	a_ARNG_Zn510Src_ArngDCheck,
 15302  	a_PREGZM_Pg1013_MergePredCheck,
 15303  	a_ARNG_Zd_ArngHCheck,
 15304  }
 15305  
 15306  var Zn_D__PgM__Zd_S = []operand{
 15307  	a_ARNG_Zn510Src_ArngDCheck,
 15308  	a_PREGZM_Pg1013_MergePredCheck,
 15309  	a_ARNG_Zd_ArngSCheck,
 15310  }
 15311  
 15312  var Zn_D__PgZ__Zd_D = []operand{
 15313  	a_ARNG_Zn510Src_ArngDCheck,
 15314  	a_PREGZM_Pg1013_ZeroPredCheck,
 15315  	a_ARNG_Zd_ArngDCheck,
 15316  }
 15317  
 15318  var Zn_D__PgZ__Zd_H = []operand{
 15319  	a_ARNG_Zn510Src_ArngDCheck,
 15320  	a_PREGZM_Pg1013_ZeroPredCheck,
 15321  	a_ARNG_Zd_ArngHCheck,
 15322  }
 15323  
 15324  var Zn_D__PgZ__Zd_S = []operand{
 15325  	a_ARNG_Zn510Src_ArngDCheck,
 15326  	a_PREGZM_Pg1013_ZeroPredCheck,
 15327  	a_ARNG_Zd_ArngSCheck,
 15328  }
 15329  
 15330  var Zn_D__Xm___PgZ___Zt_D_ = []operand{
 15331  	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 15332  	a_PREGZM_Pg1013_ZeroPredCheck,
 15333  	a_REGLIST1_Zt05_ArngDCheck,
 15334  }
 15335  
 15336  var Zn_D__Xm___PgZ___Zt_Q_ = []operand{
 15337  	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 15338  	a_PREGZM_Pg1013_ZeroPredCheck,
 15339  	a_REGLIST1_Zt05_ArngQCheck,
 15340  }
 15341  
 15342  var Zn_D__Xm___Pg___Zt_D_ = []operand{
 15343  	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 15344  	a_PREG_Pg1013_Noop,
 15345  	a_REGLIST1_Zt05_ArngDCheck,
 15346  }
 15347  
 15348  var Zn_D__Xm___Pg___Zt_Q_ = []operand{
 15349  	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 15350  	a_PREG_Pg1013_Noop,
 15351  	a_REGLIST1_Zt05_ArngQCheck,
 15352  }
 15353  
 15354  var Zn_D__Zm_D__SXTWamount___Zd_D = []operand{
 15355  	a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount,
 15356  	a_ARNG_Zd_ArngDCheck,
 15357  }
 15358  
 15359  var Zn_D__Zm_D__UXTWamount___Zd_D = []operand{
 15360  	a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount,
 15361  	a_ARNG_Zd_ArngDCheck,
 15362  }
 15363  
 15364  var Zn_D__cimm___PgZ___Zt_D___1 = []operand{
 15365  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4,
 15366  	a_PREGZM_Pg1013_ZeroPredCheck,
 15367  	a_REGLIST1_Zt05_ArngDCheck,
 15368  }
 15369  
 15370  var Zn_D__cimm___PgZ___Zt_D___2 = []operand{
 15371  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1,
 15372  	a_PREGZM_Pg1013_ZeroPredCheck,
 15373  	a_REGLIST1_Zt05_ArngDCheck,
 15374  }
 15375  
 15376  var Zn_D__cimm___PgZ___Zt_D___3 = []operand{
 15377  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2,
 15378  	a_PREGZM_Pg1013_ZeroPredCheck,
 15379  	a_REGLIST1_Zt05_ArngDCheck,
 15380  }
 15381  
 15382  var Zn_D__cimm___PgZ___Zt_D___4 = []operand{
 15383  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3,
 15384  	a_PREGZM_Pg1013_ZeroPredCheck,
 15385  	a_REGLIST1_Zt05_ArngDCheck,
 15386  }
 15387  
 15388  var Zn_D__cimm___Pg___Zt_D___1 = []operand{
 15389  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4,
 15390  	a_PREG_Pg1013_Noop,
 15391  	a_REGLIST1_Zt05_ArngDCheck,
 15392  }
 15393  
 15394  var Zn_D__cimm___Pg___Zt_D___2 = []operand{
 15395  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3,
 15396  	a_PREG_Pg1013_Noop,
 15397  	a_REGLIST1_Zt05_ArngDCheck,
 15398  }
 15399  
 15400  var Zn_D__cimm___Pg___Zt_D___3 = []operand{
 15401  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1,
 15402  	a_PREG_Pg1013_Noop,
 15403  	a_REGLIST1_Zt05_ArngDCheck,
 15404  }
 15405  
 15406  var Zn_D__cimm___Pg___Zt_D___4 = []operand{
 15407  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2,
 15408  	a_PREG_Pg1013_Noop,
 15409  	a_REGLIST1_Zt05_ArngDCheck,
 15410  }
 15411  
 15412  var Zn_D__cimm___Pg__prfop__1 = []operand{
 15413  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V4,
 15414  	a_PREG_Pg1013_Noop,
 15415  	a_SPECIAL_Prfop04,
 15416  }
 15417  
 15418  var Zn_D__cimm___Pg__prfop__2 = []operand{
 15419  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V3,
 15420  	a_PREG_Pg1013_Noop,
 15421  	a_SPECIAL_Prfop04,
 15422  }
 15423  
 15424  var Zn_D__cimm___Pg__prfop__3 = []operand{
 15425  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V1,
 15426  	a_PREG_Pg1013_Noop,
 15427  	a_SPECIAL_Prfop04,
 15428  }
 15429  
 15430  var Zn_D__cimm___Pg__prfop__4 = []operand{
 15431  	a_MEMOFF_Zn510V2_ArngDCheck_Imm51621V2,
 15432  	a_PREG_Pg1013_Noop,
 15433  	a_SPECIAL_Prfop04,
 15434  }
 15435  
 15436  var Zn_H__PgM__Zd_D = []operand{
 15437  	a_ARNG_Zn510Src_ArngHCheck,
 15438  	a_PREGZM_Pg1013_MergePredCheck,
 15439  	a_ARNG_Zd_ArngDCheck,
 15440  }
 15441  
 15442  var Zn_H__PgM__Zd_H = []operand{
 15443  	a_ARNG_Zn510Src_ArngHCheck,
 15444  	a_PREGZM_Pg1013_MergePredCheck,
 15445  	a_ARNG_Zd_ArngHCheck,
 15446  }
 15447  
 15448  var Zn_H__PgM__Zd_S = []operand{
 15449  	a_ARNG_Zn510Src_ArngHCheck,
 15450  	a_PREGZM_Pg1013_MergePredCheck,
 15451  	a_ARNG_Zd_ArngSCheck,
 15452  }
 15453  
 15454  var Zn_H__PgZ__Zd_D = []operand{
 15455  	a_ARNG_Zn510Src_ArngHCheck,
 15456  	a_PREGZM_Pg1013_ZeroPredCheck,
 15457  	a_ARNG_Zd_ArngDCheck,
 15458  }
 15459  
 15460  var Zn_H__PgZ__Zd_H = []operand{
 15461  	a_ARNG_Zn510Src_ArngHCheck,
 15462  	a_PREGZM_Pg1013_ZeroPredCheck,
 15463  	a_ARNG_Zd_ArngHCheck,
 15464  }
 15465  
 15466  var Zn_H__PgZ__Zd_S = []operand{
 15467  	a_ARNG_Zn510Src_ArngHCheck,
 15468  	a_PREGZM_Pg1013_ZeroPredCheck,
 15469  	a_ARNG_Zd_ArngSCheck,
 15470  }
 15471  
 15472  var Zn_Q__PgM__Zd_Q = []operand{
 15473  	a_ARNG_Zn510Src_ArngQCheck,
 15474  	a_PREGZM_Pg1013_MergePredCheck,
 15475  	a_ARNG_Zd_ArngQCheck,
 15476  }
 15477  
 15478  var Zn_Q__PgZ__Zd_Q = []operand{
 15479  	a_ARNG_Zn510Src_ArngQCheck,
 15480  	a_PREGZM_Pg1013_ZeroPredCheck,
 15481  	a_ARNG_Zd_ArngQCheck,
 15482  }
 15483  
 15484  var Zn_S__PgM__Zd_D = []operand{
 15485  	a_ARNG_Zn510Src_ArngSCheck,
 15486  	a_PREGZM_Pg1013_MergePredCheck,
 15487  	a_ARNG_Zd_ArngDCheck,
 15488  }
 15489  
 15490  var Zn_S__PgM__Zd_H = []operand{
 15491  	a_ARNG_Zn510Src_ArngSCheck,
 15492  	a_PREGZM_Pg1013_MergePredCheck,
 15493  	a_ARNG_Zd_ArngHCheck,
 15494  }
 15495  
 15496  var Zn_S__PgM__Zd_S = []operand{
 15497  	a_ARNG_Zn510Src_ArngSCheck,
 15498  	a_PREGZM_Pg1013_MergePredCheck,
 15499  	a_ARNG_Zd_ArngSCheck,
 15500  }
 15501  
 15502  var Zn_S__PgZ__Zd_D = []operand{
 15503  	a_ARNG_Zn510Src_ArngSCheck,
 15504  	a_PREGZM_Pg1013_ZeroPredCheck,
 15505  	a_ARNG_Zd_ArngDCheck,
 15506  }
 15507  
 15508  var Zn_S__PgZ__Zd_H = []operand{
 15509  	a_ARNG_Zn510Src_ArngSCheck,
 15510  	a_PREGZM_Pg1013_ZeroPredCheck,
 15511  	a_ARNG_Zd_ArngHCheck,
 15512  }
 15513  
 15514  var Zn_S__PgZ__Zd_S = []operand{
 15515  	a_ARNG_Zn510Src_ArngSCheck,
 15516  	a_PREGZM_Pg1013_ZeroPredCheck,
 15517  	a_ARNG_Zd_ArngSCheck,
 15518  }
 15519  
 15520  var Zn_S__Xm___PgZ___Zt_S_ = []operand{
 15521  	a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 15522  	a_PREGZM_Pg1013_ZeroPredCheck,
 15523  	a_REGLIST1_Zt05_ArngSCheck,
 15524  }
 15525  
 15526  var Zn_S__Xm___Pg___Zt_S_ = []operand{
 15527  	a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
 15528  	a_PREG_Pg1013_Noop,
 15529  	a_REGLIST1_Zt05_ArngSCheck,
 15530  }
 15531  
 15532  var Zn_S__cimm___PgZ___Zt_S___1 = []operand{
 15533  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4,
 15534  	a_PREGZM_Pg1013_ZeroPredCheck,
 15535  	a_REGLIST1_Zt05_ArngSCheck,
 15536  }
 15537  
 15538  var Zn_S__cimm___PgZ___Zt_S___2 = []operand{
 15539  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1,
 15540  	a_PREGZM_Pg1013_ZeroPredCheck,
 15541  	a_REGLIST1_Zt05_ArngSCheck,
 15542  }
 15543  
 15544  var Zn_S__cimm___PgZ___Zt_S___3 = []operand{
 15545  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2,
 15546  	a_PREGZM_Pg1013_ZeroPredCheck,
 15547  	a_REGLIST1_Zt05_ArngSCheck,
 15548  }
 15549  
 15550  var Zn_S__cimm___Pg___Zt_S___1 = []operand{
 15551  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4,
 15552  	a_PREG_Pg1013_Noop,
 15553  	a_REGLIST1_Zt05_ArngSCheck,
 15554  }
 15555  
 15556  var Zn_S__cimm___Pg___Zt_S___2 = []operand{
 15557  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1,
 15558  	a_PREG_Pg1013_Noop,
 15559  	a_REGLIST1_Zt05_ArngSCheck,
 15560  }
 15561  
 15562  var Zn_S__cimm___Pg___Zt_S___3 = []operand{
 15563  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2,
 15564  	a_PREG_Pg1013_Noop,
 15565  	a_REGLIST1_Zt05_ArngSCheck,
 15566  }
 15567  
 15568  var Zn_S__cimm___Pg__prfop__1 = []operand{
 15569  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V4,
 15570  	a_PREG_Pg1013_Noop,
 15571  	a_SPECIAL_Prfop04,
 15572  }
 15573  
 15574  var Zn_S__cimm___Pg__prfop__2 = []operand{
 15575  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V3,
 15576  	a_PREG_Pg1013_Noop,
 15577  	a_SPECIAL_Prfop04,
 15578  }
 15579  
 15580  var Zn_S__cimm___Pg__prfop__3 = []operand{
 15581  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V1,
 15582  	a_PREG_Pg1013_Noop,
 15583  	a_SPECIAL_Prfop04,
 15584  }
 15585  
 15586  var Zn_S__cimm___Pg__prfop__4 = []operand{
 15587  	a_MEMOFF_Zn510V2_ArngSCheck_Imm51621V2,
 15588  	a_PREG_Pg1013_Noop,
 15589  	a_SPECIAL_Prfop04,
 15590  }
 15591  
 15592  var Zn_T__PgM__Zd_T__1 = []operand{
 15593  	a_ARNG_Zn510Src_SizeHSD2224,
 15594  	a_PREGZM_Pg1013_MergePredCheck,
 15595  	a_ARNG_Zd_SizeHSD2224,
 15596  }
 15597  
 15598  var Zn_T__PgM__Zd_T__2 = []operand{
 15599  	a_ARNG_Zn510Src_SizeBHSD2224,
 15600  	a_PREGZM_Pg1013_MergePredCheck,
 15601  	a_ARNG_Zd_SizeBHSD2224,
 15602  }
 15603  
 15604  var Zn_T__PgM__Zd_T__3 = []operand{
 15605  	a_ARNG_Zn510Src_SzSD1718,
 15606  	a_PREGZM_Pg1013_MergePredCheck,
 15607  	a_ARNG_Zd_SzSD1718,
 15608  }
 15609  
 15610  var Zn_T__PgM__Zd_T__4 = []operand{
 15611  	a_ARNG_Zn510Src_SizeByteMergeZero,
 15612  	a_PREGZM_Pg1013_MergePredCheck,
 15613  	a_ARNG_Zd_SizeByteMergeZero,
 15614  }
 15615  
 15616  var Zn_T__PgM__Zd_T__5 = []operand{
 15617  	a_ARNG_Zn510Src_Size0HalfwordMergeZero,
 15618  	a_PREGZM_Pg1013_MergePredCheck,
 15619  	a_ARNG_Zd_Size0HalfwordMergeZero,
 15620  }
 15621  
 15622  var Zn_T__PgM__Zd_T__6 = []operand{
 15623  	a_ARNG_Zn510Src_SizeHSD1719,
 15624  	a_PREGZM_Pg1013_MergePredCheck,
 15625  	a_ARNG_Zd_SizeHSD1719,
 15626  }
 15627  
 15628  var Zn_T__PgZM__Zd_T = []operand{
 15629  	a_ARNG_Zn510Src_SizeBHSD2224,
 15630  	a_PREGZM_Pg1013_PredQualM1617,
 15631  	a_ARNG_Zd_SizeBHSD2224,
 15632  }
 15633  
 15634  var Zn_T__PgZ__Zd_T__1 = []operand{
 15635  	a_ARNG_Zn510Src_SizeHSD2224,
 15636  	a_PREGZM_Pg1013_ZeroPredCheck,
 15637  	a_ARNG_Zd_SizeHSD2224,
 15638  }
 15639  
 15640  var Zn_T__PgZ__Zd_T__2 = []operand{
 15641  	a_ARNG_Zn510Src_SizeBHSD2224,
 15642  	a_PREGZM_Pg1013_ZeroPredCheck,
 15643  	a_ARNG_Zd_SizeBHSD2224,
 15644  }
 15645  
 15646  var Zn_T__PgZ__Zd_T__3 = []operand{
 15647  	a_ARNG_Zn510Src_SzSD1415,
 15648  	a_PREGZM_Pg1013_ZeroPredCheck,
 15649  	a_ARNG_Zd_SzSD1415,
 15650  }
 15651  
 15652  var Zn_T__PgZ__Zd_T__4 = []operand{
 15653  	a_ARNG_Zn510Src_SizeByteMergeZero,
 15654  	a_PREGZM_Pg1013_ZeroPredCheck,
 15655  	a_ARNG_Zd_SizeByteMergeZero,
 15656  }
 15657  
 15658  var Zn_T__PgZ__Zd_T__5 = []operand{
 15659  	a_ARNG_Zn510Src_Size0HalfwordMergeZero,
 15660  	a_PREGZM_Pg1013_ZeroPredCheck,
 15661  	a_ARNG_Zd_Size0HalfwordMergeZero,
 15662  }
 15663  
 15664  var Zn_T__PgZ__Zd_T__6 = []operand{
 15665  	a_ARNG_Zn510Src_SizeHSD1315,
 15666  	a_PREGZM_Pg1013_ZeroPredCheck,
 15667  	a_ARNG_Zd_SizeHSD1315,
 15668  }
 15669  
 15670  var Zn_T__Pg__Dd__1 = []operand{
 15671  	a_ARNG_Zn510Src_SizeBHS2224,
 15672  	a_PREG_Pg1013_Noop,
 15673  	a_VREG_Noop_Vd0564,
 15674  }
 15675  
 15676  var Zn_T__Pg__Dd__2 = []operand{
 15677  	a_ARNG_Zn510Src_SizeBHSD2224,
 15678  	a_PREG_Pg1013_Noop,
 15679  	a_VREG_Noop_Vd0564,
 15680  }
 15681  
 15682  var Zn_T__Pg__Rd = []operand{
 15683  	a_ARNG_Zn510Src_SizeBHSD2224,
 15684  	a_PREG_Pg1013_Noop,
 15685  	a_SPZGREG_Noop_Rd05ZR,
 15686  }
 15687  
 15688  var Zn_T__Pg__Vd__1 = []operand{
 15689  	a_ARNG_Zn510Src_SizeBHSD2224,
 15690  	a_PREG_Pg1013_Noop,
 15691  	a_VREG_Noop_Vd05,
 15692  }
 15693  
 15694  var Zn_T__Pg__Vd__2 = []operand{
 15695  	a_ARNG_Zn510Src_SizeHSD2224,
 15696  	a_PREG_Pg1013_Noop,
 15697  	a_VREG_Noop_Vd05,
 15698  }
 15699  
 15700  var Zn_T__Pg__Zd_T__1 = []operand{
 15701  	a_ARNG_Zn510Src_SzByteHalfword,
 15702  	a_PREG_Pg1013_Noop,
 15703  	a_ARNG_Zd_SzByteHalfword,
 15704  }
 15705  
 15706  var Zn_T__Pg__Zd_T__2 = []operand{
 15707  	a_ARNG_Zn510Src_SzWordDoubleword,
 15708  	a_PREG_Pg1013_Noop,
 15709  	a_ARNG_Zd_SzWordDoubleword,
 15710  }
 15711  
 15712  var Zn_T__Pg__Zd_T__3 = []operand{
 15713  	a_ARNG_Zn510Src_SizeBHSD2224,
 15714  	a_PREG_Pg1013_Noop,
 15715  	a_ARNG_Zd_SizeBHSD2224,
 15716  }
 15717  
 15718  var Zn_T__Zd_T__1 = []operand{
 15719  	a_ARNG_Zn510Src_SizeHSD2224,
 15720  	a_ARNG_Zd_SizeHSD2224,
 15721  }
 15722  
 15723  var Zn_T__Zd_T__2 = []operand{
 15724  	a_ARNG_Zn510Src_SizeBHSD2224,
 15725  	a_ARNG_Zd_SizeBHSD2224,
 15726  }
 15727  
 15728  var Zn_T__Zm_T__mod_amount___Zd_T = []operand{
 15729  	a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount,
 15730  	a_ARNG_Zd_SzSD2223,
 15731  }
 15732  
 15733  var Zn_T_imm___Zd_T__1 = []operand{
 15734  	a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate,
 15735  	a_ARNG_Zd_Tsz_1621_SizeSpecifier5,
 15736  }
 15737  
 15738  var Zn_T_imm___Zd_T__2 = []operand{
 15739  	a_ARNGIDX_Zn510Src_Tsz_1620_SizeSpecifier4_I1Tsz_Delegate,
 15740  	a_ARNG_Zd_Tsz_1620_SizeSpecifier4,
 15741  }
 15742  
 15743  var Zn_Tb__PgM__Zda_T = []operand{
 15744  	a_ARNG_Zn510V1_SizeTbBHS2224,
 15745  	a_PREGZM_Pg1013_MergePredCheck,
 15746  	a_ARNG_ZdaDest_SizeHSD2224,
 15747  }
 15748  
 15749  var Zn_Tb__Pg__Vd_T__1 = []operand{
 15750  	a_ARNG_Zn510Src_SizeTbBHSD2224,
 15751  	a_PREG_Pg1013_Noop,
 15752  	a_ARNG_Vd_Size16B8H4S2D,
 15753  }
 15754  
 15755  var Zn_Tb__Pg__Vd_T__2 = []operand{
 15756  	a_ARNG_Zn510Src_SizeTbHSD2224Offset1,
 15757  	a_PREG_Pg1013_Noop,
 15758  	a_ARNG_Vd_Size8H4S2D,
 15759  }
 15760  
 15761  var Zn_Tb__Zd_T__1 = []operand{
 15762  	a_ARNG_Zn510Src_SizeTbBHS2224,
 15763  	a_ARNG_Zd_SizeHSD2224,
 15764  }
 15765  
 15766  var Zn_Tb__Zd_T__2 = []operand{
 15767  	a_ARNG_Zn510Src_TszhTszlTbHSD,
 15768  	a_ARNG_Zd_TszhTszlBHS,
 15769  }
 15770  
 15771  var Zn__Pd_B = []operand{
 15772  	a_ZREG_Zn510Src_Noop,
 15773  	a_ARNG_Pd_ArngBCheck,
 15774  }
 15775  
 15776  var Zn__Zd = []operand{
 15777  	a_ZREG_Zn510Src_Noop,
 15778  	a_ZREG_Zd_Noop,
 15779  }
 15780  
 15781  var Zn_imm___Pd_D = []operand{
 15782  	a_ZREGIDX_Zn510Src_Noop_I3hI3l_1722_Doubleword,
 15783  	a_ARNG_Pd_ArngDCheck,
 15784  }
 15785  
 15786  var Zn_imm___Pd_H = []operand{
 15787  	a_ZREGIDX_Zn510Src_Noop_I1_1718_Halfword,
 15788  	a_ARNG_Pd_ArngHCheck,
 15789  }
 15790  
 15791  var Zn_imm___Pd_S = []operand{
 15792  	a_ZREGIDX_Zn510Src_Noop_I2_1719_Word,
 15793  	a_ARNG_Pd_ArngSCheck,
 15794  }
 15795  
 15796  var c0_0__Zn_T__PgZ__Pd_T = []operand{
 15797  	a_IMM_Fimm0_0_56,
 15798  	a_ARNG_Zn510Src_SizeHSD2224,
 15799  	a_PREGZM_Pg1013_ZeroPredCheck,
 15800  	a_ARNG_Pd_SizeHSD2224,
 15801  }
 15802  
 15803  var cconst__PgM__Zd_T = []operand{
 15804  	a_IMM_Imm8_513_Fimm,
 15805  	a_PREGZM_Pg1620_MergePredCheck,
 15806  	a_ARNG_Zd_SizeHSD2224,
 15807  }
 15808  
 15809  var cconst__Zd_T__1 = []operand{
 15810  	a_IMM_Imm13_518,
 15811  	a_ARNG_Zd_SizeImm13NoOp,
 15812  }
 15813  
 15814  var cconst__Zd_T__2 = []operand{
 15815  	a_IMM_Imm8_513_Fimm,
 15816  	a_ARNG_Zd_SizeHSD2224,
 15817  }
 15818  
 15819  var cconst__Zdn_T__PgM__Zdn_T__1 = []operand{
 15820  	a_IMM_ShiftTsz58Range1,
 15821  	a_ARNG_ZdnSrcDst_SizeBhsdTsz810,
 15822  	a_PREGZM_Pg1013_MergePredCheck,
 15823  	a_ARNG_ZdnSrcDst_SizeBhsdTsz810,
 15824  }
 15825  
 15826  var cconst__Zdn_T__PgM__Zdn_T__2 = []operand{
 15827  	a_IMM_ShiftTsz58Range0,
 15828  	a_ARNG_ZdnSrcDst_SizeBhsdTsz810,
 15829  	a_PREGZM_Pg1013_MergePredCheck,
 15830  	a_ARNG_ZdnSrcDst_SizeBhsdTsz810,
 15831  }
 15832  
 15833  var cconst__Zdn_T__Zdn_T = []operand{
 15834  	a_IMM_Imm13_518,
 15835  	a_ARNG_ZdnSrcDst_SizeImm13NoOp,
 15836  	a_ARNG_ZdnSrcDst_SizeImm13NoOp,
 15837  }
 15838  
 15839  var cconst__Zm_T__Zdn_T__Zdn_T = []operand{
 15840  	a_IMM_ShiftTsz1619Range1V2,
 15841  	a_ARNG_Zm510V1_SizeBhsdTsz1921,
 15842  	a_ARNG_ZdnDest_SizeBhsdTsz1921,
 15843  	a_ARNG_ZdnDest_SizeBhsdTsz1921,
 15844  }
 15845  
 15846  var cconst__Zn_T__Zd_T__1 = []operand{
 15847  	a_IMM_ShiftTsz1619Range1V2,
 15848  	a_ARNG_Zn510Src_SizeBhsdTsz1921,
 15849  	a_ARNG_Zd_SizeBhsdTsz1921,
 15850  }
 15851  
 15852  var cconst__Zn_T__Zd_T__2 = []operand{
 15853  	a_IMM_ShiftTsz1619Range0V2,
 15854  	a_ARNG_Zn510Src_SizeBhsdTsz1921,
 15855  	a_ARNG_Zd_SizeBhsdTsz1921,
 15856  }
 15857  
 15858  var cconst__Zn_T__Zda_T = []operand{
 15859  	a_IMM_ShiftTsz1619Range1V2,
 15860  	a_ARNG_Zn510V1_SizeBhsdTsz1921,
 15861  	a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921,
 15862  }
 15863  
 15864  var cconst__Zn_Tb__Zd_T__1 = []operand{
 15865  	a_IMM_ShiftTsz1619Range1V1,
 15866  	a_ARNG_Zn510Src_SizeHsdTsz1921Unique,
 15867  	a_ARNG_Zd_SizeBhsTsz1921,
 15868  }
 15869  
 15870  var cconst__Zn_Tb__Zd_T__2 = []operand{
 15871  	a_IMM_ShiftTsz1619Range0V1,
 15872  	a_ARNG_Zn510Src_SizeBhsTsz1921Unique,
 15873  	a_ARNG_Zd_SizeHsdTsz1921,
 15874  }
 15875  
 15876  var cconst___Zn1_H_Zn2_H___Zd_B = []operand{
 15877  	a_IMM_Imm31619,
 15878  	a_REGLIST_RANGE_Zn610V1_ArngHCheck_Zn610V2_ArngHCheck,
 15879  	a_ARNG_Zd_ArngBCheck,
 15880  }
 15881  
 15882  var cconst___Zn1_S_Zn2_S___Zd_H = []operand{
 15883  	a_IMM_Imm41620V7,
 15884  	a_REGLIST_RANGE_Zn610V1_ArngSCheck_Zn610V2_ArngSCheck,
 15885  	a_ARNG_Zd_ArngHCheck,
 15886  }
 15887  
 15888  var cconst___Zn1_Tb_Zn2_Tb___Zd_T = []operand{
 15889  	a_IMM_Imm3Tsize1621Stub,
 15890  	a_REGLIST_RANGE_Zn610V1_Tsize1921V2_Zn610V2_Tsize1921V2,
 15891  	a_ARNG_Zd_Tsize1921V1,
 15892  }
 15893  
 15894  var cimm2__cimm1__Zd_T = []operand{
 15895  	a_IMM_Imm5bSigned_1621,
 15896  	a_IMM_Imm5Signed_510,
 15897  	a_ARNG_Zd_SizeBHSD2224,
 15898  }
 15899  
 15900  var cimm__Rn__Zd_T = []operand{
 15901  	a_IMM_Imm5Signed_1621V1,
 15902  	a_SPZGREG_Noop_Rn510ZR,
 15903  	a_ARNG_Zd_SizeBHSD2224,
 15904  }
 15905  
 15906  var cimm__Xd = []operand{
 15907  	a_IMM_Imm6Signed_511,
 15908  	a_SPZGREG_Noop_Rd05,
 15909  }
 15910  
 15911  var cimm__XnSP__XdSP = []operand{
 15912  	a_IMM_Imm6Signed_511,
 15913  	a_SPZGREG_XCheck_Rn1621_SPAllowed,
 15914  	a_SPZGREG_XCheck_Rd05_SPAllowed,
 15915  }
 15916  
 15917  var cimm__Zdn_T__Zdn_T__1 = []operand{
 15918  	a_IMM_Imm8Signed_513,
 15919  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 15920  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 15921  }
 15922  
 15923  var cimm__Zdn_T__Zdn_T__2 = []operand{
 15924  	a_IMM_Imm8Unsigned_513,
 15925  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 15926  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 15927  }
 15928  
 15929  var cimm__Zm_B__Zdn_B__Zdn_B__1 = []operand{
 15930  	a_IMM_Imm8hImm8l_Unsigned,
 15931  	a_ARNG_Zm510V1_ArngBCheck,
 15932  	a_ARNG_ZdnDest_ArngBCheck,
 15933  	a_ARNG_ZdnDest_ArngBCheck,
 15934  }
 15935  
 15936  var cimm__Zm_B__Zdn_B__Zdn_B__2 = []operand{
 15937  	a_IMM_Imm4Unsigned_1620,
 15938  	a_ARNG_Zm510V1_ArngBCheck,
 15939  	a_ARNG_ZdnDest_ArngBCheck,
 15940  	a_ARNG_ZdnDest_ArngBCheck,
 15941  }
 15942  
 15943  var cimm__Zm_T__Zdn_T__Zdn_T = []operand{
 15944  	a_IMM_Imm3Unsigned_1619,
 15945  	a_ARNG_Zm510V1_SizeHSD2224,
 15946  	a_ARNG_ZdnDest_SizeHSD2224,
 15947  	a_ARNG_ZdnDest_SizeHSD2224,
 15948  }
 15949  
 15950  var cimm__Zn_T__PgZ__Pd_T__1 = []operand{
 15951  	a_IMM_Imm5Signed_1621V2,
 15952  	a_ARNG_Zn510Src_SizeBHSD2224,
 15953  	a_PREGZM_Pg1013_ZeroPredCheck,
 15954  	a_ARNG_Pd_SizeBHSD2224,
 15955  }
 15956  
 15957  var cimm__Zn_T__PgZ__Pd_T__2 = []operand{
 15958  	a_IMM_Imm7Unsigned_1421,
 15959  	a_ARNG_Zn510Src_SizeBHSD2224,
 15960  	a_PREGZM_Pg1013_ZeroPredCheck,
 15961  	a_ARNG_Pd_SizeBHSD2224,
 15962  }
 15963  
 15964  var cimm___Zn1_B__Zn2_B___Zd_B = []operand{
 15965  	a_IMM_Imm8hImm8l_Unsigned,
 15966  	a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck,
 15967  	a_ARNG_Zd_ArngBCheck,
 15968  }
 15969  
 15970  var cimm__shift__PgM__Zd_T = []operand{
 15971  	a_IMM_Imm8SignedLsl8,
 15972  	a_PREGZM_Pg1620_MergePredCheck,
 15973  	a_ARNG_Zd_SizeBHSD2224,
 15974  }
 15975  
 15976  var cimm__shift__PgZ__Zd_T = []operand{
 15977  	a_IMM_Imm8SignedLsl8,
 15978  	a_PREGZM_Pg1620_ZeroPredCheck,
 15979  	a_ARNG_Zd_SizeBHSD2224,
 15980  }
 15981  
 15982  var cimm__shift__Zd_T = []operand{
 15983  	a_IMM_Imm8SignedLsl8,
 15984  	a_ARNG_Zd_SizeBHSD2224,
 15985  }
 15986  
 15987  var cimm__shift__Zdn_T__Zdn_T = []operand{
 15988  	a_IMM_Imm8UnsignedLsl8,
 15989  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 15990  	a_ARNG_ZdnSrcDst_SizeBHSD2224,
 15991  }
 15992  
 15993  var const__Zdn_T__PgM__Zdn_T__1 = []operand{
 15994  	a_IMM_Fimm0_0_1_0_56,
 15995  	a_ARNG_ZdnSrcDst_SizeHSD2224,
 15996  	a_PREGZM_Pg1013_MergePredCheck,
 15997  	a_ARNG_ZdnSrcDst_SizeHSD2224,
 15998  }
 15999  
 16000  var const__Zdn_T__PgM__Zdn_T__2 = []operand{
 16001  	a_IMM_Fimm0_5_1_0_56,
 16002  	a_ARNG_ZdnSrcDst_SizeHSD2224,
 16003  	a_PREGZM_Pg1013_MergePredCheck,
 16004  	a_ARNG_ZdnSrcDst_SizeHSD2224,
 16005  }
 16006  
 16007  var const__Zdn_T__PgM__Zdn_T__3 = []operand{
 16008  	a_IMM_Fimm0_5_2_0_56,
 16009  	a_ARNG_ZdnSrcDst_SizeHSD2224,
 16010  	a_PREGZM_Pg1013_MergePredCheck,
 16011  	a_ARNG_ZdnSrcDst_SizeHSD2224,
 16012  }
 16013  
 16014  var const__Zm_B_imm___Zn_B__Zda_S = []operand{
 16015  	a_IMM_Rot0_90_180_270_1012,
 16016  	a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit,
 16017  	a_ARNG_Zn510V1_ArngBCheck,
 16018  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 16019  }
 16020  
 16021  var const__Zm_H_imm___Zn_H__Zda_D = []operand{
 16022  	a_IMM_Rot0_90_180_270_1012,
 16023  	a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit,
 16024  	a_ARNG_Zn510V1_ArngHCheck,
 16025  	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 16026  }
 16027  
 16028  var const__Zm_H_imm___Zn_H__Zda_H__1 = []operand{
 16029  	a_IMM_Rot0_90_180_270_1012,
 16030  	a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit,
 16031  	a_ARNG_Zn510V1_ArngHCheck,
 16032  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 16033  }
 16034  
 16035  var const__Zm_H_imm___Zn_H__Zda_H__2 = []operand{
 16036  	a_IMM_Rot0_90_180_270_1012,
 16037  	a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half,
 16038  	a_ARNG_Zn510V1_ArngHCheck,
 16039  	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 16040  }
 16041  
 16042  var const__Zm_S_imm___Zn_S__Zda_S__1 = []operand{
 16043  	a_IMM_Rot0_90_180_270_1012,
 16044  	a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit,
 16045  	a_ARNG_Zn510V1_ArngSCheck,
 16046  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 16047  }
 16048  
 16049  var const__Zm_S_imm___Zn_S__Zda_S__2 = []operand{
 16050  	a_IMM_Rot0_90_180_270_1012,
 16051  	a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single,
 16052  	a_ARNG_Zn510V1_ArngSCheck,
 16053  	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 16054  }
 16055  
 16056  var const__Zm_T__Zdn_T__PgM__Zdn_T = []operand{
 16057  	a_IMM_Rot90_270_1617,
 16058  	a_ARNG_Zm510V1_SizeHSD2224,
 16059  	a_ARNG_ZdnDest_SizeHSD2224,
 16060  	a_PREGZM_Pg1013_MergePredCheck,
 16061  	a_ARNG_ZdnDest_SizeHSD2224,
 16062  }
 16063  
 16064  var const__Zm_T__Zdn_T__Zdn_T = []operand{
 16065  	a_IMM_Rot90_270_1011,
 16066  	a_ARNG_Zm510V1_SizeBHSD2224,
 16067  	a_ARNG_ZdnDest_SizeBHSD2224,
 16068  	a_ARNG_ZdnDest_SizeBHSD2224,
 16069  }
 16070  
 16071  var const__Zm_T__Zn_T__PgM__Zda_T = []operand{
 16072  	a_IMM_Rot0_90_180_270_1315,
 16073  	a_ARNG_Zm1621V2_SizeHSD2224,
 16074  	a_ARNG_Zn510V1_SizeHSD2224,
 16075  	a_PREGZM_Pg1013_MergePredCheck,
 16076  	a_ARNG_Zda3RdSrcDst_SizeHSD2224,
 16077  }
 16078  
 16079  var const__Zm_T__Zn_T__Zda_T = []operand{
 16080  	a_IMM_Rot0_90_180_270_1012,
 16081  	a_ARNG_Zm1621V2_SizeBHSD2224,
 16082  	a_ARNG_Zn510V1_SizeBHSD2224,
 16083  	a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
 16084  }
 16085  
 16086  var const__Zm_Tb__Zn_Tb__Zda_T = []operand{
 16087  	a_IMM_Rot0_90_180_270_1012,
 16088  	a_ARNG_Zm1621V2_Size0TbBH2223,
 16089  	a_ARNG_Zn510V1_Size0TbBH2223,
 16090  	a_ARNG_Zda3RdSrcDst_Size0SD2223,
 16091  }
 16092  
 16093  var oc = []operand{}
 16094  
 16095  var vl__PNn_T__Xd = []operand{
 16096  	a_SPECIAL_Vl1011,
 16097  	a_ARNG_PNn59_SizeBHSD2224,
 16098  	a_SPZGREG_Noop_Rd05,
 16099  }
 16100  
 16101  var vl__Xm__Xn__PNd_T = []operand{
 16102  	a_SPECIAL_Vl1314,
 16103  	a_SPZGREG_Noop_Rm1621V1,
 16104  	a_SPZGREG_Noop_Rn510,
 16105  	a_ARNG_PNd_SizeBHSD2224,
 16106  }
 16107