Source file src/cmd/internal/obj/arm64/encoding_gen.go
1 // Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'. 2 3 package arm64 4 5 import "cmd/internal/obj" 6 7 // stripRawZ first checks if v is a raw register number(0 to 31). 8 // If v is not a raw Z register, it will check if it's a Z register in the ARM64 range: 9 // - if within the range, it returns true, and set v to be the raw Z register. 10 // - otherwise it returns false 11 // 12 // If v is a raw register number, it returns true and leaves v unchanged. 13 func stripRawZ(v *uint32) bool { 14 if *v >= obj.RBaseARM64 { 15 if !(*v >= REG_Z0 && *v <= REG_Z31) && !(*v >= REG_ZARNG && *v < REG_ZARNGELEM) { 16 return false 17 } 18 } 19 *v = *v & 31 20 return true 21 } 22 23 // checkIsR checks if v is a scalar register: 24 // - if v is a raw register number or is within the ARM64 scalar register range, 25 // it returns true. 26 // - otherwise it returns false. 27 func checkIsR(v uint32) bool { 28 if v > REG_R31 && v != REG_RSP { 29 return false 30 } 31 return true 32 } 33 34 const ( 35 enc_NIL component = iota 36 enc_i1_tsz 37 enc_i2h_i2l 38 enc_i3h_i3l 39 enc_i4h_i4l 40 enc_imm2_tsz 41 enc_imm8h_imm8l 42 enc_imm9h_imm9l 43 enc_tsize_imm3 44 enc_tszh_tszl_imm3 45 enc_tszh_tszl 46 enc_M 47 enc_PNd 48 enc_PNg 49 enc_PNn 50 enc_Pd 51 enc_Pdm 52 enc_Pdn 53 enc_Pg 54 enc_Pm 55 enc_Pn 56 enc_Pt 57 enc_Pv 58 enc_Rd 59 enc_Rdn 60 enc_Rm 61 enc_Rn 62 enc_Vd 63 enc_Vdn 64 enc_Vm 65 enc_Vn 66 enc_Za 67 enc_Zd 68 enc_Zda 69 enc_Zdn 70 enc_Zk 71 enc_Zm 72 enc_Zn 73 enc_Zt 74 enc_i1 75 enc_i2 76 enc_imm13 77 enc_imm2 78 enc_imm3 79 enc_imm4 80 enc_imm5 81 enc_imm5b 82 enc_imm6 83 enc_imm7 84 enc_imm8 85 enc_msz 86 enc_prfop 87 enc_rot 88 enc_size 89 enc_size0 90 enc_sz 91 enc_tsize 92 enc_tsz 93 enc_vl 94 enc_xs 95 ) 96 97 // encodeNoModCheck is the implementation of the following encoding logic: 98 // Check that there is no modifier (UXTW, SXTW, LSL) 99 func encodeNoModCheck(v uint32) (uint32, bool) { 100 return 0, v == 0 101 } 102 103 // encodeNoAmtCheck is the implementation of the following encoding logic: 104 // Check that there is no modifier amount 105 func encodeNoAmtCheck(v uint32) (uint32, bool) { 106 return 0, v == 0 107 } 108 109 // encodeXCheck is the implementation of the following encoding logic: 110 // Check this is a 64-bit scalar register 111 func encodeXCheck(v uint32) (uint32, bool) { 112 return 0, true 113 } 114 115 // encodeArngBCheck is the implementation of the following encoding logic: 116 // Check this is a B arrangement 117 func encodeArngBCheck(v uint32) (uint32, bool) { 118 if v == ARNG_B { 119 return 0, true 120 } 121 return 0, false 122 } 123 124 // encodeArngDCheck is the implementation of the following encoding logic: 125 // Check this is a D arrangement 126 func encodeArngDCheck(v uint32) (uint32, bool) { 127 if v == ARNG_D { 128 return 0, true 129 } 130 return 0, false 131 } 132 133 // encodeArngHCheck is the implementation of the following encoding logic: 134 // Check this is a H arrangement 135 func encodeArngHCheck(v uint32) (uint32, bool) { 136 if v == ARNG_H { 137 return 0, true 138 } 139 return 0, false 140 } 141 142 // encodeArngQCheck is the implementation of the following encoding logic: 143 // Check this is a Q arrangement 144 func encodeArngQCheck(v uint32) (uint32, bool) { 145 if v == ARNG_Q { 146 return 0, true 147 } 148 return 0, false 149 } 150 151 // encodeArngSCheck is the implementation of the following encoding logic: 152 // Check this is a S arrangement 153 func encodeArngSCheck(v uint32) (uint32, bool) { 154 if v == ARNG_S { 155 return 0, true 156 } 157 return 0, false 158 } 159 160 // encodeMergePredCheck is the implementation of the following encoding logic: 161 // Check this is a merging predication 162 func encodeMergePredCheck(v uint32) (uint32, bool) { 163 if v == PRED_M { 164 return 0, true 165 } 166 return 0, false 167 } 168 169 // encodeZeroPredCheck is the implementation of the following encoding logic: 170 // Check this is a zeroing predication 171 func encodeZeroPredCheck(v uint32) (uint32, bool) { 172 if v == PRED_Z { 173 return 0, true 174 } 175 return 0, false 176 } 177 178 // encodeFimm0_0_56 is the implementation of the following encoding logic: 179 // Check this is immediate 0.0 180 func encodeFimm0_0_56(v uint32) (uint32, bool) { 181 if (v & 0x7FFFFFFF) != 0 { 182 return 0, false 183 } 184 return 0, true 185 } 186 187 // encodeModAmt1Check is the implementation of the following encoding logic: 188 // Check this is mod amount and is 1 189 func encodeModAmt1Check(v uint32) (uint32, bool) { 190 if v == 1 { 191 return 0, true 192 } 193 return 0, false 194 } 195 196 // encodeModAmt2Check is the implementation of the following encoding logic: 197 // Check this is mod amount and is 2 198 func encodeModAmt2Check(v uint32) (uint32, bool) { 199 if v == 2 { 200 return 0, true 201 } 202 return 0, false 203 } 204 205 // encodeModAmt3Check is the implementation of the following encoding logic: 206 // Check this is mod amount and is 3 207 func encodeModAmt3Check(v uint32) (uint32, bool) { 208 if v == 3 { 209 return 0, true 210 } 211 return 0, false 212 } 213 214 // encodeModAmt4Check is the implementation of the following encoding logic: 215 // Check this is mod amount and is 4 216 func encodeModAmt4Check(v uint32) (uint32, bool) { 217 if v == 4 { 218 return 0, true 219 } 220 return 0, false 221 } 222 223 // encodeModLSLCheck is the implementation of the following encoding logic: 224 // Check this is mod and is LSL 225 func encodeModLSLCheck(v uint32) (uint32, bool) { 226 if v&0b100 != 0 { 227 return 0, true 228 } 229 return 0, false 230 } 231 232 // encodeModSXTWCheck is the implementation of the following encoding logic: 233 // Check this is mod and is SXTW 234 func encodeModSXTWCheck(v uint32) (uint32, bool) { 235 if v&0b10 != 0 { 236 return 0, true 237 } 238 return 0, false 239 } 240 241 // encodeModUXTWCheck is the implementation of the following encoding logic: 242 // Check this is mod and is UXTW 243 func encodeModUXTWCheck(v uint32) (uint32, bool) { 244 if v&0b1 != 0 { 245 return 0, true 246 } 247 return 0, false 248 } 249 250 // encodeI2_1921_16To32Bit is the implementation of the following encoding logic: 251 // For the "16-bit to 32-bit" variant: is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. 252 // bit range mappings: 253 // i2: [19:21) 254 func encodeI2_1921_16To32Bit(v uint32) (uint32, bool) { 255 if v > 3 { 256 return 0, false 257 } 258 return v << 19, true 259 } 260 261 // encodeI1_2021_16To64Bit is the implementation of the following encoding logic: 262 // For the "16-bit to 64-bit" variant: is the immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment, in the range 0 to 1, encoded in the "i1" field. 263 // bit range mappings: 264 // i1: [20:21) 265 func encodeI1_2021_16To64Bit(v uint32) (uint32, bool) { 266 if v > 1 { 267 return 0, false 268 } 269 return v << 20, true 270 } 271 272 // encodeZm1620_16To64Bit is the implementation of the following encoding logic: 273 // For the "16-bit to 64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. 274 // bit range mappings: 275 // Zm: [16:20) 276 func encodeZm1620_16To64Bit(v uint32) (uint32, bool) { 277 if !stripRawZ(&v) { 278 return 0, false 279 } 280 if v > 15 { 281 return 0, false 282 } 283 return v << 16, true 284 } 285 286 // encodeZm1619_16Bit32Bit is the implementation of the following encoding logic: 287 // For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. 288 // bit range mappings: 289 // Zm: [16:19) 290 func encodeZm1619_16Bit32Bit(v uint32) (uint32, bool) { 291 if !stripRawZ(&v) { 292 return 0, false 293 } 294 if v > 7 { 295 return 0, false 296 } 297 return v << 16, true 298 } 299 300 // encodeI2_1921_16bit is the implementation of the following encoding logic: 301 // For the "16-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field. 302 // bit range mappings: 303 // i2: [19:21) 304 func encodeI2_1921_16bit(v uint32) (uint32, bool) { 305 if v > 3 { 306 return 0, false 307 } 308 return v << 19, true 309 } 310 311 // encodeI3hI3l_1923_16Bit is the implementation of the following encoding logic: 312 // For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields. 313 // bit range mappings: 314 // i3h: [22:23) 315 // i3l: [19:21) 316 func encodeI3hI3l_1923_16Bit(v uint32) (uint32, bool) { 317 if v > 7 { 318 return 0, false 319 } 320 return (v&3)<<19 | (v>>2)<<22, true 321 } 322 323 // encodeImm41620V7 is the implementation of the following encoding logic: 324 // For the "16-bit" variant: is the immediate shift amount, in the range 1 to 16, encoded in the "imm4" field. 325 // bit range mappings: 326 // imm4: [16:20) 327 func encodeImm41620V7(v uint32) (uint32, bool) { 328 if v < 1 || v > 16 { 329 return 0, false 330 } 331 // From ARM ASL: let shift : integer = esize - UInt(imm3); 332 // very weird design. 333 return (16 - v) << 16, true 334 } 335 336 // encodeZm_1619_Range0_7V1 is the implementation of the following encoding logic: 337 // For the "16-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. 338 // bit range mappings: 339 // Zm: [16:19) 340 func encodeZm_1619_Range0_7V1(v uint32) (uint32, bool) { 341 if !stripRawZ(&v) { 342 return 0, false 343 } 344 if v <= 7 { 345 return v << 16, true 346 } 347 return 0, false 348 } 349 350 // encodeI1_2021_32bit is the implementation of the following encoding logic: 351 // For the "32-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field. 352 // bit range mappings: 353 // i1: [20:21) 354 func encodeI1_2021_32bit(v uint32) (uint32, bool) { 355 if v > 1 { 356 return 0, false 357 } 358 return v << 20, true 359 } 360 361 // encodeI2_1921_32Bit is the implementation of the following encoding logic: 362 // For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field. 363 // bit range mappings: 364 // i2: [19:21) 365 func encodeI2_1921_32Bit(v uint32) (uint32, bool) { 366 if v > 3 { 367 return 0, false 368 } 369 return v << 19, true 370 } 371 372 // encodeI3hI3l_1119_32Bit is the implementation of the following encoding logic: 373 // For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields. 374 // bit range mappings: 375 // i3h: [19:21) 376 // i3l: [11:12) 377 func encodeI3hI3l_1119_32Bit(v uint32) (uint32, bool) { 378 if v > 7 { 379 return 0, false 380 } 381 return (v&1)<<11 | (v>>1)<<19, true 382 } 383 384 // encodeZm_1620_Range0_15 is the implementation of the following encoding logic: 385 // For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. 386 // bit range mappings: 387 // Zm: [16:20) 388 func encodeZm_1620_Range0_15(v uint32) (uint32, bool) { 389 if !stripRawZ(&v) { 390 return 0, false 391 } 392 if v <= 15 { 393 return v << 16, true 394 } 395 return 0, false 396 } 397 398 // encodeZm1619_32Bit is the implementation of the following encoding logic: 399 // For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. 400 // bit range mappings: 401 // Zm: [16:19) 402 func encodeZm1619_32Bit(v uint32) (uint32, bool) { 403 if !stripRawZ(&v) { 404 return 0, false 405 } 406 if v > 7 { 407 return 0, false 408 } 409 return v << 16, true 410 } 411 412 // encodeI1_2021_64Bit is the implementation of the following encoding logic: 413 // For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field. 414 // bit range mappings: 415 // i1: [20:21) 416 func encodeI1_2021_64Bit(v uint32) (uint32, bool) { 417 if v > 1 { 418 return 0, false 419 } 420 return v << 20, true 421 } 422 423 // encodeI2hI2l_1120_64Bit is the implementation of the following encoding logic: 424 // For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields. 425 // bit range mappings: 426 // i2h: [20:21) 427 // i2l: [11:12) 428 func encodeI2hI2l_1120_64Bit(v uint32) (uint32, bool) { 429 if v > 3 { 430 return 0, false 431 } 432 return (v&1)<<11 | (v>>1)<<20, true 433 } 434 435 // encodeZm1620_64Bit is the implementation of the following encoding logic: 436 // For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. 437 // bit range mappings: 438 // Zm: [16:20) 439 func encodeZm1620_64Bit(v uint32) (uint32, bool) { 440 if !stripRawZ(&v) { 441 return 0, false 442 } 443 if v > 15 { 444 return 0, false 445 } 446 return v << 16, true 447 } 448 449 // encodeI3hI3l_1923_8To16Bit is the implementation of the following encoding logic: 450 // For the "8-bit to 16-bit" variant: is the immediate index of a pair of 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields. 451 // bit range mappings: 452 // i3h: [22:23) 453 // i3l: [19:21) 454 func encodeI3hI3l_1923_8To16Bit(v uint32) (uint32, bool) { 455 if v > 7 { 456 return 0, false 457 } 458 return (v&3)<<19 | (v>>2)<<22, true 459 } 460 461 // encodeI2_1921_8To32Bit is the implementation of the following encoding logic: 462 // For the "8-bit to 32-bit" variant: is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. 463 // bit range mappings: 464 // i2: [19:21) 465 func encodeI2_1921_8To32Bit(v uint32) (uint32, bool) { 466 if v > 3 { 467 return 0, false 468 } 469 return v << 19, true 470 } 471 472 // encodeZm1619_8To32Bit is the implementation of the following encoding logic: 473 // For the "8-bit to 32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. 474 // bit range mappings: 475 // Zm: [16:19) 476 func encodeZm1619_8To32Bit(v uint32) (uint32, bool) { 477 if !stripRawZ(&v) { 478 return 0, false 479 } 480 if v > 7 { 481 return 0, false 482 } 483 return v << 16, true 484 } 485 486 // encodeImm31619 is the implementation of the following encoding logic: 487 // For the "8-bit" variant: is the immediate shift amount, in the range 1 to 8, encoded in the "imm3" field. 488 // bit range mappings: 489 // imm3: [16:19) 490 func encodeImm31619(v uint32) (uint32, bool) { 491 if v < 1 || v > 8 { 492 return 0, false 493 } 494 return v << 16, true 495 } 496 497 // encodeSzByteHalfword is the implementation of the following encoding logic: 498 // For the "Byte and halfword" variant: is the size specifier, 499 // sz <T> 500 // 0 B 501 // 1 H 502 // bit range mappings: 503 // sz: [22:23) 504 func encodeSzByteHalfword(v uint32) (uint32, bool) { 505 switch v { 506 case ARNG_B: 507 return 0, true 508 case ARNG_H: 509 return 1 << 22, true 510 } 511 return 0, false 512 } 513 514 // encodeI22224 is the implementation of the following encoding logic: 515 // For the "Byte" variant: is the vector segment index, in the range 0 to 3, encoded in the "i2" field. 516 // bit range mappings: 517 // i2: [22:24) 518 func encodeI22224(v uint32) (uint32, bool) { 519 if v > 3 { 520 return 0, false 521 } 522 return v << 22, true 523 } 524 525 // encodeSizeByteMergeZero is the implementation of the following encoding logic: 526 // For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier, 527 // size <T> 528 // 00 RESERVED 529 // 01 H 530 // 10 S 531 // 11 D 532 // bit range mappings: 533 // size: [22:24) 534 func encodeSizeByteMergeZero(v uint32) (uint32, bool) { 535 switch v { 536 case ARNG_H: 537 return 1 << 22, true 538 case ARNG_S: 539 return 2 << 22, true 540 case ARNG_D: 541 return 3 << 22, true 542 } 543 return 0, false 544 } 545 546 // encodeI12324B is the implementation of the following encoding logic: 547 // For the "Byte, single register table" variant: is the vector segment index, in the range 0 to 1, encoded in the "i1" field. 548 // bit range mappings: 549 // i1: [23:24) 550 func encodeI12324B(v uint32) (uint32, bool) { 551 if v > 1 { 552 return 0, false 553 } 554 return v << 23, true 555 } 556 557 // encodeI1_2021_DoublePrecision is the implementation of the following encoding logic: 558 // For the "Double-precision" variant: is the immediate index, in the range 0 to 1, encoded in the "i1" field. 559 // bit range mappings: 560 // i1: [20:21) 561 func encodeI1_2021_DoublePrecision(v uint32) (uint32, bool) { 562 if v > 1 { 563 return 0, false 564 } 565 return v << 20, true 566 } 567 568 // encodeZm1620_DoublePrecision is the implementation of the following encoding logic: 569 // For the "Double-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. 570 // bit range mappings: 571 // Zm: [16:20) 572 func encodeZm1620_DoublePrecision(v uint32) (uint32, bool) { 573 if !stripRawZ(&v) { 574 return 0, false 575 } 576 if v > 15 { 577 return 0, false 578 } 579 return v << 16, true 580 } 581 582 // encodeI3hI3l_1722_Doubleword is the implementation of the following encoding logic: 583 // For the "Doubleword" variant: is the optional portion index, in the range 0 to 7, defaulting to 0, encoded in the "i3h:i3l" fields. 584 // bit range mappings: 585 // i3h: [22:23) 586 // i3l: [17:19) 587 func encodeI3hI3l_1722_Doubleword(v uint32) (uint32, bool) { 588 if v > 7 { 589 return 0, false 590 } 591 return (v&3)<<17 | (v>>2)<<22, true 592 } 593 594 // encodeImm5Signed_1621V2 is the implementation of the following encoding logic: 595 // For the "Equal", "Greater than or equal", "Greater than", "Less than or equal", "Less than", and "Not equal" variants: is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. 596 // bit range mappings: 597 // imm5: [16:21) 598 func encodeImm5Signed_1621V2(v uint32) (uint32, bool) { 599 if int32(v) >= -16 && int32(v) <= 15 { 600 return (v & 31) << 16, true 601 } 602 return 0, false 603 } 604 605 // encodeZdn25V1 is the implementation of the following encoding logic: 606 // For the "Four registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4. 607 // bit range mappings: 608 // Zdn: [2:5) 609 func encodeZdn25V1(v uint32) (uint32, bool) { 610 if !stripRawZ(&v) { 611 return 0, false 612 } 613 if v%4 != 0 { 614 return 0, false 615 } 616 return (v / 4) << 2, true 617 } 618 619 // encodeZt25V1 is the implementation of the following encoding logic: 620 // For the "Four registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4. 621 // bit range mappings: 622 // Zt: [2:5) 623 func encodeZt25V1(v uint32) (uint32, bool) { 624 if !stripRawZ(&v) { 625 return 0, false 626 } 627 if v%4 != 0 { 628 return 0, false 629 } 630 return (v / 4) << 2, true 631 } 632 633 // encodeImm41620V8 is the implementation of the following encoding logic: 634 // For the "Four registers" variant: is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field. 635 // bit range mappings: 636 // imm4: [16:20) 637 func encodeImm41620V8(v uint32) (uint32, bool) { 638 val := int32(v) 639 if val < -32 || val > 28 || val%4 != 0 { 640 return 0, false 641 } 642 encoded := uint32((val >> 2) & 0xf) 643 return encoded << 16, true 644 } 645 646 // encodeZm1619_HalfSinglePrecision is the implementation of the following encoding logic: 647 // For the "Half-precision" and "Single-precision" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. 648 // bit range mappings: 649 // Zm: [16:19) 650 func encodeZm1619_HalfSinglePrecision(v uint32) (uint32, bool) { 651 if !stripRawZ(&v) { 652 return 0, false 653 } 654 if v > 7 { 655 return 0, false 656 } 657 return v << 16, true 658 } 659 660 // encodeI3hI3l_1923_HalfPrecision is the implementation of the following encoding logic: 661 // For the "Half-precision" variant: is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields. 662 // bit range mappings: 663 // i3h: [22:23) 664 // i3l: [19:21) 665 func encodeI3hI3l_1923_HalfPrecision(v uint32) (uint32, bool) { 666 if v > 7 { 667 return 0, false 668 } 669 return (v&3)<<19 | (v>>2)<<22, true 670 } 671 672 // encodeI2_1921_Half is the implementation of the following encoding logic: 673 // For the "Half-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 3, encoded in the "i2" field. 674 // bit range mappings: 675 // i2: [19:21) 676 func encodeI2_1921_Half(v uint32) (uint32, bool) { 677 if v > 3 { 678 return 0, false 679 } 680 return v << 19, true 681 } 682 683 // encodeZm_1619_Half is the implementation of the following encoding logic: 684 // For the "Half-precision" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. 685 // bit range mappings: 686 // Zm: [16:19) 687 func encodeZm_1619_Half(v uint32) (uint32, bool) { 688 if !stripRawZ(&v) { 689 return 0, false 690 } 691 if v <= 7 { 692 return v << 16, true 693 } 694 return 0, false 695 } 696 697 // encodeI1_1718_Halfword is the implementation of the following encoding logic: 698 // For the "Halfword" variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field. 699 // bit range mappings: 700 // i1: [17:18) 701 func encodeI1_1718_Halfword(v uint32) (uint32, bool) { 702 if v > 1 { 703 return 0, false 704 } 705 return v << 17, true 706 } 707 708 // encodeI3224I31213 is the implementation of the following encoding logic: 709 // For the "Halfword" variant: is the vector segment index, in the range 0 to 7, encoded in the "i3h:i3l" fields. 710 // bit range mappings: 711 // i3h: [22:24) 712 // i3l: [12:13) 713 func encodeI3224I31213(v uint32) (uint32, bool) { 714 if v > 7 { 715 return 0, false 716 } 717 return (v&1)<<12 | (v>>1)<<22, true 718 } 719 720 // encodeSize0HalfwordMergeZero is the implementation of the following encoding logic: 721 // For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier, 722 // size[0] <T> 723 // 0 S 724 // 1 D 725 // bit range mappings: 726 // size: [22:23) 727 func encodeSize0HalfwordMergeZero(v uint32) (uint32, bool) { 728 switch v { 729 case ARNG_S: 730 return 0, true 731 case ARNG_D: 732 return 1 << 22, true 733 } 734 return 0, false 735 } 736 737 // encodeI22224HW is the implementation of the following encoding logic: 738 // For the "Halfword, single register table" and "Halfword, two register table" variants: is the vector segment index, in the range 0 to 3, encoded in the "i2" field. 739 // bit range mappings: 740 // i2: [22:24) 741 func encodeI22224HW(v uint32) (uint32, bool) { 742 if v > 3 { 743 return 0, false 744 } 745 return v << 22, true 746 } 747 748 // encodeImm7Unsigned_1421 is the implementation of the following encoding logic: 749 // For the "Higher or same", "Higher", "Lower or same", and "Lower" variants: is the unsigned immediate operand, in the range 0 to 127, encoded in the "imm7" field. 750 // bit range mappings: 751 // imm7: [14:21) 752 func encodeImm7Unsigned_1421(v uint32) (uint32, bool) { 753 if v <= 127 { 754 return v << 14, true 755 } 756 return 0, false 757 } 758 759 // encodeI2_1921_SinglePrecision is the implementation of the following encoding logic: 760 // For the "Single-precision" variant: is the immediate index, in the range 0 to 3, encoded in the "i2" field. 761 // bit range mappings: 762 // i2: [19:21) 763 func encodeI2_1921_SinglePrecision(v uint32) (uint32, bool) { 764 if v > 3 { 765 return 0, false 766 } 767 return v << 19, true 768 } 769 770 // encodeI1_2021_Single is the implementation of the following encoding logic: 771 // For the "Single-precision" variant: is the index of a Real and Imaginary pair, in the range 0 to 1, encoded in the "i1" field. 772 // bit range mappings: 773 // i1: [20:21) 774 func encodeI1_2021_Single(v uint32) (uint32, bool) { 775 if v > 1 { 776 return 0, false 777 } 778 return v << 20, true 779 } 780 781 // encodeZm_1620_Single is the implementation of the following encoding logic: 782 // For the "Single-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. 783 // bit range mappings: 784 // Zm: [16:20) 785 func encodeZm_1620_Single(v uint32) (uint32, bool) { 786 if !stripRawZ(&v) { 787 return 0, false 788 } 789 if v <= 15 { 790 return v << 16, true 791 } 792 return 0, false 793 } 794 795 // encodeZdn15V1 is the implementation of the following encoding logic: 796 // For the "Two registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2. 797 // bit range mappings: 798 // Zdn: [1:5) 799 func encodeZdn15V1(v uint32) (uint32, bool) { 800 if !stripRawZ(&v) { 801 return 0, false 802 } 803 if v%2 != 0 { 804 return 0, false 805 } 806 return (v / 2) << 1, true 807 } 808 809 // encodeZt15V1 is the implementation of the following encoding logic: 810 // For the "Two registers" variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2. 811 // bit range mappings: 812 // Zt: [1:5) 813 func encodeZt15V1(v uint32) (uint32, bool) { 814 if !stripRawZ(&v) { 815 return 0, false 816 } 817 if v%2 != 0 { 818 return 0, false 819 } 820 return (v / 2) << 1, true 821 } 822 823 // encodeImm41620V9 is the implementation of the following encoding logic: 824 // For the "Two registers" variant: is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field. 825 // bit range mappings: 826 // imm4: [16:20) 827 func encodeImm41620V9(v uint32) (uint32, bool) { 828 val := int32(v) 829 if val < -16 || val > 14 || val%2 != 0 { 830 return 0, false 831 } 832 encoded := uint32((val>>1)&0xf) << 16 833 return encoded, true 834 } 835 836 // encodeSzWordDoubleword is the implementation of the following encoding logic: 837 // For the "Word and doubleword" variant: is the size specifier, 838 // sz <T> 839 // 0 S 840 // 1 D 841 // bit range mappings: 842 // sz: [22:23) 843 func encodeSzWordDoubleword(v uint32) (uint32, bool) { 844 switch v { 845 case ARNG_S: 846 return 0, true 847 case ARNG_D: 848 return 1 << 22, true 849 } 850 return 0, false 851 } 852 853 // encodeI2_1719_Word is the implementation of the following encoding logic: 854 // For the "Word" variant: is the optional portion index, in the range 0 to 3, defaulting to 0, encoded in the "i2" field. 855 // bit range mappings: 856 // i2: [17:19) 857 func encodeI2_1719_Word(v uint32) (uint32, bool) { 858 if v > 3 { 859 return 0, false 860 } 861 return v << 17, true 862 } 863 864 // encodeImm13_518 is the implementation of the following encoding logic: 865 // Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field. 866 // bit range mappings: 867 // imm13: [5:18) 868 func encodeImm13_518(v uint32) (uint32, bool) { 869 return codeLogicalImmArrEncoding, false 870 } 871 872 // encodeImm8_513_Fimm is the implementation of the following encoding logic: 873 // Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field. 874 // bit range mappings: 875 // imm8: [5:13) 876 func encodeImm8_513_Fimm(v uint32) (uint32, bool) { 877 if v <= 255 { 878 return v << 5, true 879 } 880 return 0, false 881 } 882 883 // encodeImm8SignedLsl8 is the implementation of the following encoding logic: 884 // Is a signed immediate in the range -128 to 127, encoded in the "imm8" field. 885 // bit range mappings: 886 // imm8: [5:13) 887 // 888 // Is the optional left shift to apply to the immediate, defaulting to LSL #0 and 889 // sh <shift> 890 // 0 LSL #0 891 // 1 LSL #8 892 // bit range mappings: 893 // sh: [13:14) 894 func encodeImm8SignedLsl8(v uint32) (uint32, bool) { 895 vi := int32(v) 896 if vi >= -128 && vi <= 127 { 897 imm8 := uint32(uint8(int8(vi))) 898 return (imm8 << 5), true 899 } 900 if vi&255 == 0 { 901 unshifted := vi >> 8 902 if unshifted >= -128 && unshifted <= 127 { 903 imm8 := uint32(uint8(int8(unshifted))) 904 return (imm8 << 5) | (1 << 13), true 905 } 906 } 907 return 0, false 908 } 909 910 // encodeSize16B8H4S2D is the implementation of the following encoding logic: 911 // Is an arrangement specifier, 912 // size <T> 913 // 00 16B 914 // 01 8H 915 // 10 4S 916 // 11 2D 917 // bit range mappings: 918 // size: [22:24) 919 func encodeSize16B8H4S2D(v uint32) (uint32, bool) { 920 switch v { 921 case ARNG_16B: 922 return 0, true 923 case ARNG_8H: 924 return 1 << 22, true 925 case ARNG_4S: 926 return 2 << 22, true 927 case ARNG_2D: 928 return 3 << 22, true 929 } 930 return 0, false 931 } 932 933 // encodeSize8H4S2D is the implementation of the following encoding logic: 934 // Is an arrangement specifier, 935 // size <T> 936 // 00 RESERVED 937 // 01 8H 938 // 10 4S 939 // 11 2D 940 // bit range mappings: 941 // size: [22:24) 942 func encodeSize8H4S2D(v uint32) (uint32, bool) { 943 switch v { 944 case ARNG_8H: 945 return 1 << 22, true 946 case ARNG_4S: 947 return 2 << 22, true 948 case ARNG_2D: 949 return 3 << 22, true 950 } 951 return 0, false 952 } 953 954 // encodeImm8UnsignedLsl8 is the implementation of the following encoding logic: 955 // Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field. 956 // bit range mappings: 957 // imm8: [5:13) 958 // 959 // Is the optional left shift to apply to the immediate, defaulting to LSL #0 and 960 // sh <shift> 961 // 0 LSL #0 962 // 1 LSL #8 963 // bit range mappings: 964 // sh: [13:14) 965 func encodeImm8UnsignedLsl8(v uint32) (uint32, bool) { 966 if v <= 255 { 967 return v << 5, true 968 } 969 if v&255 == 0 { 970 unshifted := v >> 8 971 if unshifted <= 255 { 972 return (unshifted << 5) | (1 << 13), true 973 } 974 } 975 return 0, false 976 } 977 978 // encodeWdn05 is the implementation of the following encoding logic: 979 // Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. 980 // bit range mappings: 981 // Rdn: [0:5) 982 func encodeWdn05(v uint32) (uint32, bool) { 983 if !checkIsR(v) { 984 return 0, false 985 } 986 if v == REG_RSP { 987 return 0, false 988 } 989 return v & 31, true 990 } 991 992 // encodeVd0564 is the implementation of the following encoding logic: 993 // Is the 64-bit name of the destination SIMD&FP register, encoded in the "Vd" field. 994 // bit range mappings: 995 // Vd: [0:5) 996 func encodeVd0564(v uint32) (uint32, bool) { 997 return v & 31, true 998 } 999 1000 // encodeRd05_SPAllowed is the implementation of the following encoding logic: 1001 // Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field. 1002 // bit range mappings: 1003 // Rd: [0:5) 1004 func encodeRd05_SPAllowed(v uint32) (uint32, bool) { 1005 if !checkIsR(v) { 1006 return 0, false 1007 } 1008 if v == REG_R31 { 1009 return 0, false 1010 } 1011 if v == REG_RSP { 1012 return 31, true 1013 } 1014 return v & 31, true 1015 } 1016 1017 // encodeRd05 is the implementation of the following encoding logic: 1018 // Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field. 1019 // bit range mappings: 1020 // Rd: [0:5) 1021 func encodeRd05(v uint32) (uint32, bool) { 1022 if !checkIsR(v) { 1023 return 0, false 1024 } 1025 if v == REG_RSP { 1026 return 0, false 1027 } 1028 return v & 31, true 1029 } 1030 1031 // encodeRn510 is the implementation of the following encoding logic: 1032 // Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field. 1033 // bit range mappings: 1034 // Rn: [5:10) 1035 func encodeRn510(v uint32) (uint32, bool) { 1036 if !checkIsR(v) { 1037 return 0, false 1038 } 1039 if v == REG_RSP { 1040 return 0, false 1041 } 1042 return (v & 31) << 5, true 1043 } 1044 1045 // encodeRn510SPV2 is the implementation of the following encoding logic: 1046 // Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. 1047 // bit range mappings: 1048 // Rn: [5:10) 1049 func encodeRn510SPV2(v uint32) (uint32, bool) { 1050 if !checkIsR(v) { 1051 return 0, false 1052 } 1053 if v == REG_R31 { 1054 return 0, false 1055 } 1056 if v == REG_RSP { 1057 return 31 << 5, true 1058 } 1059 return (v & 31) << 5, true 1060 } 1061 1062 // encodeRm1621V2 is the implementation of the following encoding logic: 1063 // Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. 1064 // bit range mappings: 1065 // Rm: [16:21) 1066 func encodeRm1621V2(v uint32) (uint32, bool) { 1067 if !checkIsR(v) { 1068 return 0, false 1069 } 1070 if v == REG_RSP { 1071 return 0, false 1072 } 1073 return (v & 31) << 16, true 1074 } 1075 1076 // encodeRm1621V1 is the implementation of the following encoding logic: 1077 // Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field. 1078 // bit range mappings: 1079 // Rm: [16:21) 1080 func encodeRm1621V1(v uint32) (uint32, bool) { 1081 if !checkIsR(v) { 1082 return 0, false 1083 } 1084 if v == REG_RSP { 1085 return 0, false 1086 } 1087 return (v & 31) << 16, true 1088 } 1089 1090 // encodeXdn05 is the implementation of the following encoding logic: 1091 // Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field. 1092 // bit range mappings: 1093 // Rdn: [0:5) 1094 func encodeXdn05(v uint32) (uint32, bool) { 1095 if !checkIsR(v) { 1096 return 0, false 1097 } 1098 if v == REG_RSP { 1099 return 0, false 1100 } 1101 return v & 31, true 1102 } 1103 1104 // encodeRn1621_SPAllowed is the implementation of the following encoding logic: 1105 // Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. 1106 // bit range mappings: 1107 // Rn: [16:21) 1108 func encodeRn1621_SPAllowed(v uint32) (uint32, bool) { 1109 if !checkIsR(v) { 1110 return 0, false 1111 } 1112 if v == REG_R31 { 1113 return 0, false 1114 } 1115 if v == REG_RSP { 1116 return 31 << 16, true 1117 } 1118 return (v & 31) << 16, true 1119 } 1120 1121 // encodeRot90_270_1011 is the implementation of the following encoding logic: 1122 // Is the const specifier, 1123 // rot <const> 1124 // 0 #90 1125 // 1 #270 1126 // bit range mappings: 1127 // rot: [10:11) 1128 func encodeRot90_270_1011(v uint32) (uint32, bool) { 1129 switch v { 1130 case 90: 1131 return 0, true 1132 case 270: 1133 return 1 << 10, true 1134 } 1135 return 0, false 1136 } 1137 1138 // encodeRot90_270_1617 is the implementation of the following encoding logic: 1139 // Is the const specifier, 1140 // rot <const> 1141 // 0 #90 1142 // 1 #270 1143 // bit range mappings: 1144 // rot: [16:17) 1145 func encodeRot90_270_1617(v uint32) (uint32, bool) { 1146 switch v { 1147 case 90: 1148 return 0, true 1149 case 270: 1150 return 1 << 16, true 1151 } 1152 return 0, false 1153 } 1154 1155 // encodeRot0_90_180_270_1012 is the implementation of the following encoding logic: 1156 // Is the const specifier, 1157 // rot <const> 1158 // 00 #0 1159 // 01 #90 1160 // 10 #180 1161 // 11 #270 1162 // bit range mappings: 1163 // rot: [10:12) 1164 func encodeRot0_90_180_270_1012(v uint32) (uint32, bool) { 1165 switch v { 1166 case 0: 1167 return 0, true 1168 case 90: 1169 return 1 << 10, true 1170 case 180: 1171 return 2 << 10, true 1172 case 270: 1173 return 3 << 10, true 1174 } 1175 return 0, false 1176 } 1177 1178 // encodeRot0_90_180_270_1315 is the implementation of the following encoding logic: 1179 // Is the const specifier, 1180 // rot <const> 1181 // 00 #0 1182 // 01 #90 1183 // 10 #180 1184 // 11 #270 1185 // bit range mappings: 1186 // rot: [13:15) 1187 func encodeRot0_90_180_270_1315(v uint32) (uint32, bool) { 1188 switch v { 1189 case 0: 1190 return 0, true 1191 case 90: 1192 return 1 << 13, true 1193 case 180: 1194 return 2 << 13, true 1195 case 270: 1196 return 3 << 13, true 1197 } 1198 return 0, false 1199 } 1200 1201 // encodeImm5Signed_510 is the implementation of the following encoding logic: 1202 // Is the first signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. 1203 // bit range mappings: 1204 // imm5: [5:10) 1205 func encodeImm5Signed_510(v uint32) (uint32, bool) { 1206 if int32(v) >= -16 && int32(v) <= 15 { 1207 return (v & 31) << 5, true 1208 } 1209 return 0, false 1210 } 1211 1212 // encodeFimm0_0_1_0_56 is the implementation of the following encoding logic: 1213 // Is the floating-point immediate value, 1214 // i1 <const> 1215 // 0 #0.0 1216 // 1 #1.0 1217 // bit range mappings: 1218 // i1: [5:6) 1219 func encodeFimm0_0_1_0_56(v uint32) (uint32, bool) { 1220 switch v { 1221 case 0: 1222 return 0, true 1223 case 0x3F800000: // 1.0 1224 return 1 << 5, true 1225 } 1226 return 0, false 1227 } 1228 1229 // encodeFimm0_5_1_0_56 is the implementation of the following encoding logic: 1230 // Is the floating-point immediate value, 1231 // i1 <const> 1232 // 0 #0.5 1233 // 1 #1.0 1234 // bit range mappings: 1235 // i1: [5:6) 1236 func encodeFimm0_5_1_0_56(v uint32) (uint32, bool) { 1237 switch v { 1238 case 0x3F000000: // 0.5 1239 return 0, true 1240 case 0x3F800000: // 1.0 1241 return 1 << 5, true 1242 } 1243 return 0, false 1244 } 1245 1246 // encodeFimm0_5_2_0_56 is the implementation of the following encoding logic: 1247 // Is the floating-point immediate value, 1248 // i1 <const> 1249 // 0 #0.5 1250 // 1 #2.0 1251 // bit range mappings: 1252 // i1: [5:6) 1253 func encodeFimm0_5_2_0_56(v uint32) (uint32, bool) { 1254 switch v { 1255 case 0x3F000000: // 0.5 1256 return 0, true 1257 case 0x40000000: // 2.0 1258 return 1 << 5, true 1259 } 1260 return 0, false 1261 } 1262 1263 // encodeI2_1921_8BitGroup is the implementation of the following encoding logic: 1264 // Is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. 1265 // bit range mappings: 1266 // i2: [19:21) 1267 func encodeI2_1921_8BitGroup(v uint32) (uint32, bool) { 1268 if v > 3 { 1269 return 0, false 1270 } 1271 return v << 19, true 1272 } 1273 1274 // encodeI2_1921_Pair16Bit is the implementation of the following encoding logic: 1275 // Is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. 1276 // bit range mappings: 1277 // i2: [19:21) 1278 func encodeI2_1921_Pair16Bit(v uint32) (uint32, bool) { 1279 if v > 3 { 1280 return 0, false 1281 } 1282 return v << 19, true 1283 } 1284 1285 // encodeI3hI3l_1119_Pair8Bit is the implementation of the following encoding logic: 1286 // Is the immediate index of a pair of 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields. 1287 // bit range mappings: 1288 // i3h: [19:21) 1289 // i3l: [11:12) 1290 func encodeI3hI3l_1119_Pair8Bit(v uint32) (uint32, bool) { 1291 if v > 7 { 1292 return 0, false 1293 } 1294 return (v&1)<<11 | (v>>1)<<19, true 1295 } 1296 1297 // encodeI4hI4l_1019 is the implementation of the following encoding logic: 1298 // Is the immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields. 1299 // bit range mappings: 1300 // i4h: [19:21) 1301 // i4l: [10:12) 1302 func encodeI4hI4l_1019(v uint32) (uint32, bool) { 1303 if v > 15 { 1304 return 0, false 1305 } 1306 return (v&3)<<10 | (v>>2)<<19, true 1307 } 1308 1309 // encodeI3hI3l_1119 is the implementation of the following encoding logic: 1310 // Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields. 1311 // bit range mappings: 1312 // i3h: [19:21) 1313 // i3l: [11:12) 1314 func encodeI3hI3l_1119(v uint32) (uint32, bool) { 1315 if v > 7 { 1316 return 0, false 1317 } 1318 return (v&1)<<11 | (v>>1)<<19, true 1319 } 1320 1321 // encodeI3hI3l_1922 is the implementation of the following encoding logic: 1322 // Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields. 1323 // bit range mappings: 1324 // i3h: [22:23) 1325 // i3l: [19:21) 1326 func encodeI3hI3l_1922(v uint32) (uint32, bool) { 1327 if v > 7 { 1328 return 0, false 1329 } 1330 return (v&3)<<19 | (v>>2)<<22, true 1331 } 1332 1333 // encodeI1Tsz_Delegate is the implementation of the following encoding logic: 1334 // Is the immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz". 1335 // bit range mappings: 1336 // i1: [20:21) 1337 // tsz: [16:20) 1338 func encodeI1Tsz_Delegate(v uint32) (uint32, bool) { 1339 // The statement "range 0 to one less than the number of elements in 128 bits" 1340 // is not possible to handle here, we delegate this to the caller. 1341 return codeI1Tsz, false 1342 } 1343 1344 // encodeImm2Tsz_Delegate is the implementation of the following encoding logic: 1345 // Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz". 1346 // bit range mappings: 1347 // imm2: [22:24) 1348 // tsz: [16:21) 1349 func encodeImm2Tsz_Delegate(v uint32) (uint32, bool) { 1350 // The statement "range 0 to one less than the number of elements in 512 bits" 1351 // is not possible to handle here, we delegate this to the caller. 1352 return codeImm2Tsz, false 1353 } 1354 1355 // encodeShiftTsz1619Range0V1 is the implementation of the following encoding logic: 1356 // Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". 1357 // bit range mappings: 1358 // imm3: [16:19) 1359 // tszh: [22:23) 1360 // tszl: [19:21) 1361 func encodeShiftTsz1619Range0V1(v uint32) (uint32, bool) { 1362 return codeShift161919212223, false 1363 } 1364 1365 // encodeShiftTsz1619Range0V2 is the implementation of the following encoding logic: 1366 // Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". 1367 // bit range mappings: 1368 // imm3: [16:19) 1369 // tszh: [22:24) 1370 // tszl: [19:21) 1371 func encodeShiftTsz1619Range0V2(v uint32) (uint32, bool) { 1372 return codeShift161919212224, false 1373 } 1374 1375 // encodeShiftTsz58Range0 is the implementation of the following encoding logic: 1376 // Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3". 1377 // bit range mappings: 1378 // imm3: [5:8) 1379 // tszh: [22:24) 1380 // tszl: [8:10) 1381 func encodeShiftTsz58Range0(v uint32) (uint32, bool) { 1382 return codeShift588102224, false 1383 } 1384 1385 // encodeImm3Tsize1621Stub is the implementation of the following encoding logic: 1386 // Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsize:imm3". 1387 // bit range mappings: 1388 // imm3: [16:19) 1389 // tsize: [19:21) 1390 func encodeImm3Tsize1621Stub(v uint32) (uint32, bool) { 1391 return codeImm3Tsize1621, false 1392 } 1393 1394 // encodeShiftTsz1619Range1V1 is the implementation of the following encoding logic: 1395 // Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". 1396 // bit range mappings: 1397 // imm3: [16:19) 1398 // tszh: [22:23) 1399 // tszl: [19:21) 1400 func encodeShiftTsz1619Range1V1(v uint32) (uint32, bool) { 1401 return codeShift161919212223, false 1402 } 1403 1404 // encodeShiftTsz1619Range1V2 is the implementation of the following encoding logic: 1405 // Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". 1406 // bit range mappings: 1407 // imm3: [16:19) 1408 // tszh: [22:24) 1409 // tszl: [19:21) 1410 func encodeShiftTsz1619Range1V2(v uint32) (uint32, bool) { 1411 return codeShift161919212224, false 1412 } 1413 1414 // encodeShiftTsz58Range1 is the implementation of the following encoding logic: 1415 // Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". 1416 // bit range mappings: 1417 // imm3: [5:8) 1418 // tszh: [22:24) 1419 // tszl: [8:10) 1420 func encodeShiftTsz58Range1(v uint32) (uint32, bool) { 1421 return codeShift588102224, false 1422 } 1423 1424 // encodeMsz1012 is the implementation of the following encoding logic: 1425 // Is the index extend and shift specifier, 1426 // msz <mod> 1427 // 00 [absent] 1428 // x1 LSL 1429 // 10 LSL 1430 // bit range mappings: 1431 // msz: [10:12) 1432 func encodeMsz1012(v uint32) (uint32, bool) { 1433 // This does not accept UXTW and SXTW, check that 1434 if v&0b11 != 0 { 1435 return 0, false 1436 } 1437 // Note: this encoding function's semantic is entailed by its peer that 1438 // encode <amount>, so just do nothing. 1439 return codeNoOp, false 1440 } 1441 1442 // encodeXs1415 is the implementation of the following encoding logic: 1443 // Is the index extend and shift specifier, 1444 // xs <mod> 1445 // 0 UXTW 1446 // 1 SXTW 1447 // bit range mappings: 1448 // xs: [14:15) 1449 func encodeXs1415(v uint32) (uint32, bool) { 1450 if v&0b1 != 0 { 1451 return 0, true 1452 } else if v&0b10 != 0 { 1453 return 1 << 14, true 1454 } 1455 return 0, false 1456 } 1457 1458 // encodeXs2223 is the implementation of the following encoding logic: 1459 // Is the index extend and shift specifier, 1460 // xs <mod> 1461 // 0 UXTW 1462 // 1 SXTW 1463 // bit range mappings: 1464 // xs: [22:23) 1465 func encodeXs2223(v uint32) (uint32, bool) { 1466 if v&0b1 != 0 { 1467 return 0, true 1468 } else if v&0b10 != 0 { 1469 return 1 << 22, true 1470 } 1471 return 0, false 1472 } 1473 1474 // encodeMsz1012Amount is the implementation of the following encoding logic: 1475 // Is the index shift amount, 1476 // msz <amount> 1477 // 00 [absent] 1478 // 01 #1 1479 // 10 #2 1480 // 11 #3 1481 // bit range mappings: 1482 // msz: [10:12) 1483 func encodeMsz1012Amount(v uint32) (uint32, bool) { 1484 if v <= 3 { 1485 return v << 10, true 1486 } 1487 return 0, false 1488 } 1489 1490 // encodeZn510V2 is the implementation of the following encoding logic: 1491 // Is the name of the base scalable vector register, encoded in the "Zn" field. 1492 // bit range mappings: 1493 // Zn: [5:10) 1494 func encodeZn510V2(v uint32) (uint32, bool) { 1495 if !stripRawZ(&v) { 1496 return 0, false 1497 } 1498 return v << 5, true 1499 } 1500 1501 // encodeVd is the implementation of the following encoding logic: 1502 // Is the name of the destination SIMD&FP register, encoded in the "Vd" field. 1503 // bit range mappings: 1504 // Vd: [0:5) 1505 func encodeVd(v uint32) (uint32, bool) { 1506 return v & 31, true 1507 } 1508 1509 // encodePNd is the implementation of the following encoding logic: 1510 // Is the name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field. 1511 // bit range mappings: 1512 // PNd: [0:3) 1513 func encodePNd(v uint32) (uint32, bool) { 1514 if v >= 24 && v <= 31 { 1515 // PN registers starts from 16. 1516 return v - 24, true 1517 } 1518 return 0, false 1519 } 1520 1521 // encodePd is the implementation of the following encoding logic: 1522 // Is the name of the destination scalable predicate register, encoded in the "Pd" field. 1523 // bit range mappings: 1524 // Pd: [0:4) 1525 func encodePd(v uint32) (uint32, bool) { 1526 return v, true 1527 } 1528 1529 // encodePt04V1 is the implementation of the following encoding logic: 1530 // Is the name of the destination scalable predicate register, encoded in the "Pt" field. 1531 // bit range mappings: 1532 // Pt: [0:4) 1533 func encodePt04V1(v uint32) (uint32, bool) { 1534 if v > 15 { 1535 return 0, false 1536 } 1537 return v, true 1538 } 1539 1540 // encodeZd is the implementation of the following encoding logic: 1541 // Is the name of the destination scalable vector register, encoded in the "Zd" field. 1542 // bit range mappings: 1543 // Zd: [0:5) 1544 func encodeZd(v uint32) (uint32, bool) { 1545 if !stripRawZ(&v) { 1546 return 0, false 1547 } 1548 return v, true 1549 } 1550 1551 // encodePd14 is the implementation of the following encoding logic: 1552 // Is the name of the first destination scalable predicate register, encoded as "Pd" times 2. 1553 // bit range mappings: 1554 // Pd: [1:4) 1555 func encodePd14(v uint32) (uint32, bool) { 1556 if v > 14 { 1557 return 0, false 1558 } 1559 if v&1 != 0 { 1560 return 0, false 1561 } 1562 return v, true 1563 } 1564 1565 // encodePd04 is the implementation of the following encoding logic: 1566 // Is the name of the first destination scalable predicate register, encoded in the "Pd" field. 1567 // bit range mappings: 1568 // Pd: [0:4) 1569 func encodePd04(v uint32) (uint32, bool) { 1570 return v, true 1571 } 1572 1573 // encodeZd15V1 is the implementation of the following encoding logic: 1574 // Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. 1575 // bit range mappings: 1576 // Zd: [1:5) 1577 func encodeZd15V1(v uint32) (uint32, bool) { 1578 if !stripRawZ(&v) { 1579 return 0, false 1580 } 1581 if v%2 != 0 { 1582 return 0, false 1583 } 1584 return (v / 2) << 1, true 1585 } 1586 1587 // encodeZda15V1 is the implementation of the following encoding logic: 1588 // Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zda" times 2. 1589 // bit range mappings: 1590 // Zda: [1:5) 1591 func encodeZda15V1(v uint32) (uint32, bool) { 1592 if !stripRawZ(&v) { 1593 return 0, false 1594 } 1595 if v%2 != 0 { 1596 return 0, false 1597 } 1598 return (v / 2) << 1, true 1599 } 1600 1601 // encodeGenZn510V1 is the implementation of the following encoding logic: 1602 // Is the name of the first scalable vector register of the first source multi-vector group, encoded in the "Zn" field. 1603 // bit range mappings: 1604 // Zn: [5:10) 1605 func encodeGenZn510V1(v uint32) (uint32, bool) { 1606 if !stripRawZ(&v) { 1607 return 0, false 1608 } 1609 return v << 5, true 1610 } 1611 1612 // encodeZn610V1 is the implementation of the following encoding logic: 1613 // Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. 1614 // bit range mappings: 1615 // Zn: [6:10) 1616 func encodeZn610V1(v uint32) (uint32, bool) { 1617 if !stripRawZ(&v) { 1618 return 0, false 1619 } 1620 if v%2 != 0 { 1621 return 0, false 1622 } 1623 return (v / 2) << 6, true 1624 } 1625 1626 // encodeZn510MultiSrc1 is the implementation of the following encoding logic: 1627 // Is the name of the first scalable vector register of the source multi-vector group, encoded in the "Zn" field. 1628 // bit range mappings: 1629 // Zn: [5:10) 1630 func encodeZn510MultiSrc1(v uint32) (uint32, bool) { 1631 if !stripRawZ(&v) { 1632 return 0, false 1633 } 1634 return v << 5, true 1635 } 1636 1637 // encodeZt051 is the implementation of the following encoding logic: 1638 // Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. 1639 // bit range mappings: 1640 // Zt: [0:5) 1641 func encodeZt051(v uint32) (uint32, bool) { 1642 if !stripRawZ(&v) { 1643 return 0, false 1644 } 1645 return v, true 1646 } 1647 1648 // encodePdnDest is the implementation of the following encoding logic: 1649 // Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field. 1650 // bit range mappings: 1651 // Pdn: [0:4) 1652 func encodePdnDest(v uint32) (uint32, bool) { 1653 return v, true 1654 } 1655 1656 // encodeZdnDest is the implementation of the following encoding logic: 1657 // Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. 1658 // bit range mappings: 1659 // Zdn: [0:5) 1660 func encodeZdnDest(v uint32) (uint32, bool) { 1661 if !stripRawZ(&v) { 1662 return 0, false 1663 } 1664 return v, true 1665 } 1666 1667 // encodePnN_58 is the implementation of the following encoding logic: 1668 // Is the name of the first source scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNn" field. 1669 // bit range mappings: 1670 // PNn: [5:8) 1671 func encodePnN_58(v uint32) (uint32, bool) { 1672 if v >= 24 && v <= 31 { 1673 // PN registers starts from 16. 1674 return (v - 24) << 5, true 1675 } 1676 return 0, false 1677 } 1678 1679 // encodePn59 is the implementation of the following encoding logic: 1680 // Is the name of the first source scalable predicate register, encoded in the "Pn" field. 1681 // bit range mappings: 1682 // Pn: [5:9) 1683 func encodePn59(v uint32) (uint32, bool) { 1684 return v << 5, true 1685 } 1686 1687 // encodeZn510V1 is the implementation of the following encoding logic: 1688 // Is the name of the first source scalable vector register, encoded in the "Zn" field. 1689 // bit range mappings: 1690 // Zn: [5:10) 1691 func encodeZn510V1(v uint32) (uint32, bool) { 1692 if !stripRawZ(&v) { 1693 return 0, false 1694 } 1695 return v << 5, true 1696 } 1697 1698 // encodeZn510Table1 is the implementation of the following encoding logic: 1699 // Is the name of the first table vector register, encoded as "Zn". 1700 // bit range mappings: 1701 // Zn: [5:10) 1702 func encodeZn510Table1(v uint32) (uint32, bool) { 1703 return v << 5, true 1704 } 1705 1706 // encodeZdn25V2 is the implementation of the following encoding logic: 1707 // Is the name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3. 1708 // bit range mappings: 1709 // Zdn: [2:5) 1710 func encodeZdn25V2(v uint32) (uint32, bool) { 1711 if !stripRawZ(&v) { 1712 return 0, false 1713 } 1714 if v < 3 || (v-3)%4 != 0 { 1715 return 0, false 1716 } 1717 return ((v - 3) / 4) << 2, true 1718 } 1719 1720 // encodeZt054 is the implementation of the following encoding logic: 1721 // Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32. 1722 // bit range mappings: 1723 // Zt: [0:5) 1724 func encodeZt054(v uint32) (uint32, bool) { 1725 if !stripRawZ(&v) { 1726 return 0, false 1727 } 1728 return (v - 3) % 32, true 1729 } 1730 1731 // encodeZt25V2 is the implementation of the following encoding logic: 1732 // Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3. 1733 // bit range mappings: 1734 // Zt: [2:5) 1735 func encodeZt25V2(v uint32) (uint32, bool) { 1736 if !stripRawZ(&v) { 1737 return 0, false 1738 } 1739 if v < 3 || (v-3)%4 != 0 { 1740 return 0, false 1741 } 1742 return ((v - 3) / 4) << 2, true 1743 } 1744 1745 // encodePg1013 is the implementation of the following encoding logic: 1746 // Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. 1747 // bit range mappings: 1748 // Pg: [10:13) 1749 func encodePg1013(v uint32) (uint32, bool) { 1750 if v <= 7 { 1751 return v << 10, true 1752 } 1753 return 0, false 1754 } 1755 1756 // encodePNg1013 is the implementation of the following encoding logic: 1757 // Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field. 1758 // bit range mappings: 1759 // PNg: [10:13) 1760 func encodePNg1013(v uint32) (uint32, bool) { 1761 if v < 24 { 1762 return 0, false 1763 } 1764 return (v - 24) << 10, true 1765 } 1766 1767 // encodePg1014 is the implementation of the following encoding logic: 1768 // Is the name of the governing scalable predicate register, encoded in the "Pg" field. 1769 // bit range mappings: 1770 // Pg: [10:14) 1771 func encodePg1014(v uint32) (uint32, bool) { 1772 return v << 10, true 1773 } 1774 1775 // encodePg1620 is the implementation of the following encoding logic: 1776 // Is the name of the governing scalable predicate register, encoded in the "Pg" field. 1777 // bit range mappings: 1778 // Pg: [16:20) 1779 func encodePg1620(v uint32) (uint32, bool) { 1780 return v << 16, true 1781 } 1782 1783 // encodePg59 is the implementation of the following encoding logic: 1784 // Is the name of the governing scalable predicate register, encoded in the "Pg" field. 1785 // bit range mappings: 1786 // Pg: [5:9) 1787 func encodePg59(v uint32) (uint32, bool) { 1788 return v << 5, true 1789 } 1790 1791 // encodeZm1621V3 is the implementation of the following encoding logic: 1792 // Is the name of the offset scalable vector register, encoded in the "Zm" field. 1793 // bit range mappings: 1794 // Zm: [16:21) 1795 func encodeZm1621V3(v uint32) (uint32, bool) { 1796 if !stripRawZ(&v) { 1797 return 0, false 1798 } 1799 return v << 16, true 1800 } 1801 1802 // encodePt04V2 is the implementation of the following encoding logic: 1803 // Is the name of the scalable predicate transfer register, encoded in the "Pt" field. 1804 // bit range mappings: 1805 // Pt: [0:4) 1806 func encodePt04V2(v uint32) (uint32, bool) { 1807 if v > 15 { 1808 return 0, false 1809 } 1810 return v, true 1811 } 1812 1813 // encodeZt05 is the implementation of the following encoding logic: 1814 // Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. 1815 // bit range mappings: 1816 // Zt: [0:5) 1817 func encodeZt05(v uint32) (uint32, bool) { 1818 if !stripRawZ(&v) { 1819 return 0, false 1820 } 1821 return v, true 1822 } 1823 1824 // encodePd14Plus1 is the implementation of the following encoding logic: 1825 // Is the name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1. 1826 // bit range mappings: 1827 // Pd: [1:4) 1828 func encodePd14Plus1(v uint32) (uint32, bool) { 1829 if v&1 == 0 { 1830 return 0, false 1831 } 1832 return v - 1, true 1833 } 1834 1835 // encodePd04Plus1 is the implementation of the following encoding logic: 1836 // Is the name of the second destination scalable predicate register, encoded in the "Pd" field. 1837 // bit range mappings: 1838 // Pd: [0:4) 1839 func encodePd04Plus1(v uint32) (uint32, bool) { 1840 // This "second destination" incurs Pd + 1 == v 1841 return v - 1, true 1842 } 1843 1844 // encodeZdn15V2 is the implementation of the following encoding logic: 1845 // Is the name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1. 1846 // bit range mappings: 1847 // Zdn: [1:5) 1848 func encodeZdn15V2(v uint32) (uint32, bool) { 1849 if !stripRawZ(&v) { 1850 return 0, false 1851 } 1852 if v < 1 || (v-1)%2 != 0 { 1853 return 0, false 1854 } 1855 return ((v - 1) / 2) << 1, true 1856 } 1857 1858 // encodeZd15V2 is the implementation of the following encoding logic: 1859 // Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. 1860 // bit range mappings: 1861 // Zd: [1:5) 1862 func encodeZd15V2(v uint32) (uint32, bool) { 1863 if !stripRawZ(&v) { 1864 return 0, false 1865 } 1866 if v%2 == 0 { 1867 return 0, false 1868 } 1869 return ((v - 1) / 2) << 1, true 1870 } 1871 1872 // encodeZda15V2 is the implementation of the following encoding logic: 1873 // Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zda" times 2 plus 1. 1874 // bit range mappings: 1875 // Zda: [1:5) 1876 func encodeZda15V2(v uint32) (uint32, bool) { 1877 if !stripRawZ(&v) { 1878 return 0, false 1879 } 1880 if v%2 == 0 { 1881 return 0, false 1882 } 1883 return ((v - 1) / 2) << 1, true 1884 } 1885 1886 // encodeGenZn510V2 is the implementation of the following encoding logic: 1887 // Is the name of the second scalable vector register of the first source multi-vector group, encoded in the "Zn" field. 1888 // bit range mappings: 1889 // Zn: [5:10) 1890 func encodeGenZn510V2(v uint32) (uint32, bool) { 1891 if !stripRawZ(&v) { 1892 return 0, false 1893 } 1894 return (v - 1) << 5, true 1895 } 1896 1897 // encodeZn610V2 is the implementation of the following encoding logic: 1898 // Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. 1899 // bit range mappings: 1900 // Zn: [6:10) 1901 func encodeZn610V2(v uint32) (uint32, bool) { 1902 if !stripRawZ(&v) { 1903 return 0, false 1904 } 1905 if v%2 == 0 { 1906 return 0, false 1907 } 1908 return ((v - 1) / 2) << 6, true 1909 } 1910 1911 // encodeZn510MultiSrc2 is the implementation of the following encoding logic: 1912 // Is the name of the second scalable vector register of the source multi-vector group, encoded in the "Zn" field. 1913 // bit range mappings: 1914 // Zn: [5:10) 1915 func encodeZn510MultiSrc2(v uint32) (uint32, bool) { 1916 if !stripRawZ(&v) { 1917 return 0, false 1918 } 1919 return (v - 1) << 5, true 1920 } 1921 1922 // encodeZt052 is the implementation of the following encoding logic: 1923 // Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. 1924 // bit range mappings: 1925 // Zt: [0:5) 1926 func encodeZt052(v uint32) (uint32, bool) { 1927 if !stripRawZ(&v) { 1928 return 0, false 1929 } 1930 return (v - 1) % 32, true 1931 } 1932 1933 // encodeZt15V2 is the implementation of the following encoding logic: 1934 // Is the name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1. 1935 // bit range mappings: 1936 // Zt: [1:5) 1937 func encodeZt15V2(v uint32) (uint32, bool) { 1938 if !stripRawZ(&v) { 1939 return 0, false 1940 } 1941 if v < 1 || (v-1)%2 != 0 { 1942 return 0, false 1943 } 1944 return ((v - 1) / 2) << 1, true 1945 } 1946 1947 // encodePdmDest is the implementation of the following encoding logic: 1948 // Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field. 1949 // bit range mappings: 1950 // Pdm: [0:4) 1951 func encodePdmDest(v uint32) (uint32, bool) { 1952 return v, true 1953 } 1954 1955 // encodeZdaDest is the implementation of the following encoding logic: 1956 // Is the name of the second source and destination scalable vector register, encoded in the "Zda" field. 1957 // bit range mappings: 1958 // Zda: [0:5) 1959 func encodeZdaDest(v uint32) (uint32, bool) { 1960 if !stripRawZ(&v) { 1961 return 0, false 1962 } 1963 return v, true 1964 } 1965 1966 // encodePm1620 is the implementation of the following encoding logic: 1967 // Is the name of the second source scalable predicate register, encoded in the "Pm" field. 1968 // bit range mappings: 1969 // Pm: [16:20) 1970 func encodePm1620(v uint32) (uint32, bool) { 1971 return v << 16, true 1972 } 1973 1974 // encodeZm_1619_Range0_7V2 is the implementation of the following encoding logic: 1975 // Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. 1976 // bit range mappings: 1977 // Zm: [16:19) 1978 func encodeZm_1619_Range0_7V2(v uint32) (uint32, bool) { 1979 if v <= 7 { 1980 return v << 16, true 1981 } 1982 return 0, false 1983 } 1984 1985 // encodeZm1621V2 is the implementation of the following encoding logic: 1986 // Is the name of the second source scalable vector register, encoded in the "Zm" field. 1987 // bit range mappings: 1988 // Zm: [16:21) 1989 func encodeZm1621V2(v uint32) (uint32, bool) { 1990 if !stripRawZ(&v) { 1991 return 0, false 1992 } 1993 return v << 16, true 1994 } 1995 1996 // encodeZm510V1 is the implementation of the following encoding logic: 1997 // Is the name of the second source scalable vector register, encoded in the "Zm" field. 1998 // bit range mappings: 1999 // Zm: [5:10) 2000 func encodeZm510V1(v uint32) (uint32, bool) { 2001 if !stripRawZ(&v) { 2002 return 0, false 2003 } 2004 return (v & 31) << 5, true 2005 } 2006 2007 // encodeZn510Table2 is the implementation of the following encoding logic: 2008 // Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32. 2009 // bit range mappings: 2010 // Zn: [5:10) 2011 func encodeZn510Table2(v uint32) (uint32, bool) { 2012 return ((v - 1) & 0x1f) << 5, true 2013 } 2014 2015 // encodePdnSrcDst is the implementation of the following encoding logic: 2016 // Is the name of the source and destination scalable predicate register, encoded in the "Pdn" field. 2017 // bit range mappings: 2018 // Pdn: [0:4) 2019 func encodePdnSrcDst(v uint32) (uint32, bool) { 2020 return v, true 2021 } 2022 2023 // encodeZdnSrcDst is the implementation of the following encoding logic: 2024 // Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. 2025 // bit range mappings: 2026 // Zdn: [0:5) 2027 func encodeZdnSrcDst(v uint32) (uint32, bool) { 2028 if !stripRawZ(&v) { 2029 return 0, false 2030 } 2031 return v, true 2032 } 2033 2034 // encodePm59V1 is the implementation of the following encoding logic: 2035 // Is the name of the source scalable predicate register, encoded in the "Pm" field. 2036 // bit range mappings: 2037 // Pm: [5:9) 2038 func encodePm59V1(v uint32) (uint32, bool) { 2039 return v << 5, true 2040 } 2041 2042 // encodePn59V2 is the implementation of the following encoding logic: 2043 // Is the name of the source scalable predicate register, encoded in the "Pn" field. 2044 // bit range mappings: 2045 // Pn: [5:9) 2046 func encodePn59V2(v uint32) (uint32, bool) { 2047 return v << 5, true 2048 } 2049 2050 // encodePNn59 is the implementation of the following encoding logic: 2051 // Is the name of the source scalable predicate register, with predicate-as-counter encoding, encoded in the "PNn" field. 2052 // bit range mappings: 2053 // PNn: [5:9) 2054 func encodePNn59(v uint32) (uint32, bool) { 2055 if v > 15 { 2056 return (v - 16) << 5, true 2057 } 2058 return 0, false 2059 } 2060 2061 // encodeZm1621V1 is the implementation of the following encoding logic: 2062 // Is the name of the source scalable vector register, encoded in the "Zm" field. 2063 // bit range mappings: 2064 // Zm: [16:21) 2065 func encodeZm1621V1(v uint32) (uint32, bool) { 2066 if !stripRawZ(&v) { 2067 return 0, false 2068 } 2069 return v << 16, true 2070 } 2071 2072 // encodeZm510V2 is the implementation of the following encoding logic: 2073 // Is the name of the source scalable vector register, encoded in the "Zm" field. 2074 // bit range mappings: 2075 // Zm: [5:10) 2076 func encodeZm510V2(v uint32) (uint32, bool) { 2077 if !stripRawZ(&v) { 2078 return 0, false 2079 } 2080 return (v & 31) << 5, true 2081 } 2082 2083 // encodeZn510Src is the implementation of the following encoding logic: 2084 // Is the name of the source scalable vector register, encoded in the "Zn" field. 2085 // bit range mappings: 2086 // Zn: [5:10) 2087 func encodeZn510Src(v uint32) (uint32, bool) { 2088 if !stripRawZ(&v) { 2089 return 0, false 2090 } 2091 return (v & 31) << 5, true 2092 } 2093 2094 // encodeZn510Table3 is the implementation of the following encoding logic: 2095 // Is the name of the table vector register, encoded in the "Zn" field. 2096 // bit range mappings: 2097 // Zn: [5:10) 2098 func encodeZn510Table3(v uint32) (uint32, bool) { 2099 return v << 5, true 2100 } 2101 2102 // encodeZt053 is the implementation of the following encoding logic: 2103 // Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32. 2104 // bit range mappings: 2105 // Zt: [0:5) 2106 func encodeZt053(v uint32) (uint32, bool) { 2107 if !stripRawZ(&v) { 2108 return 0, false 2109 } 2110 return (v - 2) % 32, true 2111 } 2112 2113 // encodeZda3RdSrcDst is the implementation of the following encoding logic: 2114 // Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. 2115 // bit range mappings: 2116 // Zda: [0:5) 2117 func encodeZda3RdSrcDst(v uint32) (uint32, bool) { 2118 if !stripRawZ(&v) { 2119 return 0, false 2120 } 2121 return v, true 2122 } 2123 2124 // encodeZa16213Rd is the implementation of the following encoding logic: 2125 // Is the name of the third source scalable vector register, encoded in the "Za" field. 2126 // bit range mappings: 2127 // Za: [16:21) 2128 func encodeZa16213Rd(v uint32) (uint32, bool) { 2129 if !stripRawZ(&v) { 2130 return 0, false 2131 } 2132 return v << 16, true 2133 } 2134 2135 // encodeZa5103Rd is the implementation of the following encoding logic: 2136 // Is the name of the third source scalable vector register, encoded in the "Za" field. 2137 // bit range mappings: 2138 // Za: [5:10) 2139 func encodeZa5103Rd(v uint32) (uint32, bool) { 2140 if !stripRawZ(&v) { 2141 return 0, false 2142 } 2143 return v << 5, true 2144 } 2145 2146 // encodeZk5103Rd is the implementation of the following encoding logic: 2147 // Is the name of the third source scalable vector register, encoded in the "Zk" field. 2148 // bit range mappings: 2149 // Zk: [5:10) 2150 func encodeZk5103Rd(v uint32) (uint32, bool) { 2151 if !stripRawZ(&v) { 2152 return 0, false 2153 } 2154 return v << 5, true 2155 } 2156 2157 // encodePv1013 is the implementation of the following encoding logic: 2158 // Is the name of the vector select predicate register P0-P7, encoded in the "Pv" field. 2159 // bit range mappings: 2160 // Pv: [10:13) 2161 func encodePv1013(v uint32) (uint32, bool) { 2162 return v << 10, true 2163 } 2164 2165 // encodePv1014 is the implementation of the following encoding logic: 2166 // Is the name of the vector select predicate register, encoded in the "Pv" field. 2167 // bit range mappings: 2168 // Pv: [10:14) 2169 func encodePv1014(v uint32) (uint32, bool) { 2170 return v << 10, true 2171 } 2172 2173 // encodePv59 is the implementation of the following encoding logic: 2174 // Is the name of the vector select predicate register, encoded in the "Pv" field. 2175 // bit range mappings: 2176 // Pv: [5:9) 2177 func encodePv59(v uint32) (uint32, bool) { 2178 return v << 5, true 2179 } 2180 2181 // encodeRd05ZR is the implementation of the following encoding logic: 2182 // Is the number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field. 2183 // bit range mappings: 2184 // Rd: [0:5) 2185 func encodeRd05ZR(v uint32) (uint32, bool) { 2186 if !checkIsR(v) { 2187 return 0, false 2188 } 2189 if v == REG_RSP { 2190 return 0, false 2191 } 2192 // ZR is just R31 2193 return v & 31, true 2194 } 2195 2196 // encodeRn510SPV1 is the implementation of the following encoding logic: 2197 // Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field. 2198 // bit range mappings: 2199 // Rn: [5:10) 2200 func encodeRn510SPV1(v uint32) (uint32, bool) { 2201 if !checkIsR(v) { 2202 return 0, false 2203 } 2204 if v == REG_R31 { 2205 return 0, false 2206 } 2207 if v == REG_RSP { 2208 return (REG_R31 & 31) << 5, true 2209 } 2210 return (v & 31) << 5, true 2211 } 2212 2213 // encodeRdn05ZR is the implementation of the following encoding logic: 2214 // Is the number [0-30] of the source and destination general-purpose register or the name ZR (31), encoded in the "Rdn" field. 2215 // bit range mappings: 2216 // Rdn: [0:5) 2217 func encodeRdn05ZR(v uint32) (uint32, bool) { 2218 if !checkIsR(v) { 2219 return 0, false 2220 } 2221 if v == REG_RSP { 2222 return 0, false 2223 } 2224 return v & 31, true 2225 } 2226 2227 // encodeRm1621ZR is the implementation of the following encoding logic: 2228 // Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field. 2229 // bit range mappings: 2230 // Rm: [16:21) 2231 func encodeRm1621ZR(v uint32) (uint32, bool) { 2232 if !checkIsR(v) { 2233 return 0, false 2234 } 2235 if v == REG_RSP { 2236 return 0, false 2237 } 2238 return (v & 31) << 16, true 2239 } 2240 2241 // encodeRm510ZR is the implementation of the following encoding logic: 2242 // Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field. 2243 // bit range mappings: 2244 // Rm: [5:10) 2245 func encodeRm510ZR(v uint32) (uint32, bool) { 2246 if !checkIsR(v) { 2247 return 0, false 2248 } 2249 if v == REG_RSP { 2250 return 0, false 2251 } 2252 return (v & 31) << 5, true 2253 } 2254 2255 // encodeRn510ZR is the implementation of the following encoding logic: 2256 // Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field. 2257 // bit range mappings: 2258 // Rn: [5:10) 2259 func encodeRn510ZR(v uint32) (uint32, bool) { 2260 if !checkIsR(v) { 2261 return 0, false 2262 } 2263 if v == REG_RSP { 2264 return 0, false 2265 } 2266 return (v & 31) << 5, true 2267 } 2268 2269 // encodeVd05 is the implementation of the following encoding logic: 2270 // Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field. 2271 // bit range mappings: 2272 // Vd: [0:5) 2273 func encodeVd05(v uint32) (uint32, bool) { 2274 return v & 31, true 2275 } 2276 2277 // encodeVm510 is the implementation of the following encoding logic: 2278 // Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field. 2279 // bit range mappings: 2280 // Vm: [5:10) 2281 func encodeVm510(v uint32) (uint32, bool) { 2282 return (v & 31) << 5, true 2283 } 2284 2285 // encodeVn510 is the implementation of the following encoding logic: 2286 // Is the number [0-31] of the source SIMD&FP register, encoded in the "Vn" field. 2287 // bit range mappings: 2288 // Vn: [5:10) 2289 func encodeVn510(v uint32) (uint32, bool) { 2290 return (v & 31) << 5, true 2291 } 2292 2293 // encodeVdn05 is the implementation of the following encoding logic: 2294 // Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field. 2295 // bit range mappings: 2296 // Vdn: [0:5) 2297 func encodeVdn05(v uint32) (uint32, bool) { 2298 return v & 31, true 2299 } 2300 2301 // encodeRm1621XZR is the implementation of the following encoding logic: 2302 // Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. 2303 // bit range mappings: 2304 // Rm: [16:21) 2305 func encodeRm1621XZR(v uint32) (uint32, bool) { 2306 if v == 0 { 2307 // absent case, according to the spec this should be ZR (R31) 2308 return 31, true 2309 } 2310 if !checkIsR(v) { 2311 return 0, false 2312 } 2313 return (v & 31) << 16, true 2314 } 2315 2316 // encodeImm41620V1 is the implementation of the following encoding logic: 2317 // Is the optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field. 2318 // bit range mappings: 2319 // imm4: [16:20) 2320 func encodeImm41620V1(v uint32) (uint32, bool) { 2321 vi := int32(v) 2322 if vi >= -128 && vi <= 112 && vi%16 == 0 { 2323 return uint32((vi/16)&15) << 16, true 2324 } 2325 return 0, false 2326 } 2327 2328 // encodeImm41620V2 is the implementation of the following encoding logic: 2329 // Is the optional signed immediate byte offset, a multiple of 32 in the range -256 to 224, defaulting to 0, encoded in the "imm4" field. 2330 // bit range mappings: 2331 // imm4: [16:20) 2332 func encodeImm41620V2(v uint32) (uint32, bool) { 2333 vi := int32(v) 2334 if vi >= -256 && vi <= 224 && vi%32 == 0 { 2335 return uint32((vi/32)&15) << 16, true 2336 } 2337 return 0, false 2338 } 2339 2340 // encodeImm41620V6 is the implementation of the following encoding logic: 2341 // Is the optional signed immediate vector offset, a multiple of 2 in the range -16 to 14, defaulting to 0, encoded in the "imm4" field. 2342 // bit range mappings: 2343 // imm4: [16:20) 2344 func encodeImm41620V6(v uint32) (uint32, bool) { 2345 if v&1 != 0 { 2346 return 0, false 2347 } 2348 vi := int32(v) 2349 if vi >= -16 && vi <= 14 { 2350 return (uint32(vi/2) & 15) << 16, true 2351 } 2352 return 0, false 2353 } 2354 2355 // encodeImm41620V3 is the implementation of the following encoding logic: 2356 // Is the optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field. 2357 // bit range mappings: 2358 // imm4: [16:20) 2359 func encodeImm41620V3(v uint32) (uint32, bool) { 2360 vi := int32(v) 2361 if vi >= -24 && vi <= 21 && vi%3 == 0 { 2362 return uint32((vi/3)&15) << 16, true 2363 } 2364 return 0, false 2365 } 2366 2367 // encodeImm41620V4 is the implementation of the following encoding logic: 2368 // Is the optional signed immediate vector offset, a multiple of 4 in the range -32 to 28, defaulting to 0, encoded in the "imm4" field. 2369 // bit range mappings: 2370 // imm4: [16:20) 2371 func encodeImm41620V4(v uint32) (uint32, bool) { 2372 vi := int32(v) 2373 if vi >= -32 && vi <= 28 && vi%4 == 0 { 2374 return uint32((vi/4)&15) << 16, true 2375 } 2376 return 0, false 2377 } 2378 2379 // encodeImm9h1622L1013 is the implementation of the following encoding logic: 2380 // Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. 2381 // bit range mappings: 2382 // imm9h: [16:22) 2383 // imm9l: [10:13) 2384 func encodeImm9h1622L1013(v uint32) (uint32, bool) { 2385 vi := int32(v) 2386 if vi >= -256 && vi <= 255 { 2387 val := uint32(vi) & 0x1FF 2388 return ((val & 7) << 10) | ((val >> 3) << 16), true 2389 } 2390 return 0, false 2391 } 2392 2393 // encodeImm61622V5 is the implementation of the following encoding logic: 2394 // Is the optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field. 2395 // bit range mappings: 2396 // imm6: [16:22) 2397 func encodeImm61622V5(v uint32) (uint32, bool) { 2398 vi := int32(v) 2399 if vi >= -32 && vi <= 31 { 2400 return (uint32(vi) & 0x3F) << 16, true 2401 } 2402 return 0, false 2403 } 2404 2405 // encodeImm41620V5 is the implementation of the following encoding logic: 2406 // Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field. 2407 // bit range mappings: 2408 // imm4: [16:20) 2409 func encodeImm41620V5(v uint32) (uint32, bool) { 2410 vi := int32(v) 2411 if vi >= -8 && vi <= 7 { 2412 return (uint32(vi) & 0xF) << 16, true 2413 } 2414 return 0, false 2415 } 2416 2417 // encodeImm61622V1 is the implementation of the following encoding logic: 2418 // Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field. 2419 // bit range mappings: 2420 // imm6: [16:22) 2421 func encodeImm61622V1(v uint32) (uint32, bool) { 2422 if v <= 126 && v%2 == 0 { 2423 return (v / 2) << 16, true 2424 } 2425 return 0, false 2426 } 2427 2428 // encodeImm51621V1 is the implementation of the following encoding logic: 2429 // Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field. 2430 // bit range mappings: 2431 // imm5: [16:21) 2432 func encodeImm51621V1(v uint32) (uint32, bool) { 2433 if v <= 62 && v%2 == 0 { 2434 return (v / 2) << 16, true 2435 } 2436 return 0, false 2437 } 2438 2439 // encodeImm51621V2 is the implementation of the following encoding logic: 2440 // Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 124, defaulting to 0, encoded in the "imm5" field. 2441 // bit range mappings: 2442 // imm5: [16:21) 2443 func encodeImm51621V2(v uint32) (uint32, bool) { 2444 if v <= 124 && v%4 == 0 { 2445 return (v / 4) << 16, true 2446 } 2447 return 0, false 2448 } 2449 2450 // encodeImm61622V2 is the implementation of the following encoding logic: 2451 // Is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 252, defaulting to 0, encoded in the "imm6" field. 2452 // bit range mappings: 2453 // imm6: [16:22) 2454 func encodeImm61622V2(v uint32) (uint32, bool) { 2455 if v <= 252 && v%4 == 0 { 2456 return (v / 4) << 16, true 2457 } 2458 return 0, false 2459 } 2460 2461 // encodeImm51621V3 is the implementation of the following encoding logic: 2462 // Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field. 2463 // bit range mappings: 2464 // imm5: [16:21) 2465 func encodeImm51621V3(v uint32) (uint32, bool) { 2466 if v <= 248 && v%8 == 0 { 2467 return (v / 8) << 16, true 2468 } 2469 return 0, false 2470 } 2471 2472 // encodeImm61622V3 is the implementation of the following encoding logic: 2473 // Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 504, defaulting to 0, encoded in the "imm6" field. 2474 // bit range mappings: 2475 // imm6: [16:22) 2476 func encodeImm61622V3(v uint32) (uint32, bool) { 2477 if v <= 504 && v%8 == 0 { 2478 return (v / 8) << 16, true 2479 } 2480 return 0, false 2481 } 2482 2483 // encodeImm51621V4 is the implementation of the following encoding logic: 2484 // Is the optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field. 2485 // bit range mappings: 2486 // imm5: [16:21) 2487 func encodeImm51621V4(v uint32) (uint32, bool) { 2488 if v <= 31 { 2489 return v << 16, true 2490 } 2491 return 0, false 2492 } 2493 2494 // encodeImm61622V4 is the implementation of the following encoding logic: 2495 // Is the optional unsigned immediate byte offset, in the range 0 to 63, defaulting to 0, encoded in the "imm6" field. 2496 // bit range mappings: 2497 // imm6: [16:22) 2498 func encodeImm61622V4(v uint32) (uint32, bool) { 2499 if v <= 63 { 2500 return v << 16, true 2501 } 2502 return 0, false 2503 } 2504 2505 // encodeI189 is the implementation of the following encoding logic: 2506 // Is the portion index, in the range 0 to 1, encoded in the "i1" field. 2507 // bit range mappings: 2508 // i1: [8:9) 2509 func encodeI189(v uint32) (uint32, bool) { 2510 if v > 1 { 2511 return 0, false 2512 } 2513 return v << 8, true 2514 } 2515 2516 // encodeImm2_810 is the implementation of the following encoding logic: 2517 // Is the portion index, in the range 0 to 3, encoded in the "imm2" field. 2518 // bit range mappings: 2519 // imm2: [8:10) 2520 func encodeImm2_810(v uint32) (uint32, bool) { 2521 if v > 3 { 2522 return 0, false 2523 } 2524 return v << 8, true 2525 } 2526 2527 // encodePredQualM1617 is the implementation of the following encoding logic: 2528 // Is the predication qualifier, 2529 // M <ZM> 2530 // 0 Z 2531 // 1 M 2532 // bit range mappings: 2533 // M: [16:17) 2534 func encodePredQualM1617(v uint32) (uint32, bool) { 2535 switch v { 2536 case PRED_Z: 2537 return 0, true 2538 case PRED_M: 2539 return 1 << 16, true 2540 } 2541 return 0, false 2542 } 2543 2544 // encodePredQualM45 is the implementation of the following encoding logic: 2545 // Is the predication qualifier, 2546 // M <ZM> 2547 // 0 Z 2548 // 1 M 2549 // bit range mappings: 2550 // M: [4:5) 2551 func encodePredQualM45(v uint32) (uint32, bool) { 2552 switch v { 2553 case PRED_Z: 2554 return 0, true 2555 case PRED_M: 2556 return 1 << 4, true 2557 } 2558 return 0, false 2559 } 2560 2561 // encodePrfop04 is the implementation of the following encoding logic: 2562 // Is the prefetch operation specifier, 2563 // prfop <prfop> 2564 // 0000 PLDL1KEEP 2565 // 0001 PLDL1STRM 2566 // 0010 PLDL2KEEP 2567 // 0011 PLDL2STRM 2568 // 0100 PLDL3KEEP 2569 // 0101 PLDL3STRM 2570 // x11x #uimm4 2571 // 1000 PSTL1KEEP 2572 // 1001 PSTL1STRM 2573 // 1010 PSTL2KEEP 2574 // 1011 PSTL2STRM 2575 // 1100 PSTL3KEEP 2576 // 1101 PSTL3STRM 2577 // bit range mappings: 2578 // prfop: [0:4) 2579 func encodePrfop04(v uint32) (uint32, bool) { 2580 switch SpecialOperand(v) { 2581 case SPOP_PLDL1KEEP: 2582 return 0, true 2583 case SPOP_PLDL1STRM: 2584 return 1, true 2585 case SPOP_PLDL2KEEP: 2586 return 2, true 2587 case SPOP_PLDL2STRM: 2588 return 3, true 2589 case SPOP_PLDL3KEEP: 2590 return 4, true 2591 case SPOP_PLDL3STRM: 2592 return 5, true 2593 case SPOP_PSTL1KEEP: 2594 return 8, true 2595 case SPOP_PSTL1STRM: 2596 return 9, true 2597 case SPOP_PSTL2KEEP: 2598 return 10, true 2599 case SPOP_PSTL2STRM: 2600 return 11, true 2601 case SPOP_PSTL3KEEP: 2602 return 12, true 2603 case SPOP_PSTL3STRM: 2604 return 13, true 2605 default: 2606 return 0, false 2607 } 2608 } 2609 2610 // encodeI21921 is the implementation of the following encoding logic: 2611 // Is the round key index, in the range 0 to 3, encoded in the "i2" field. 2612 // bit range mappings: 2613 // i2: [19:21) 2614 func encodeI21921(v uint32) (uint32, bool) { 2615 if v > 3 { 2616 return 0, false 2617 } 2618 return v << 19, true 2619 } 2620 2621 // encodeImm5bSigned_1621 is the implementation of the following encoding logic: 2622 // Is the second signed immediate operand, in the range -16 to 15, encoded in the "imm5b" field. 2623 // bit range mappings: 2624 // imm5b: [16:21) 2625 func encodeImm5bSigned_1621(v uint32) (uint32, bool) { 2626 if int32(v) >= -16 && int32(v) <= 15 { 2627 return (v & 31) << 16, true 2628 } 2629 return 0, false 2630 } 2631 2632 // encodeImm8Signed_513 is the implementation of the following encoding logic: 2633 // Is the signed immediate operand, in the range -128 to 127, encoded in the "imm8" field. 2634 // bit range mappings: 2635 // imm8: [5:13) 2636 func encodeImm8Signed_513(v uint32) (uint32, bool) { 2637 if int32(v) >= -128 && int32(v) <= 127 { 2638 return (v & 255) << 5, true 2639 } 2640 return 0, false 2641 } 2642 2643 // encodeImm5Signed_1621V1 is the implementation of the following encoding logic: 2644 // Is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. 2645 // bit range mappings: 2646 // imm5: [16:21) 2647 func encodeImm5Signed_1621V1(v uint32) (uint32, bool) { 2648 if int32(v) >= -16 && int32(v) <= 15 { 2649 return (v & 31) << 16, true 2650 } 2651 return 0, false 2652 } 2653 2654 // encodeImm5Signed510Unique is the implementation of the following encoding logic: 2655 // Is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field. 2656 // bit range mappings: 2657 // imm5: [5:10) 2658 func encodeImm5Signed510Unique(v uint32) (uint32, bool) { 2659 if int32(v) >= -16 && int32(v) <= 15 { 2660 return (v & 31) << 5, true 2661 } 2662 return 0, false 2663 } 2664 2665 // encodeImm6Signed_511 is the implementation of the following encoding logic: 2666 // Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field. 2667 // bit range mappings: 2668 // imm6: [5:11) 2669 func encodeImm6Signed_511(v uint32) (uint32, bool) { 2670 if int32(v) >= -32 && int32(v) <= 31 { 2671 return (v & 63) << 5, true 2672 } 2673 return 0, false 2674 } 2675 2676 // encodeSizeImm13NoOp is the implementation of the following encoding logic: 2677 // Is the size specifier, 2678 // imm13 <T> 2679 // 0xxxxxx0xxxxx S 2680 // 0xxxxxx10xxxx H 2681 // 0xxxxxx110xxx B 2682 // 0xxxxxx1110xx B 2683 // 0xxxxxx11110x B 2684 // 0xxxxxx11111x RESERVED 2685 // 1xxxxxxxxxxxx D 2686 // bit range mappings: 2687 // imm13: [5:18) 2688 func encodeSizeImm13NoOp(v uint32) (uint32, bool) { 2689 return codeNoOp, false 2690 } 2691 2692 // encodeSize2123V1 is the implementation of the following encoding logic: 2693 // Is the size specifier, 2694 // size <T> 2695 // 00 B 2696 // 01 H 2697 // 10 S 2698 // 11 D 2699 // bit range mappings: 2700 // size: [21:23) 2701 func encodeSize2123V1(v uint32) (uint32, bool) { 2702 switch v { 2703 case ARNG_B: 2704 return 0, true 2705 case ARNG_H: 2706 return 1 << 21, true 2707 case ARNG_S: 2708 return 2 << 21, true 2709 case ARNG_D: 2710 return 3 << 21, true 2711 default: 2712 return 0, false 2713 } 2714 } 2715 2716 // encodeSizeBHSD2224 is the implementation of the following encoding logic: 2717 // Is the size specifier, 2718 // size <T> 2719 // 00 B 2720 // 01 H 2721 // 10 S 2722 // 11 D 2723 // bit range mappings: 2724 // size: [22:24) 2725 func encodeSizeBHSD2224(v uint32) (uint32, bool) { 2726 switch v { 2727 case ARNG_B: 2728 return 0 << 22, true 2729 case ARNG_H: 2730 return 1 << 22, true 2731 case ARNG_S: 2732 return 2 << 22, true 2733 case ARNG_D: 2734 return 3 << 22, true 2735 } 2736 return 0, false 2737 } 2738 2739 // encodeSizeBHS2224 is the implementation of the following encoding logic: 2740 // Is the size specifier, 2741 // size <T> 2742 // 00 B 2743 // 01 H 2744 // 10 S 2745 // 11 RESERVED 2746 // bit range mappings: 2747 // size: [22:24) 2748 func encodeSizeBHS2224(v uint32) (uint32, bool) { 2749 switch v { 2750 case ARNG_B: 2751 return 0 << 22, true 2752 case ARNG_H: 2753 return 1 << 22, true 2754 case ARNG_S: 2755 return 2 << 22, true 2756 } 2757 return 0, false 2758 } 2759 2760 // encodeSizeBHS2224Offset1 is the implementation of the following encoding logic: 2761 // Is the size specifier, 2762 // size <T> 2763 // 00 RESERVED 2764 // 01 B 2765 // 10 H 2766 // 11 S 2767 // bit range mappings: 2768 // size: [22:24) 2769 func encodeSizeBHS2224Offset1(v uint32) (uint32, bool) { 2770 switch v { 2771 case ARNG_B: 2772 return 1 << 22, true 2773 case ARNG_H: 2774 return 2 << 22, true 2775 case ARNG_S: 2776 return 3 << 22, true 2777 } 2778 return 0, false 2779 } 2780 2781 // encodeSizeHSD1315 is the implementation of the following encoding logic: 2782 // Is the size specifier, 2783 // size <T> 2784 // 00 RESERVED 2785 // 01 H 2786 // 10 S 2787 // 11 D 2788 // bit range mappings: 2789 // size: [13:15) 2790 func encodeSizeHSD1315(v uint32) (uint32, bool) { 2791 switch v { 2792 case ARNG_H: 2793 return 1 << 13, true 2794 case ARNG_S: 2795 return 2 << 13, true 2796 case ARNG_D: 2797 return 3 << 13, true 2798 } 2799 return 0, false 2800 } 2801 2802 // encodeSizeHSD1719 is the implementation of the following encoding logic: 2803 // Is the size specifier, 2804 // size <T> 2805 // 00 RESERVED 2806 // 01 H 2807 // 10 S 2808 // 11 D 2809 // bit range mappings: 2810 // size: [17:19) 2811 func encodeSizeHSD1719(v uint32) (uint32, bool) { 2812 switch v { 2813 case ARNG_H: 2814 return 1 << 17, true 2815 case ARNG_S: 2816 return 2 << 17, true 2817 case ARNG_D: 2818 return 3 << 17, true 2819 } 2820 return 0, false 2821 } 2822 2823 // encodeSize2123V2 is the implementation of the following encoding logic: 2824 // Is the size specifier, 2825 // size <T> 2826 // 00 RESERVED 2827 // 01 H 2828 // 10 S 2829 // 11 D 2830 // bit range mappings: 2831 // size: [21:23) 2832 func encodeSize2123V2(v uint32) (uint32, bool) { 2833 switch v { 2834 case ARNG_H: 2835 return 1 << 21, true 2836 case ARNG_S: 2837 return 2 << 21, true 2838 case ARNG_D: 2839 return 3 << 21, true 2840 } 2841 return 0, false 2842 } 2843 2844 // encodeSizeHSD2224 is the implementation of the following encoding logic: 2845 // Is the size specifier, 2846 // size <T> 2847 // 00 RESERVED 2848 // 01 H 2849 // 10 S 2850 // 11 D 2851 // bit range mappings: 2852 // size: [22:24) 2853 func encodeSizeHSD2224(v uint32) (uint32, bool) { 2854 switch v { 2855 case ARNG_H: 2856 return 1 << 22, true 2857 case ARNG_S: 2858 return 2 << 22, true 2859 case ARNG_D: 2860 return 3 << 22, true 2861 } 2862 return 0, false 2863 } 2864 2865 // encodeSizeHSD2224No00 is the implementation of the following encoding logic: 2866 // Is the size specifier, 2867 // size <T> 2868 // 01 H 2869 // 10 S 2870 // 11 D 2871 // bit range mappings: 2872 // size: [22:24) 2873 func encodeSizeHSD2224No00(v uint32) (uint32, bool) { 2874 switch v { 2875 case ARNG_H: 2876 return 1 << 22, true 2877 case ARNG_S: 2878 return 2 << 22, true 2879 case ARNG_D: 2880 return 3 << 22, true 2881 } 2882 return 0, false 2883 } 2884 2885 // encodeSizeHD2224 is the implementation of the following encoding logic: 2886 // Is the size specifier, 2887 // size <T> 2888 // 01 H 2889 // 1x D 2890 // bit range mappings: 2891 // size: [22:24) 2892 func encodeSizeHD2224(v uint32) (uint32, bool) { 2893 switch v { 2894 case ARNG_H: 2895 return 1 << 22, true 2896 case ARNG_D: 2897 return 3 << 22, true 2898 } 2899 return 0, false 2900 } 2901 2902 // encodeSizeTbBHSD2224 is the implementation of the following encoding logic: 2903 // Is the size specifier, 2904 // size <Tb> 2905 // 00 B 2906 // 01 H 2907 // 10 S 2908 // 11 D 2909 // bit range mappings: 2910 // size: [22:24) 2911 func encodeSizeTbBHSD2224(v uint32) (uint32, bool) { 2912 switch v { 2913 case ARNG_B: 2914 return 0 << 22, true 2915 case ARNG_H: 2916 return 1 << 22, true 2917 case ARNG_S: 2918 return 2 << 22, true 2919 case ARNG_D: 2920 return 3 << 22, true 2921 } 2922 return 0, false 2923 } 2924 2925 // encodeSizeTbBHS2224 is the implementation of the following encoding logic: 2926 // Is the size specifier, 2927 // size <Tb> 2928 // 00 RESERVED 2929 // 01 B 2930 // 10 H 2931 // 11 S 2932 // bit range mappings: 2933 // size: [22:24) 2934 func encodeSizeTbBHS2224(v uint32) (uint32, bool) { 2935 switch v { 2936 case ARNG_B: 2937 return 1 << 22, true 2938 case ARNG_H: 2939 return 2 << 22, true 2940 case ARNG_S: 2941 return 3 << 22, true 2942 } 2943 return 0, false 2944 } 2945 2946 // encodeSizeTbHSD2224Offset1 is the implementation of the following encoding logic: 2947 // Is the size specifier, 2948 // size <Tb> 2949 // 00 RESERVED 2950 // 01 H 2951 // 10 S 2952 // 11 D 2953 // bit range mappings: 2954 // size: [22:24) 2955 func encodeSizeTbHSD2224Offset1(v uint32) (uint32, bool) { 2956 switch v { 2957 case ARNG_H: 2958 return 1 << 22, true 2959 case ARNG_S: 2960 return 2 << 22, true 2961 case ARNG_D: 2962 return 3 << 22, true 2963 } 2964 return 0, false 2965 } 2966 2967 // encodeSizeTbBS2224 is the implementation of the following encoding logic: 2968 // Is the size specifier, 2969 // size <Tb> 2970 // 01 B 2971 // 1x S 2972 // bit range mappings: 2973 // size: [22:24) 2974 func encodeSizeTbBS2224(v uint32) (uint32, bool) { 2975 switch v { 2976 case ARNG_B: 2977 return 1 << 22, true 2978 case ARNG_S: 2979 return 3 << 22, true 2980 } 2981 return 0, false 2982 } 2983 2984 // encodeSize0BH2223 is the implementation of the following encoding logic: 2985 // Is the size specifier, 2986 // size[0] <T> 2987 // 0 B 2988 // 1 H 2989 // bit range mappings: 2990 // size: [22:23) 2991 func encodeSize0BH2223(v uint32) (uint32, bool) { 2992 switch v { 2993 case ARNG_B: 2994 return 0 << 22, true 2995 case ARNG_H: 2996 return 1 << 22, true 2997 } 2998 return 0, false 2999 } 3000 3001 // encodeSize0SD2223 is the implementation of the following encoding logic: 3002 // Is the size specifier, 3003 // size[0] <T> 3004 // 0 S 3005 // 1 D 3006 // bit range mappings: 3007 // size: [22:23) 3008 func encodeSize0SD2223(v uint32) (uint32, bool) { 3009 switch v { 3010 case ARNG_S: 3011 return 0 << 22, true 3012 case ARNG_D: 3013 return 1 << 22, true 3014 } 3015 return 0, false 3016 } 3017 3018 // encodeSize0TbBH2223 is the implementation of the following encoding logic: 3019 // Is the size specifier, 3020 // size[0] <Tb> 3021 // 0 B 3022 // 1 H 3023 // bit range mappings: 3024 // size: [22:23) 3025 func encodeSize0TbBH2223(v uint32) (uint32, bool) { 3026 switch v { 3027 case ARNG_B: 3028 return 0 << 22, true 3029 case ARNG_H: 3030 return 1 << 22, true 3031 } 3032 return 0, false 3033 } 3034 3035 // encodeSzSD1415 is the implementation of the following encoding logic: 3036 // Is the size specifier, 3037 // sz <T> 3038 // 0 S 3039 // 1 D 3040 // bit range mappings: 3041 // sz: [14:15) 3042 func encodeSzSD1415(v uint32) (uint32, bool) { 3043 switch v { 3044 case ARNG_S: 3045 return 0 << 14, true 3046 case ARNG_D: 3047 return 1 << 14, true 3048 } 3049 return 0, false 3050 } 3051 3052 // encodeSzSD1718 is the implementation of the following encoding logic: 3053 // Is the size specifier, 3054 // sz <T> 3055 // 0 S 3056 // 1 D 3057 // bit range mappings: 3058 // sz: [17:18) 3059 func encodeSzSD1718(v uint32) (uint32, bool) { 3060 switch v { 3061 case ARNG_S: 3062 return 0 << 17, true 3063 case ARNG_D: 3064 return 1 << 17, true 3065 } 3066 return 0, false 3067 } 3068 3069 // encodeSz2122 is the implementation of the following encoding logic: 3070 // Is the size specifier, 3071 // sz <T> 3072 // 0 S 3073 // 1 D 3074 // bit range mappings: 3075 // sz: [21:22) 3076 func encodeSz2122(v uint32) (uint32, bool) { 3077 switch v { 3078 case ARNG_S: 3079 return 0, true 3080 case ARNG_D: 3081 return 1 << 21, true 3082 } 3083 return 0, false 3084 } 3085 3086 // encodeSzSD2223 is the implementation of the following encoding logic: 3087 // Is the size specifier, 3088 // sz <T> 3089 // 0 S 3090 // 1 D 3091 // bit range mappings: 3092 // sz: [22:23) 3093 func encodeSzSD2223(v uint32) (uint32, bool) { 3094 switch v { 3095 case ARNG_S: 3096 return 0 << 22, true 3097 case ARNG_D: 3098 return 1 << 22, true 3099 } 3100 return 0, false 3101 } 3102 3103 // encodeTsize1921V1 is the implementation of the following encoding logic: 3104 // Is the size specifier, 3105 // tsize <T> 3106 // 00 RESERVED 3107 // 01 B 3108 // 1x H 3109 // bit range mappings: 3110 // tsize: [19:21) 3111 func encodeTsize1921V1(v uint32) (uint32, bool) { 3112 if v == uint32(ARNG_B) { 3113 return 1 << 19, true 3114 } 3115 if v == uint32(ARNG_H) { 3116 return 2 << 19, true // 2 is bit pattern 10 (1x) 3117 } 3118 return 0, false 3119 } 3120 3121 // encodeTsize1921V2 is the implementation of the following encoding logic: 3122 // Is the size specifier, 3123 // tsize <Tb> 3124 // 00 RESERVED 3125 // 01 H 3126 // 1x S 3127 // bit range mappings: 3128 // tsize: [19:21) 3129 func encodeTsize1921V2(v uint32) (uint32, bool) { 3130 if v == uint32(ARNG_H) { 3131 return 1 << 19, true 3132 } 3133 if v == uint32(ARNG_S) { 3134 return 2 << 19, true // 2 is bit pattern 10 (1x) 3135 } 3136 return 0, false 3137 } 3138 3139 // encodeTsz_1620_SizeSpecifier4 is the implementation of the following encoding logic: 3140 // Is the size specifier, 3141 // tsz <T> 3142 // 0000 RESERVED 3143 // xxx1 B 3144 // xx10 H 3145 // x100 S 3146 // 1000 D 3147 // bit range mappings: 3148 // tsz: [16:20) 3149 func encodeTsz_1620_SizeSpecifier4(v uint32) (uint32, bool) { 3150 switch v { 3151 case ARNG_B: 3152 return 1 << 16, true 3153 case ARNG_H: 3154 return 2 << 16, true 3155 case ARNG_S: 3156 return 4 << 16, true 3157 case ARNG_D: 3158 return 8 << 16, true 3159 } 3160 return 0, false 3161 } 3162 3163 // encodeTsz_1621_SizeSpecifier5 is the implementation of the following encoding logic: 3164 // Is the size specifier, 3165 // tsz <T> 3166 // 00000 RESERVED 3167 // xxxx1 B 3168 // xxx10 H 3169 // xx100 S 3170 // x1000 D 3171 // 10000 Q 3172 // bit range mappings: 3173 // tsz: [16:21) 3174 func encodeTsz_1621_SizeSpecifier5(v uint32) (uint32, bool) { 3175 switch v { 3176 case ARNG_B: 3177 return 1 << 16, true 3178 case ARNG_H: 3179 return 2 << 16, true 3180 case ARNG_S: 3181 return 4 << 16, true 3182 case ARNG_D: 3183 return 8 << 16, true 3184 case ARNG_Q: 3185 return 16 << 16, true 3186 } 3187 return 0, false 3188 } 3189 3190 // encodeTszhTszlBHS is the implementation of the following encoding logic: 3191 // Is the size specifier, 3192 // tszh tszl <T> 3193 // 0 00 RESERVED 3194 // 0 01 B 3195 // 0 10 H 3196 // 0 11 RESERVED 3197 // 1 00 S 3198 // 1 01 RESERVED 3199 // 1 1x RESERVED 3200 // bit range mappings: 3201 // tszh: [22:23) 3202 // tszl: [19:21) 3203 func encodeTszhTszlBHS(v uint32) (uint32, bool) { 3204 switch v { 3205 case ARNG_B: 3206 return 0<<22 | 1<<19, true 3207 case ARNG_H: 3208 return 0<<22 | 2<<19, true 3209 case ARNG_S: 3210 return 1 << 22, true 3211 } 3212 return 0, false 3213 } 3214 3215 // encodeSizeBhsTsz1921 is the implementation of the following encoding logic: 3216 // Is the size specifier, 3217 // tszh tszl <T> 3218 // 0 00 RESERVED 3219 // 0 01 B 3220 // 0 1x H 3221 // 1 xx S 3222 // bit range mappings: 3223 // tszh: [22:23) 3224 // tszl: [19:21) 3225 func encodeSizeBhsTsz1921(v uint32) (uint32, bool) { 3226 switch v { 3227 case ARNG_B: 3228 return 1 << 19, true 3229 case ARNG_H: 3230 return 2 << 19, true 3231 case ARNG_S: 3232 return 1 << 22, true 3233 } 3234 return 0, false 3235 } 3236 3237 // encodeSizeHsdTsz1921 is the implementation of the following encoding logic: 3238 // Is the size specifier, 3239 // tszh tszl <T> 3240 // 0 00 RESERVED 3241 // 0 01 H 3242 // 0 1x S 3243 // 1 xx D 3244 // bit range mappings: 3245 // tszh: [22:23) 3246 // tszl: [19:21) 3247 func encodeSizeHsdTsz1921(v uint32) (uint32, bool) { 3248 switch v { 3249 case ARNG_H: 3250 return 1 << 19, true 3251 case ARNG_S: 3252 return 2 << 19, true 3253 case ARNG_D: 3254 return 1 << 22, true 3255 } 3256 return 0, false 3257 } 3258 3259 // encodeSizeBhsdTsz1921 is the implementation of the following encoding logic: 3260 // Is the size specifier, 3261 // tszh tszl <T> 3262 // 00 00 RESERVED 3263 // 00 01 B 3264 // 00 1x H 3265 // 01 xx S 3266 // 1x xx D 3267 // bit range mappings: 3268 // tszh: [22:24) 3269 // tszl: [19:21) 3270 func encodeSizeBhsdTsz1921(v uint32) (uint32, bool) { 3271 switch v { 3272 case ARNG_B: 3273 return 1 << 19, true 3274 case ARNG_H: 3275 return 2 << 19, true 3276 case ARNG_S: 3277 return 1 << 22, true 3278 case ARNG_D: 3279 return 1 << 23, true 3280 } 3281 return 0, false 3282 } 3283 3284 // encodeSizeBhsdTsz810 is the implementation of the following encoding logic: 3285 // Is the size specifier, 3286 // tszh tszl <T> 3287 // 00 00 RESERVED 3288 // 00 01 B 3289 // 00 1x H 3290 // 01 xx S 3291 // 1x xx D 3292 // bit range mappings: 3293 // tszh: [22:24) 3294 // tszl: [8:10) 3295 func encodeSizeBhsdTsz810(v uint32) (uint32, bool) { 3296 switch v { 3297 case ARNG_B: 3298 return 1 << 8, true 3299 case ARNG_H: 3300 return 2 << 8, true 3301 case ARNG_S: 3302 return 1 << 22, true 3303 case ARNG_D: 3304 return 1 << 23, true 3305 } 3306 return 0, false 3307 } 3308 3309 // encodeSizeBhsTsz1921Unique is the implementation of the following encoding logic: 3310 // Is the size specifier, 3311 // tszh tszl <Tb> 3312 // 0 00 RESERVED 3313 // 0 01 B 3314 // 0 1x H 3315 // 1 xx S 3316 // bit range mappings: 3317 // tszh: [22:23) 3318 // tszl: [19:21) 3319 func encodeSizeBhsTsz1921Unique(v uint32) (uint32, bool) { 3320 switch v { 3321 case ARNG_B: 3322 return 1 << 19, true 3323 case ARNG_H: 3324 return 2 << 19, true 3325 case ARNG_S: 3326 return 1 << 22, true 3327 } 3328 return 0, false 3329 } 3330 3331 // encodeTszhTszlTbHSD is the implementation of the following encoding logic: 3332 // Is the size specifier, 3333 // tszh tszl <Tb> 3334 // 0 00 RESERVED 3335 // 0 01 H 3336 // 0 10 S 3337 // 0 11 RESERVED 3338 // 1 00 D 3339 // 1 01 RESERVED 3340 // 1 1x RESERVED 3341 // bit range mappings: 3342 // tszh: [22:23) 3343 // tszl: [19:21) 3344 func encodeTszhTszlTbHSD(v uint32) (uint32, bool) { 3345 switch v { 3346 case ARNG_H: 3347 return 0<<22 | 1<<19, true 3348 case ARNG_S: 3349 return 0<<22 | 2<<19, true 3350 case ARNG_D: 3351 return 1 << 22, true 3352 } 3353 return 0, false 3354 } 3355 3356 // encodeSizeHsdTsz1921Unique is the implementation of the following encoding logic: 3357 // Is the size specifier, 3358 // tszh tszl <Tb> 3359 // 0 00 RESERVED 3360 // 0 01 H 3361 // 0 1x S 3362 // 1 xx D 3363 // bit range mappings: 3364 // tszh: [22:23) 3365 // tszl: [19:21) 3366 func encodeSizeHsdTsz1921Unique(v uint32) (uint32, bool) { 3367 switch v { 3368 case ARNG_H: 3369 return 1 << 19, true 3370 case ARNG_S: 3371 return 2 << 19, true 3372 case ARNG_D: 3373 return 1 << 22, true 3374 } 3375 return 0, false 3376 } 3377 3378 // encodeImm4Unsigned_1620 is the implementation of the following encoding logic: 3379 // Is the unsigned immediate operand, in the range 0 to 15, encoded in the "imm4" field. 3380 // bit range mappings: 3381 // imm4: [16:20) 3382 func encodeImm4Unsigned_1620(v uint32) (uint32, bool) { 3383 if v <= 15 { 3384 return v << 16, true 3385 } 3386 return 0, false 3387 } 3388 3389 // encodeImm8Unsigned_513 is the implementation of the following encoding logic: 3390 // Is the unsigned immediate operand, in the range 0 to 255, encoded in the "imm8" field. 3391 // bit range mappings: 3392 // imm8: [5:13) 3393 func encodeImm8Unsigned_513(v uint32) (uint32, bool) { 3394 if v <= 255 { 3395 return v << 5, true 3396 } 3397 return 0, false 3398 } 3399 3400 // encodeImm8hImm8l_Unsigned is the implementation of the following encoding logic: 3401 // Is the unsigned immediate operand, in the range 0 to 255, encoded in the "imm8h:imm8l" fields. 3402 // bit range mappings: 3403 // imm8h: [16:21) 3404 // imm8l: [10:13) 3405 func encodeImm8hImm8l_Unsigned(v uint32) (uint32, bool) { 3406 if v <= 255 { 3407 l := v & 7 3408 h := v >> 3 3409 return (l << 10) | (h << 16), true 3410 } 3411 return 0, false 3412 } 3413 3414 // encodeImm3Unsigned_1619 is the implementation of the following encoding logic: 3415 // Is the unsigned immediate operand, in the range 0 to 7, encoded in the "imm3" field. 3416 // bit range mappings: 3417 // imm3: [16:19) 3418 func encodeImm3Unsigned_1619(v uint32) (uint32, bool) { 3419 if v <= 7 { 3420 return v << 16, true 3421 } 3422 return 0, false 3423 } 3424 3425 // encodeI12324 is the implementation of the following encoding logic: 3426 // Is the vector segment index, in the range 0 to 1, encoded in the "i1" field. 3427 // bit range mappings: 3428 // i1: [23:24) 3429 func encodeI12324(v uint32) (uint32, bool) { 3430 if v > 1 { 3431 return 0, false 3432 } 3433 return v << 23, true 3434 } 3435 3436 // encodeVl1011 is the implementation of the following encoding logic: 3437 // Is the vl specifier, 3438 // vl <vl> 3439 // 0 VLx2 3440 // 1 VLx4 3441 // bit range mappings: 3442 // vl: [10:11) 3443 func encodeVl1011(v uint32) (uint32, bool) { 3444 switch SpecialOperand(v) { 3445 case SPOP_VLx2: 3446 return 0, true 3447 case SPOP_VLx4: 3448 return 1 << 10, true 3449 default: 3450 return 0, false 3451 } 3452 } 3453 3454 // encodeVl1314 is the implementation of the following encoding logic: 3455 // Is the vl specifier, 3456 // vl <vl> 3457 // 0 VLx2 3458 // 1 VLx4 3459 // bit range mappings: 3460 // vl: [13:14) 3461 func encodeVl1314(v uint32) (uint32, bool) { 3462 switch SpecialOperand(v) { 3463 case SPOP_VLx2: 3464 return 0, true 3465 case SPOP_VLx4: 3466 return 1 << 13, true 3467 default: 3468 return 0, false 3469 } 3470 } 3471 3472 // encodeNoop is the implementation of the following encoding logic: 3473 // No-op check, returns true 3474 func encodeNoop(v uint32) (uint32, bool) { 3475 return 0, true 3476 } 3477